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---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY SID_f_distortion IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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STATE : IN SIGNED(17 downto 8); -- Voltage of filter, which should not impact F
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F_RAW : IN UNSIGNED(12 downto 0); -- Wanted F, scaled to same units as voltage of filter
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F_DISTORTED : OUT UNSIGNED(12 downto 0) --Result F
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);
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END SID_f_distortion;
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ARCHITECTURE vhdl OF SID_f_distortion IS
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signal y1 : unsigned(12 downto 0);
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signal y1_reg : unsigned(12 downto 0);
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signal y2 : unsigned(12 downto 0);
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signal ych : unsigned(12 downto 0);
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signal yadj_next : unsigned(25 downto 0);
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signal yadj_reg : unsigned(25 downto 0);
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signal ychpos : unsigned(12 downto 0);
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signal f_distorted_next : unsigned(12 downto 0);
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signal STATE_next : SIGNED(17 downto 8);
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signal STATE_reg : SIGNED(17 downto 8);
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signal F_RAW_next : UNSIGNED(12 downto 0);
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signal F_RAW_reg : UNSIGNED(12 downto 0);
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begin
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-- register
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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y1_reg <= (others=>'0');
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yadj_reg <= (others=>'0');
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state_reg <= (others=>'0');
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f_raw_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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y1_reg <= y1;
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yadj_reg <= yadj_next;
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state_reg <= state_next;
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f_raw_reg <= f_raw_next;
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end if;
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end process;
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state_next <= state;
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f_raw_next <= f_raw;
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process (state_reg,f_raw_reg, y1, y2, ych, ychpos, y1_reg, yadj_reg)
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type LOOKUP_TYPE is array (0 to 38) of unsigned(12 downto 0);
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variable lookup : LOOKUP_TYPE;
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variable pos: unsigned(18 downto 5);
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begin
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-- assumption: /home/markw/fpga/svn/jsidplay2-code/jsidplay2/src/main/java/builder/resid/residfp/Filter6581.java
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pos := (others=>'0');
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if (state_reg(17)='0') then
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pos := unsigned('0'&state_reg(16 downto 8)&"000"&"0") + resize('0'&f_raw_reg,14);
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end if;
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if (pos(18 downto 12) > to_unsigned(37,6)) then
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pos(18) := '0';
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pos(17 downto 12) := to_unsigned(37,6);
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pos(11 downto 5) := (others=>'1');
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end if;
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-- replace with piecewise interp. Takes a mul unit but saves lookup space.
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lookup := (
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"0000001000100","0000001000101","0000001000110","0000001001000","0000001001011","0000001001111","0000001010110","0000001100000","0000001110000","0000010001000","0000010101011","0000011100000","0000100101111","0000110100001","0001001000101","0001100101001","0010001011000","0010111010111","0011110011010","0100110000111","0101101110011","0110100110111","0111010110110","0111111100110","1000011001001","1000101101110","1000111100001","1001000101111","1001001100100","1001010001000","1001010100000","1001010101111","1001010111010","1001011000001","1001011000101","1001011001000","1001011001010","1001011001011","1001011001100");
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ychpos <= resize(pos(11 downto 5)&"00000",13);
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y1 <= lookup(to_integer(pos(17 downto 12)));
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y2 <= lookup(to_integer(pos(17 downto 12))+1);
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ych <= y2-y1;
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yadj_next <= ych * ychpos;
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f_distorted_next <= y1_reg + resize(yadj_reg(25 downto 12),13);
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end process;
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-- output
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f_distorted <= f_distorted_next;
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end vhdl;
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