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Revision 473

Added by markw over 8 years ago

Port of reverseU16 HDMI test, running over GPIO pins

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eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.qsf
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
# Date created = 20:32:21 July 11, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# atari800core_eclaireXL_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name TOP_LEVEL_ENTITY atari800core_eclaireXL
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:21 JULY 11, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_FILE atari800core_eclaireXL.vhd
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name VHDL_FILE atari800core_de1.vhd
set_global_assignment -name QIP_FILE pll2.qip
set_location_assignment PIN_H16 -to CLOCK_5
set_location_assignment PIN_C9 -to VGA_BLANK_N
set_location_assignment PIN_G11 -to VGA_CLK
set_location_assignment PIN_C11 -to VGA_HS
set_location_assignment PIN_H11 -to VGA_VS
set_location_assignment PIN_J11 -to AUDIO_LEFT
set_location_assignment PIN_A12 -to AUDIO_RIGHT
set_location_assignment PIN_B12 -to GPIOC[0]
set_location_assignment PIN_D12 -to GPIOC[1]
set_location_assignment PIN_E12 -to GPIOC[2]
set_location_assignment PIN_F12 -to GPIOC[3]
set_location_assignment PIN_A13 -to GPIOC[4]
set_location_assignment PIN_B13 -to GPIOC[5]
set_location_assignment PIN_D13 -to GPIOC[6]
set_location_assignment PIN_C13 -to GPIOC[7]
set_location_assignment PIN_F13 -to GPIOC[8]
set_location_assignment PIN_G13 -to GPIOC[9]
set_location_assignment PIN_A14 -to GPIOC[10]
set_location_assignment PIN_E14 -to GPIOC[11]
set_location_assignment PIN_F14 -to GPIOC[12]
set_location_assignment PIN_H14 -to GPIOC[13]
set_location_assignment PIN_A15 -to GPIOC[14]
set_location_assignment PIN_B15 -to GPIOC[15]
set_location_assignment PIN_E15 -to GPIOC[16]
set_location_assignment PIN_C15 -to GPIOC[17]
set_location_assignment PIN_F15 -to GPIOA[0]
set_location_assignment PIN_G15 -to GPIOB[0]
set_location_assignment PIN_B16 -to GPIOA[1]
set_location_assignment PIN_E16 -to GPIOB[1]
set_location_assignment PIN_C16 -to GPIOA[2]
set_location_assignment PIN_D17 -to GPIOB[2]
set_location_assignment PIN_G17 -to GPIOA[3]
set_location_assignment PIN_G18 -to GPIOB[3]
set_location_assignment PIN_G16 -to GPIOA[4]
set_location_assignment PIN_H18 -to GPIOB[4]
set_location_assignment PIN_J18 -to GPIOA[5]
set_location_assignment PIN_J19 -to GPIOB[5]
set_location_assignment PIN_J17 -to GPIOA[6]
set_location_assignment PIN_K22 -to GPIOB[6]
set_location_assignment PIN_K21 -to GPIOA[7]
set_location_assignment PIN_K19 -to GPIOB[7]
set_location_assignment PIN_K20 -to GPIOA[8]
set_location_assignment PIN_K17 -to GPIOB[8]
set_location_assignment PIN_K16 -to GPIOA[9]
set_location_assignment PIN_L22 -to GPIOB[9]
set_location_assignment PIN_L19 -to GPIOA[10]
set_location_assignment PIN_L18 -to GPIOB[10]
set_location_assignment PIN_L17 -to GPIOA[11]
set_location_assignment PIN_M22 -to GPIOB[11]
set_location_assignment PIN_M21 -to GPIOA[12]
set_location_assignment PIN_M18 -to GPIOB[12]
set_location_assignment PIN_M20 -to GPIOA[13]
set_location_assignment PIN_M16 -to GPIOB[13]
set_location_assignment PIN_N21 -to GPIOA[14]
set_location_assignment PIN_N19 -to GPIOB[14]
set_location_assignment PIN_N20 -to GPIOA[15]
set_location_assignment PIN_N16 -to GPIOB[15]
set_location_assignment PIN_P22 -to GPIOA[16]
set_location_assignment PIN_P18 -to GPIOB[16]
set_location_assignment PIN_P19 -to GPIOA[17]
set_location_assignment PIN_P17 -to GPIOB[17]
set_location_assignment PIN_P16 -to GPIOA[18]
set_location_assignment PIN_R22 -to GPIOB[18]
set_location_assignment PIN_R21 -to GPIOA[19]
set_location_assignment PIN_R17 -to GPIOB[19]
set_location_assignment PIN_R16 -to GPIOA[20]
set_location_assignment PIN_T22 -to GPIOB[20]
set_location_assignment PIN_T19 -to GPIOA[21]
set_location_assignment PIN_T20 -to GPIOB[21]
set_location_assignment PIN_T18 -to GPIOA[22]
set_location_assignment PIN_T17 -to GPIOB[22]
set_location_assignment PIN_U22 -to GPIOA[23]
set_location_assignment PIN_U21 -to GPIOB[23]
set_location_assignment PIN_U20 -to GPIOA[24]
set_location_assignment PIN_V21 -to GPIOB[24]
set_location_assignment PIN_V19 -to GPIOA[25]
set_location_assignment PIN_V20 -to GPIOB[25]
set_location_assignment PIN_W22 -to GPIOA[26]
set_location_assignment PIN_W21 -to GPIOB[26]
set_location_assignment PIN_Y22 -to GPIOA[27]
set_location_assignment PIN_Y21 -to GPIOB[27]
set_location_assignment PIN_AA22 -to GPIOA[28]
set_location_assignment PIN_AB22 -to GPIOB[28]
set_location_assignment PIN_AB21 -to GPIOA[29]
set_location_assignment PIN_AB20 -to GPIOB[29]
set_location_assignment PIN_AA20 -to GPIOA[30]
set_location_assignment PIN_Y20 -to GPIOB[30]
set_location_assignment PIN_AA19 -to GPIOA[31]
set_location_assignment PIN_W19 -to GPIOB[31]
set_location_assignment PIN_Y19 -to GPIOA[32]
set_location_assignment PIN_AB18 -to GPIOB[32]
set_location_assignment PIN_AA18 -to GPIOA[33]
set_location_assignment PIN_V18 -to GPIOB[33]
set_location_assignment PIN_AB17 -to GPIOA[34]
set_location_assignment PIN_AA17 -to GPIOB[34]
set_location_assignment PIN_U17 -to GPIOA[35]
set_location_assignment PIN_Y17 -to GPIOB[35]
set_location_assignment PIN_Y16 -to GPIOC[18]
set_location_assignment PIN_V16 -to GPIOC[19]
set_location_assignment PIN_W16 -to GPIOC[20]
set_location_assignment PIN_U16 -to GPIOC[21]
set_location_assignment PIN_AB15 -to GPIOC[22]
set_location_assignment PIN_AA15 -to GPIOC[23]
set_location_assignment PIN_V15 -to GPIOC[24]
set_location_assignment PIN_Y15 -to GPIOC[25]
set_location_assignment PIN_U15 -to GPIOC[26]
set_location_assignment PIN_T15 -to GPIOC[27]
set_location_assignment PIN_AA14 -to GPIOC[28]
set_location_assignment PIN_V14 -to GPIOC[29]
set_location_assignment PIN_Y14 -to GPIOC[30]
set_location_assignment PIN_T14 -to GPIOC[31]
set_location_assignment PIN_R14 -to GPIOC[32]
set_location_assignment PIN_AB13 -to GPIOC[33]
set_location_assignment PIN_AA13 -to GPIOC[34]
set_location_assignment PIN_V13 -to GPIOC[35]
set_location_assignment PIN_U13 -to SD_WRITEPROTECT
set_location_assignment PIN_T13 -to SD_DETECT
set_location_assignment PIN_AB12 -to SD_DAT1
set_location_assignment PIN_AA12 -to SD_DAT0
set_location_assignment PIN_U12 -to SD_CLK
set_location_assignment PIN_T12 -to SD_CMD
set_location_assignment PIN_R12 -to SD_DAT3
set_location_assignment PIN_AB11 -to SD_DAT2
set_location_assignment PIN_U11 -to PS2CLK
set_location_assignment PIN_Y11 -to PS2DAT
set_location_assignment PIN_R11 -to USB2DM
set_location_assignment PIN_AB10 -to USB2DP
set_location_assignment PIN_AA10 -to USB1DM
set_location_assignment PIN_V10 -to USB1DP
set_location_assignment PIN_Y10 -to DRAM_ADDR[4]
set_location_assignment PIN_U10 -to DRAM_ADDR[5]
set_location_assignment PIN_T10 -to DRAM_ADDR[6]
set_location_assignment PIN_AA9 -to DRAM_ADDR[7]
set_location_assignment PIN_W9 -to DRAM_ADDR[8]
set_location_assignment PIN_Y9 -to DRAM_ADDR[9]
set_location_assignment PIN_V9 -to DRAM_ADDR[11]
set_location_assignment PIN_T9 -to DRAM_ADDR[12]
set_location_assignment PIN_AB8 -to DRAM_CKE
set_location_assignment PIN_AA8 -to DRAM_CLK
set_location_assignment PIN_U8 -to DRAM_UDQM
set_location_assignment PIN_W8 -to DRAM_DQ[8]
set_location_assignment PIN_T8 -to DRAM_DQ[9]
set_location_assignment PIN_AB7 -to DRAM_DQ[10]
set_location_assignment PIN_AA7 -to DRAM_DQ[11]
set_location_assignment PIN_U7 -to DRAM_DQ[12]
set_location_assignment PIN_AB6 -to DRAM_DQ[13]
set_location_assignment PIN_V6 -to DRAM_DQ[14]
set_location_assignment PIN_AB5 -to DRAM_DQ[15]
set_location_assignment PIN_U6 -to DRAM_ADDR[3]
set_location_assignment PIN_T7 -to DRAM_ADDR[2]
set_location_assignment PIN_R5 -to DRAM_ADDR[1]
set_location_assignment PIN_R6 -to DRAM_ADDR[0]
set_location_assignment PIN_R7 -to DRAM_ADDR[10]
set_location_assignment PIN_P6 -to DRAM_BA_1
set_location_assignment PIN_P7 -to DRAM_BA_0
set_location_assignment PIN_P8 -to DRAM_CS_N
set_location_assignment PIN_N6 -to DRAM_RAS_N
set_location_assignment PIN_N8 -to DRAM_CAS_N
set_location_assignment PIN_N9 -to DRAM_WE_N
set_location_assignment PIN_M6 -to DRAM_LDQM
set_location_assignment PIN_M7 -to DRAM_DQ[7]
set_location_assignment PIN_M8 -to DRAM_DQ[6]
set_location_assignment PIN_L7 -to DRAM_DQ[5]
set_location_assignment PIN_L8 -to DRAM_DQ[4]
set_location_assignment PIN_K7 -to DRAM_DQ[0]
set_location_assignment PIN_K9 -to DRAM_DQ[1]
set_location_assignment PIN_J7 -to DRAM_DQ[2]
set_location_assignment PIN_J8 -to DRAM_DQ[3]
set_location_assignment PIN_H6 -to ADC_SDA
set_location_assignment PIN_G6 -to ADC_SCL
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[16]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[17]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[18]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[19]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[20]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[21]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[22]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[23]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[24]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[25]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[26]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[27]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[28]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[29]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[30]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[31]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[32]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[33]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[34]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[35]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[16]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[17]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[18]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[19]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[20]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[21]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[22]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[23]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[24]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[25]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[26]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[27]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[28]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[29]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[30]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[31]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[32]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[33]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[34]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[35]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[16]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[17]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[18]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[19]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[20]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[21]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[22]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[23]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[24]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[25]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[26]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[27]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[28]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[29]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[30]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[31]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[32]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[33]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[34]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[35]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_UDQM
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_BA_1
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_BA_0
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_CS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_RAS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_CAS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_WE_N
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_LDQM
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA_0
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA_1
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_UDQM
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_LDQM
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CS_N
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[15]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[0]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[4]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[5]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[6]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[7]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[8]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[9]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[10]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[11]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[12]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[13]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[14]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[15]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_DAT2
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_DAT1
set_global_assignment -name DEVICE 5CEBA2F23C8
eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.sdc
create_clock -period 5MHz [get_ports CLOCK_5]
derive_pll_clocks
derive_clock_uncertainty
eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.vhd
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_MISC.all;
LIBRARY work;
ENTITY atari800core_eclaireXL IS
PORT
(
CLOCK_5 : IN STD_LOGIC;
PS2CLK : IN STD_LOGIC;
PS2DAT : IN STD_LOGIC;
GPIOA : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
GPIOB : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
GPIOC: INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
DRAM_BA_0 : OUT STD_LOGIC;
DRAM_BA_1 : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
DRAM_LDQM : OUT STD_LOGIC;
DRAM_UDQM : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_ADDR : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
SD_WRITEPROTECT : IN STD_LOGIC;
SD_DETECT : IN STD_LOGIC;
SD_DAT1 : OUT STD_LOGIC;
SD_DAT0 : IN STD_LOGIC;
SD_CLK : OUT STD_LOGIC;
SD_CMD : OUT STD_LOGIC;
SD_DAT3 : OUT STD_LOGIC;
SD_DAT2 : OUT STD_LOGIC;
--VGA_VS : OUT STD_LOGIC;
--VGA_HS : OUT STD_LOGIC;
--VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--TMDS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_BLANK_N : OUT STD_LOGIC;
VGA_CLK : OUT STD_LOGIC;
AUDIO_LEFT : OUT STD_LOGIC;
AUDIO_RIGHT : OUT STD_LOGIC;
USB2DM: INOUT STD_LOGIC;
USB2DP: INOUT STD_LOGIC;
USB1DM: INOUT STD_LOGIC;
USB1DP: INOUT STD_LOGIC;
ADC_SDA: INOUT STD_LOGIC;
ADC_SCL: INOUT STD_LOGIC
);
END atari800core_eclaireXL;
ARCHITECTURE vhdl OF atari800core_eclaireXL IS
component hq_dac
port (
reset :in std_logic;
clk :in std_logic;
clk_ena : in std_logic;
pcm_in : in std_logic_vector(19 downto 0);
dac_out : out std_logic
);
end component;
component pll2
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
outclk_1 : out std_logic; -- outclk1.clk
locked : out std_logic -- locked.export
);
end component;
-- SYSTEM
SIGNAL CLK : STD_LOGIC;
SIGNAL CLK_114 : STD_LOGIC;
SIGNAL SVIDEO_ECS_CLK : STD_LOGIC;
SIGNAL PLL_LOCKED : STD_LOGIC;
-- ModeLine "720x576@50" 27 720 732 795 864 576 581 586 625 -hsync -vsync (576p)
-- ModeLine "768x576@50" 29.5 768 789 858 944 576 581 586 625 -hsync -vsync
-- ModeLine " 640x 480@60Hz" 25.20 640 656 752 800 480 490 492 525 -HSync -VSync
-- ModeLine " 720x 480@60Hz" 27.00 720 736 798 858 480 489 495 525 -HSync -VSync
-- Modeline " 800x 600@60Hz" 40.00 800 840 968 1056 600 601 605 628 +HSync +VSync
-- ModeLine "1024x 768@60Hz" 65.00 1024 1048 1184 1344 768 771 777 806 -HSync -VSync
-- ModeLine "1280x 720@60Hz" 74.25 1280 1390 1430 1650 720 725 730 750 +HSync +VSync
-- ModeLine "1280x 768@60Hz" 80.14 1280 1344 1480 1680 768 769 772 795 +HSync +VSync
-- ModeLine "1280x 800@60Hz" 83.46 1280 1344 1480 1680 800 801 804 828 +HSync +VSync
-- ModeLine "1280x 960@60Hz" 108.00 1280 1376 1488 1800 960 961 964 1000 +HSync +VSync
-- ModeLine "1280x1024@60Hz" 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +HSync +VSync
-- ModeLine "1360x 768@60Hz" 85.50 1360 1424 1536 1792 768 771 778 795 -HSync -VSync
-- ModeLine "1920x1080@25Hz" 74.25 1920 2448 2492 2640 1080 1084 1089 1125 +HSync +VSync
-- ModeLine "1920x1080@30Hz" 89.01 1920 2448 2492 2640 1080 1084 1089 1125 +HSync +VSync
-- Horizontal Timing constants
constant h_pixels_across : integer := 720 - 1;
constant h_sync_on : integer := 732 - 1;
constant h_sync_off : integer := 795 - 1;
constant h_end_count : integer := 864 - 1;
-- Vertical Timing constants
constant v_pixels_down : integer := 576 - 1;
constant v_sync_on : integer := 581 - 1;
constant v_sync_off : integer := 586 - 1;
constant v_end_count : integer := 625 - 1;
signal hcnt : std_logic_vector(11 downto 0) := "000000000000"; -- horizontal pixel counter
signal vcnt : std_logic_vector(11 downto 0) := "000000000000"; -- vertical line counter
signal hsync : std_logic;
signal vsync : std_logic;
signal blank : std_logic;
signal shift : std_logic_vector(7 downto 0);
signal red : std_logic_vector(7 downto 0);
signal green : std_logic_vector(7 downto 0);
signal blue : std_logic_vector(7 downto 0);
signal clk_hdmi : std_logic;
signal clk_vga : std_logic;
signal TMDS : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
DRAM_CS_N <= '1';
DRAM_BA_0 <= 'Z';
DRAM_BA_1 <= 'Z';
DRAM_RAS_N <= 'Z';
DRAM_CAS_N <= 'Z';
DRAM_WE_N <= 'Z';
DRAM_LDQM <= 'Z';
DRAM_UDQM <= 'Z';
DRAM_CKE <= 'Z';
DRAM_ADDR <= (others=>'Z');
DRAM_DQ <= (others=>'Z');
SD_DAT1 <= 'Z';
SD_DAT2 <= 'Z';
SD_DAT3 <= 'Z';
SD_CMD <= 'Z';
SD_CLK <= 'Z';
USB2DM <= 'Z';
USB2DP <= 'Z';
USB1DM <= 'Z';
USB1DP <= 'Z';
ADC_SDA <= 'Z';
ADC_SCL <= 'Z';
--VGA_VS <= 'Z';
--VGA_HS <= 'Z';
--VGA_B <= (others=>'Z');
--VGA_G <= (others=>'Z');
--VGA_R <= (others=>'Z');
VGA_BLANK_N <= '0';
VGA_CLK <= '0';
AUDIO_LEFT <= 'Z';
AUDIO_RIGHT <= 'Z';
--GPIOA <= shift_reg(35 downto 0);
GPIOB <= (others=>'0');
GPIOC <= (others=>'0');
GPIOA(35 downto 16) <= (others=>'0');
GPIOA(0) <= '0';
GPIOA(11 downto 5) <= (others=>'0');
GPIOA(1) <= TMDS(7); -- D2P
GPIOA(2) <= TMDS(6); -- D2N
GPIOA(3) <= TMDS(5); -- D1P
GPIOA(4) <= TMDS(4); -- D1N
GPIOA(12) <= TMDS(2); -- D0N
GPIOA(13) <= TMDS(3); -- D0P
GPIOA(14) <= TMDS(0); -- C N
GPIOA(15) <= TMDS(1); -- C P
-- PLL
pll2_inst: pll2
port map (
refclk => CLOCK_5, -- 5.0 MHz
-- out
locked => open,
outclk_0 => clk_hdmi, -- clk_vga * 5
outclk_1 => clk_vga);
-- HDMI
hdmi_inst: entity work.hdmi
port map (
I_CLK_PIXEL => clk_vga,
I_CLK_TMDS => clk_hdmi, -- 472.6 MHz max
I_HSYNC => hsync,
I_VSYNC => vsync,
I_BLANK => blank,
I_RED => red,
I_GREEN => green,
I_BLUE => blue,
O_TMDS => TMDS);
process (clk_vga, hcnt)
begin
if clk_vga'event and clk_vga = '1' then
if hcnt = h_end_count then
hcnt <= (others => '0');
else
hcnt <= hcnt + 1;
end if;
if hcnt = h_sync_on then
if vcnt = v_end_count then
vcnt <= (others => '0');
shift <= shift + 1;
else
vcnt <= vcnt + 1;
end if;
end if;
end if;
end process;
hsync <= '0' when (hcnt <= h_sync_on) or (hcnt > h_sync_off) else '1';
vsync <= '0' when (vcnt <= v_sync_on) or (vcnt > v_sync_off) else '1';
blank <= '1' when (hcnt > h_pixels_across) or (vcnt > v_pixels_down) else '0';
red <= "11111111" when hcnt = 0 or hcnt = h_pixels_across or vcnt = 0 or vcnt = v_pixels_down else (hcnt(7 downto 0) + shift) and "11111111";
green <= "11111111" when hcnt = 0 or hcnt = h_pixels_across or vcnt = 0 or vcnt = v_pixels_down else (vcnt(7 downto 0) + shift) and "11111111";
blue <= "11111111" when hcnt = 0 or hcnt = h_pixels_across or vcnt = 0 or vcnt = v_pixels_down else (hcnt(7 downto 0) + vcnt(7 downto 0) - shift) and "11111111";
END vhdl;
eclaireXL/hardware/test/test_hdmi/build.sh
#!/usr/bin/perl -w
use strict;
my $wanted_variant = shift @ARGV;
my $name="eclaireXL";
#variants...
my $PAL = 1;
my $NTSC = 0;
my $RGB = 1; # i.e. not scandoubled
my $VGA = 2;
#Added like this to the generated qsf
#set_parameter -name TV 1
my %variants =
(
# "PAL" =>
# {
# "TV" => $PAL
# },
# "NTSC" =>
# {
# "TV" => $NTSC
# },
"A2EBA_RGB" =>
{
}
);
if (not defined $wanted_variant or (not exists $variants{$wanted_variant} and $wanted_variant ne "ALL"))
{
die "Provide variant of ALL or ".join ",",sort keys %variants;
}
foreach my $variant (sort keys %variants)
{
next if ($wanted_variant ne $variant and $wanted_variant ne "ALL");
print "Building $variant of $name\n";
my $dir = "build_$variant";
`rm -rf $dir`;
mkdir $dir;
`cp -a hdmi $dir`;
`cp -a pll2* $dir`;
`cp *.v $dir`;
`cp *.vhd* $dir`;
`cp atari800core*.sdc $dir`;
`mkdir $dir/common`;
chdir $dir;
`../../../../makeqsf ../atari800core_eclaireXL.qsf ./hdmi`;
foreach my $key (sort keys %{$variants{$variant}})
{
my $val = $variants{$variant}->{$key};
`echo set_parameter -name $key $val >> atari800core_eclaireXL.qsf`;
}
`quartus_sh --flow compile atari800core_eclaireXL > build.log 2> build.err`;
# `quartus_cpf --convert ../output_file.cof`;
chdir "..";
}
eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.ppf
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone V" variation_name="altddio_out1" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
<global>
<pin name="datain_h[7..0]" direction="input" scope="external" />
<pin name="datain_l[7..0]" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="dataout[7..0]" direction="output" scope="external" />
</global>
</pinplan>
eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.qip
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "15.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"]
eclaireXL/hardware/test/test_hdmi/pll2_sim/synopsys/vcsmx/synopsys_sim.setup
WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera: ./libraries/altera/
lpm: ./libraries/lpm/
sgate: ./libraries/sgate/
altera_mf: ./libraries/altera_mf/
altera_lnsim: ./libraries/altera_lnsim/
cyclonev: ./libraries/cyclonev/
LIBRARY_SCAN = TRUE
eclaireXL/hardware/test/test_hdmi/pll2_sim.f
pll2_sim/pll2.vho
eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.vhd
-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTDDIO_OUT
-- ============================================================
-- File Name: altddio_out1.vhd
-- Megafunction Name(s):
-- ALTDDIO_OUT
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.0.0 Build 145 04/22/2015 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY altddio_out1 IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END altddio_out1;
ARCHITECTURE SYN OF altddio_out1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
dataout <= sub_wire0(7 DOWNTO 0);
ALTDDIO_OUT_component : ALTDDIO_OUT
GENERIC MAP (
extend_oe_disable => "OFF",
intended_device_family => "Cyclone V",
invert_output => "OFF",
lpm_hint => "UNUSED",
lpm_type => "altddio_out",
oe_reg => "UNREGISTERED",
power_up_high => "OFF",
width => 8
)
PORT MAP (
datain_h => datain_h,
datain_l => datain_l,
outclock => outclock,
dataout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]"
-- Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0
-- Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]"
-- Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0
-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE FALSE
-- Retrieval info: LIB_FILE: altera_mf
eclaireXL/hardware/test/test_hdmi/hdmi/encoder.vhd
-------------------------------------------------------------------[21.06.2016]
-- Encoder
-------------------------------------------------------------------------------
-- Engineer: MVV
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity encoder is
port (
I_CLK : in std_logic;
I_VD : in std_logic_vector(7 downto 0); -- video data (RED, GREEN or BLUE)
I_CD : in std_logic_vector(1 downto 0); -- control data
I_VDE : in std_logic; -- video data enable, to choose between CD (when VDE=0) and VD (when VDE=1)
O_TMDS : out std_logic_vector(9 downto 0));
end entity encoder;
architecture rtl of encoder is
signal nb1s : std_logic_vector(3 downto 0);
signal x_nor : std_logic;
signal balance_acc : std_logic_vector(3 downto 0) := "0000";
signal balance : std_logic_vector(3 downto 0);
signal balance_sign_eq : std_logic;
signal invert_q_m : std_logic;
signal balance_acc_inc : std_logic_vector(3 downto 0);
signal balance_acc_new : std_logic_vector(3 downto 0);
signal data : std_logic_vector(9 downto 0);
signal code : std_logic_vector(9 downto 0);
signal q_m : std_logic_vector(8 downto 0);
begin
process (I_CLK)
begin
if (I_CLK'event and I_CLK = '1') then
if (I_VDE = '1') then
O_TMDS <= data;
balance_acc <= balance_acc_new;
else
O_TMDS <= code;
balance_acc <= "0000";
end if;
end if;
case I_CD is
when "00" => code <= "1101010100";
when "01" => code <= "0010101011";
when "10" => code <= "0101010100";
when others => code <= "1010101011";
end case;
end process;
nb1s <= "000" & I_VD(0) + I_VD(1) + I_VD(2) + I_VD(3) + I_VD(4) + I_VD(5) + I_VD(6) + I_VD(7);
x_nor <= '1' when (nb1s > "0100") or (nb1s = "0100" and I_VD(0) = '0') else '0';
q_m <= not(x_nor) & (q_m(6 downto 0) xor I_VD(7 downto 1) xor (x_nor & x_nor & x_nor & x_nor & x_nor & x_nor & x_nor)) & I_VD(0);
balance <= ("000" & q_m(0) + q_m(1) + q_m(2) + q_m(3) + q_m(4) + q_m(5) + q_m(6) + q_m(7)) - "0100";
data <= invert_q_m & q_m(8) & q_m(7 downto 0) xor invert_q_m & invert_q_m & invert_q_m & invert_q_m & invert_q_m & invert_q_m & invert_q_m & invert_q_m;
balance_sign_eq <= '1' when balance(3) = balance_acc(3) else '0';
invert_q_m <= not(q_m(8)) when balance = "0000" or balance_acc = "0000" else balance_sign_eq;
balance_acc_inc <= balance - ("000" & ((q_m(8) xor not(balance_sign_eq)) and (not((balance(3) or balance(2) or balance(1) or balance(0) or balance_acc(3) or balance_acc(2) or balance_acc(1) or balance_acc(0))))));
balance_acc_new <= balance_acc - balance_acc_inc when invert_q_m = '1' else balance_acc + balance_acc_inc;
end architecture rtl;
eclaireXL/hardware/test/test_hdmi/hdmi/hdmi.vhd
-------------------------------------------------------------------[09.05.2016]
-- HDMI
-------------------------------------------------------------------------------
-- Engineer: MVV
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdmi is
port (
I_CLK_PIXEL : in std_logic; -- pixelclock
I_CLK_TMDS : in std_logic; -- pixelclock*5
I_HSYNC : in std_logic;
I_VSYNC : in std_logic;
I_BLANK : in std_logic;
I_RED : in std_logic_vector(7 downto 0);
I_GREEN : in std_logic_vector(7 downto 0);
I_BLUE : in std_logic_vector(7 downto 0);
O_TMDS : out std_logic_vector(7 downto 0));
end entity hdmi;
architecture rtl of hdmi is
signal r : std_logic_vector(9 downto 0);
signal g : std_logic_vector(9 downto 0);
signal b : std_logic_vector(9 downto 0);
signal mod5 : std_logic_vector(2 downto 0) := "000"; -- modulus 5 counter
signal shift_r : std_logic_vector(9 downto 0) := "0000000000";
signal shift_g : std_logic_vector(9 downto 0) := "0000000000";
signal shift_b : std_logic_vector(9 downto 0) := "0000000000";
signal shift_clk : std_logic_vector(9 downto 0) := "0000000000";
begin
encode_r : entity work.encoder
port map (
I_CLK => I_CLK_PIXEL,
I_VD => I_RED,
I_CD => "00",
I_VDE => not(I_BLANK),
O_TMDS => r);
encode_g : entity work.encoder
port map (
I_CLK => I_CLK_PIXEL,
I_VD => I_GREEN,
I_CD => "00",
I_VDE => not(I_BLANK),
O_TMDS => g);
encode_b : entity work.encoder
port map (
I_CLK => I_CLK_PIXEL,
I_VD => I_BLUE,
I_CD => (I_VSYNC & I_HSYNC),
I_VDE => not(I_BLANK),
O_TMDS => b);
process (I_CLK_TMDS)
begin
if (I_CLK_TMDS'event and I_CLK_TMDS = '1') then
if mod5(2) = '1' then
mod5 <= "000";
shift_r <= r;
shift_g <= g;
shift_b <= b;
shift_clk <= "0000011111";
else
mod5 <= mod5 + "001";
shift_r <= "00" & shift_r(9 downto 2);
shift_g <= "00" & shift_g(9 downto 2);
shift_b <= "00" & shift_b(9 downto 2);
shift_clk <= "00" & shift_clk(9 downto 2);
end if;
end if;
end process;
ddio_inst : entity work.altddio_out1
port map (
datain_h => shift_r(0) & not(shift_r(0)) & shift_g(0) & not(shift_g(0)) & shift_b(0) & not(shift_b(0)) & shift_clk(0) & not(shift_clk(0)),
datain_l => shift_r(1) & not(shift_r(1)) & shift_g(1) & not(shift_g(1)) & shift_b(1) & not(shift_b(1)) & shift_clk(1) & not(shift_clk(1)),
outclock => I_CLK_TMDS,
dataout => O_TMDS);
end architecture rtl;
eclaireXL/hardware/test/test_hdmi/pll2/pll2_0002.qip
set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll2_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll2_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll2_0002*|altera_pll:altera_pll_i*|*"
eclaireXL/hardware/test/test_hdmi/pll2/pll2_0002.v
`timescale 1ns/10ps
module pll2_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("5.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("135.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("27.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
eclaireXL/hardware/test/test_hdmi/pll2.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 184)
(text "pll2" (rect 71 -1 82 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 20 180)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 48 112)(line_width 1))
)
(port
(pt 160 72)
(output)
(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
(line (pt 160 72)(pt 112 72)(line_width 1))
)
(port
(pt 160 112)
(output)
(text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8)))
(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
(line (pt 160 112)(pt 112 112)(line_width 1))
)
(port
(pt 160 152)
(output)
(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
(text "locked" (rect 127 141 163 152)(font "Arial" (font_size 8)))
(line (pt 160 152)(pt 112 152)(line_width 1))
)
(drawing
(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
(text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0)))
(text "locked" (rect 113 123 262 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 82 147 200 304)(font "Arial" (color 0 0 0)))
(text " altera_pll " (rect 118 168 308 346)(font "Arial" ))
(line (pt 48 32)(pt 112 32)(line_width 1))
(line (pt 112 32)(pt 112 168)(line_width 1))
(line (pt 48 168)(pt 112 168)(line_width 1))
(line (pt 48 32)(pt 48 168)(line_width 1))
(line (pt 49 52)(pt 49 76)(line_width 1))
(line (pt 50 52)(pt 50 76)(line_width 1))
(line (pt 49 92)(pt 49 116)(line_width 1))
(line (pt 50 92)(pt 50 116)(line_width 1))
(line (pt 111 52)(pt 111 76)(line_width 1))
(line (pt 110 52)(pt 110 76)(line_width 1))
(line (pt 111 92)(pt 111 116)(line_width 1))
(line (pt 110 92)(pt 110 116)(line_width 1))
(line (pt 111 132)(pt 111 156)(line_width 1))
(line (pt 110 132)(pt 110 156)(line_width 1))
(line (pt 0 0)(pt 160 0)(line_width 1))
(line (pt 160 0)(pt 160 184)(line_width 1))
(line (pt 0 184)(pt 160 184)(line_width 1))
(line (pt 0 0)(pt 0 184)(line_width 1))
)
)
eclaireXL/hardware/test/test_hdmi/pll2.cmp
component pll2 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll2;
eclaireXL/hardware/test/test_hdmi/pll2.ppf
<?xml version="1.0" encoding="UTF-8"?>
<pinplan
variation_name="pll2"
megafunction_name="ALTERA_PLL"
intended_family="Cyclone V"
specifies="all_ports">
<global>
<pin name="refclk" direction="input" scope="external" />
<pin name="rst" direction="input" scope="external" />
<pin name="outclk_0" direction="output" scope="external" />
<pin name="outclk_1" direction="output" scope="external" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>
eclaireXL/hardware/test/test_hdmi/pll2.qip
set_global_assignment -entity "pll2" -library "pll2" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll2" -library "pll2" -name IP_TOOL_VERSION "15.0"
set_global_assignment -entity "pll2" -library "pll2" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll2" -name MISC_FILE [file join $::quartus(qip_path) "pll2.cmp"]
set_global_assignment -entity "pll2" -library "pll2" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "pll2" -library "pll2" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "pll2" -library "pll2" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_NAME "cGxsMg=="
set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_VERSION "MTUuMA=="
set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_NAME "cGxsMl8wMDAy"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_VERSION "MTUuMA=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::OA==::RGV2aWNlIFNwZWVkIEdyYWRl"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NS4w::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NS4wIE1Ieg==::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTM1LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTA4::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTA4::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MjA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
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