Index: eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.qsf
===================================================================
--- eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.qsf	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.qsf	(revision 473)
@@ -0,0 +1,453 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+# Date created = 20:32:21  July 11, 2015
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_eclaireXL_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core_eclaireXL
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:21  JULY 11, 2015"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name VHDL_FILE atari800core_eclaireXL.vhd
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+set_global_assignment -name VHDL_FILE atari800core_de1.vhd
+set_global_assignment -name QIP_FILE pll2.qip
+set_location_assignment PIN_H16 -to CLOCK_5
+
+set_location_assignment PIN_C9 -to VGA_BLANK_N
+set_location_assignment PIN_G11 -to VGA_CLK
+set_location_assignment PIN_C11 -to VGA_HS
+set_location_assignment PIN_H11 -to VGA_VS
+set_location_assignment PIN_J11 -to AUDIO_LEFT
+set_location_assignment PIN_A12 -to AUDIO_RIGHT
+set_location_assignment PIN_B12 -to GPIOC[0]
+set_location_assignment PIN_D12 -to GPIOC[1]
+set_location_assignment PIN_E12 -to GPIOC[2]
+set_location_assignment PIN_F12 -to GPIOC[3]
+set_location_assignment PIN_A13 -to GPIOC[4]
+set_location_assignment PIN_B13 -to GPIOC[5]
+set_location_assignment PIN_D13 -to GPIOC[6]
+set_location_assignment PIN_C13 -to GPIOC[7]
+set_location_assignment PIN_F13 -to GPIOC[8]
+set_location_assignment PIN_G13 -to GPIOC[9]
+set_location_assignment PIN_A14 -to GPIOC[10]
+set_location_assignment PIN_E14 -to GPIOC[11]
+set_location_assignment PIN_F14 -to GPIOC[12]
+set_location_assignment PIN_H14 -to GPIOC[13]
+set_location_assignment PIN_A15 -to GPIOC[14]
+set_location_assignment PIN_B15 -to GPIOC[15]
+set_location_assignment PIN_E15 -to GPIOC[16]
+set_location_assignment PIN_C15 -to GPIOC[17]
+set_location_assignment PIN_F15 -to GPIOA[0]
+set_location_assignment PIN_G15 -to GPIOB[0]
+set_location_assignment PIN_B16 -to GPIOA[1]
+set_location_assignment PIN_E16 -to GPIOB[1]
+set_location_assignment PIN_C16 -to GPIOA[2]
+set_location_assignment PIN_D17 -to GPIOB[2]
+set_location_assignment PIN_G17 -to GPIOA[3]
+set_location_assignment PIN_G18 -to GPIOB[3]
+set_location_assignment PIN_G16 -to GPIOA[4]
+set_location_assignment PIN_H18 -to GPIOB[4]
+set_location_assignment PIN_J18 -to GPIOA[5]
+set_location_assignment PIN_J19 -to GPIOB[5]
+set_location_assignment PIN_J17 -to GPIOA[6]
+set_location_assignment PIN_K22 -to GPIOB[6]
+set_location_assignment PIN_K21 -to GPIOA[7]
+set_location_assignment PIN_K19 -to GPIOB[7]
+set_location_assignment PIN_K20 -to GPIOA[8]
+set_location_assignment PIN_K17 -to GPIOB[8]
+set_location_assignment PIN_K16 -to GPIOA[9]
+set_location_assignment PIN_L22 -to GPIOB[9]
+set_location_assignment PIN_L19 -to GPIOA[10]
+set_location_assignment PIN_L18 -to GPIOB[10]
+set_location_assignment PIN_L17 -to GPIOA[11]
+set_location_assignment PIN_M22 -to GPIOB[11]
+set_location_assignment PIN_M21 -to GPIOA[12]
+set_location_assignment PIN_M18 -to GPIOB[12]
+set_location_assignment PIN_M20 -to GPIOA[13]
+set_location_assignment PIN_M16 -to GPIOB[13]
+set_location_assignment PIN_N21 -to GPIOA[14]
+set_location_assignment PIN_N19 -to GPIOB[14]
+set_location_assignment PIN_N20 -to GPIOA[15]
+set_location_assignment PIN_N16 -to GPIOB[15]
+set_location_assignment PIN_P22 -to GPIOA[16]
+set_location_assignment PIN_P18 -to GPIOB[16]
+set_location_assignment PIN_P19 -to GPIOA[17]
+set_location_assignment PIN_P17 -to GPIOB[17]
+set_location_assignment PIN_P16 -to GPIOA[18]
+set_location_assignment PIN_R22 -to GPIOB[18]
+set_location_assignment PIN_R21 -to GPIOA[19]
+set_location_assignment PIN_R17 -to GPIOB[19]
+set_location_assignment PIN_R16 -to GPIOA[20]
+set_location_assignment PIN_T22 -to GPIOB[20]
+set_location_assignment PIN_T19 -to GPIOA[21]
+set_location_assignment PIN_T20 -to GPIOB[21]
+set_location_assignment PIN_T18 -to GPIOA[22]
+set_location_assignment PIN_T17 -to GPIOB[22]
+set_location_assignment PIN_U22 -to GPIOA[23]
+set_location_assignment PIN_U21 -to GPIOB[23]
+set_location_assignment PIN_U20 -to GPIOA[24]
+set_location_assignment PIN_V21 -to GPIOB[24]
+set_location_assignment PIN_V19 -to GPIOA[25]
+set_location_assignment PIN_V20 -to GPIOB[25]
+set_location_assignment PIN_W22 -to GPIOA[26]
+set_location_assignment PIN_W21 -to GPIOB[26]
+set_location_assignment PIN_Y22 -to GPIOA[27]
+set_location_assignment PIN_Y21 -to GPIOB[27]
+set_location_assignment PIN_AA22 -to GPIOA[28]
+set_location_assignment PIN_AB22 -to GPIOB[28]
+set_location_assignment PIN_AB21 -to GPIOA[29]
+set_location_assignment PIN_AB20 -to GPIOB[29]
+set_location_assignment PIN_AA20 -to GPIOA[30]
+set_location_assignment PIN_Y20 -to GPIOB[30]
+set_location_assignment PIN_AA19 -to GPIOA[31]
+set_location_assignment PIN_W19 -to GPIOB[31]
+set_location_assignment PIN_Y19 -to GPIOA[32]
+set_location_assignment PIN_AB18 -to GPIOB[32]
+set_location_assignment PIN_AA18 -to GPIOA[33]
+set_location_assignment PIN_V18 -to GPIOB[33]
+set_location_assignment PIN_AB17 -to GPIOA[34]
+set_location_assignment PIN_AA17 -to GPIOB[34]
+set_location_assignment PIN_U17 -to GPIOA[35]
+set_location_assignment PIN_Y17 -to GPIOB[35]
+set_location_assignment PIN_Y16 -to GPIOC[18]
+set_location_assignment PIN_V16 -to GPIOC[19]
+set_location_assignment PIN_W16 -to GPIOC[20]
+set_location_assignment PIN_U16 -to GPIOC[21]
+set_location_assignment PIN_AB15 -to GPIOC[22]
+set_location_assignment PIN_AA15 -to GPIOC[23]
+set_location_assignment PIN_V15 -to GPIOC[24]
+set_location_assignment PIN_Y15 -to GPIOC[25]
+set_location_assignment PIN_U15 -to GPIOC[26]
+set_location_assignment PIN_T15 -to GPIOC[27]
+set_location_assignment PIN_AA14 -to GPIOC[28]
+set_location_assignment PIN_V14 -to GPIOC[29]
+set_location_assignment PIN_Y14 -to GPIOC[30]
+set_location_assignment PIN_T14 -to GPIOC[31]
+set_location_assignment PIN_R14 -to GPIOC[32]
+set_location_assignment PIN_AB13 -to GPIOC[33]
+set_location_assignment PIN_AA13 -to GPIOC[34]
+set_location_assignment PIN_V13 -to GPIOC[35]
+set_location_assignment PIN_U13 -to SD_WRITEPROTECT
+set_location_assignment PIN_T13 -to SD_DETECT
+set_location_assignment PIN_AB12 -to SD_DAT1
+set_location_assignment PIN_AA12 -to SD_DAT0
+set_location_assignment PIN_U12 -to SD_CLK
+set_location_assignment PIN_T12 -to SD_CMD
+set_location_assignment PIN_R12 -to SD_DAT3
+set_location_assignment PIN_AB11 -to SD_DAT2
+set_location_assignment PIN_U11 -to PS2CLK
+set_location_assignment PIN_Y11 -to PS2DAT
+set_location_assignment PIN_R11 -to USB2DM
+set_location_assignment PIN_AB10 -to USB2DP
+set_location_assignment PIN_AA10 -to USB1DM
+set_location_assignment PIN_V10 -to USB1DP
+set_location_assignment PIN_Y10 -to DRAM_ADDR[4]
+set_location_assignment PIN_U10 -to DRAM_ADDR[5]
+set_location_assignment PIN_T10 -to DRAM_ADDR[6]
+set_location_assignment PIN_AA9 -to DRAM_ADDR[7]
+set_location_assignment PIN_W9 -to DRAM_ADDR[8]
+set_location_assignment PIN_Y9 -to DRAM_ADDR[9]
+set_location_assignment PIN_V9 -to DRAM_ADDR[11]
+set_location_assignment PIN_T9 -to DRAM_ADDR[12]
+set_location_assignment PIN_AB8 -to DRAM_CKE
+set_location_assignment PIN_AA8 -to DRAM_CLK
+set_location_assignment PIN_U8 -to DRAM_UDQM
+set_location_assignment PIN_W8 -to DRAM_DQ[8]
+set_location_assignment PIN_T8 -to DRAM_DQ[9]
+set_location_assignment PIN_AB7 -to DRAM_DQ[10]
+set_location_assignment PIN_AA7 -to DRAM_DQ[11]
+set_location_assignment PIN_U7 -to DRAM_DQ[12]
+set_location_assignment PIN_AB6 -to DRAM_DQ[13]
+set_location_assignment PIN_V6 -to DRAM_DQ[14]
+set_location_assignment PIN_AB5 -to DRAM_DQ[15]
+set_location_assignment PIN_U6 -to DRAM_ADDR[3]
+set_location_assignment PIN_T7 -to DRAM_ADDR[2]
+set_location_assignment PIN_R5 -to DRAM_ADDR[1]
+set_location_assignment PIN_R6 -to DRAM_ADDR[0]
+set_location_assignment PIN_R7 -to DRAM_ADDR[10]
+set_location_assignment PIN_P6 -to DRAM_BA_1
+set_location_assignment PIN_P7 -to DRAM_BA_0
+set_location_assignment PIN_P8 -to DRAM_CS_N
+set_location_assignment PIN_N6 -to DRAM_RAS_N
+set_location_assignment PIN_N8 -to DRAM_CAS_N
+set_location_assignment PIN_N9 -to DRAM_WE_N
+set_location_assignment PIN_M6 -to DRAM_LDQM
+set_location_assignment PIN_M7 -to DRAM_DQ[7]
+set_location_assignment PIN_M8 -to DRAM_DQ[6]
+set_location_assignment PIN_L7 -to DRAM_DQ[5]
+set_location_assignment PIN_L8 -to DRAM_DQ[4]
+set_location_assignment PIN_K7 -to DRAM_DQ[0]
+set_location_assignment PIN_K9 -to DRAM_DQ[1]
+set_location_assignment PIN_J7 -to DRAM_DQ[2]
+set_location_assignment PIN_J8 -to DRAM_DQ[3]
+set_location_assignment PIN_H6 -to ADC_SDA
+set_location_assignment PIN_G6 -to ADC_SCL
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to GPIOA[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[16]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[17]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[18]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[19]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[20]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[21]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[22]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[23]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[24]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[25]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[26]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[27]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[28]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[29]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[30]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[31]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[32]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[33]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[34]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOA[35]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[16]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[17]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[18]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[19]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[20]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[21]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[22]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[23]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[24]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[25]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[26]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[27]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[28]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[29]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[30]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[31]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[32]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[33]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[34]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOB[35]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[16]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[17]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[18]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[19]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[20]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[21]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[22]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[23]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[24]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[25]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[26]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[27]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[28]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[29]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[30]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[31]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[32]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[33]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[34]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to GPIOC[35]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_UDQM
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_ADDR[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_BA_1
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_BA_0
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_CS_N
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_RAS_N
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_CAS_N
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_WE_N
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_LDQM
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[15]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA_0
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA_1
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_UDQM
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_LDQM
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CS_N
+
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[15]
+
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[0]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[1]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[2]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[3]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[4]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[5]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[6]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[7]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[8]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[9]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[10]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[11]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[12]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[13]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[14]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[15]
+
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_DAT2
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_DAT1
+set_global_assignment -name DEVICE 5CEBA2F23C8
+
Index: eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.sdc
===================================================================
--- eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.sdc	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.sdc	(revision 473)
@@ -0,0 +1,4 @@
+create_clock -period 5MHz [get_ports CLOCK_5]
+derive_pll_clocks
+derive_clock_uncertainty
+
Index: eclaireXL/hardware/test/test_hdmi/pll2_sim/synopsys/vcsmx/synopsys_sim.setup
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2_sim/synopsys/vcsmx/synopsys_sim.setup	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2_sim/synopsys/vcsmx/synopsys_sim.setup	(revision 473)
@@ -0,0 +1,11 @@
+
+WORK > DEFAULT
+DEFAULT:      ./libraries/work/        
+work:         ./libraries/work/        
+altera:       ./libraries/altera/      
+lpm:          ./libraries/lpm/         
+sgate:        ./libraries/sgate/       
+altera_mf:    ./libraries/altera_mf/   
+altera_lnsim: ./libraries/altera_lnsim/
+cyclonev:     ./libraries/cyclonev/    
+LIBRARY_SCAN = TRUE
Index: eclaireXL/hardware/test/test_hdmi/pll2_sim.f
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2_sim.f	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2_sim.f	(revision 473)
@@ -0,0 +1 @@
+pll2_sim/pll2.vho
Index: eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.vhd
===================================================================
--- eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.vhd	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/atari800core_eclaireXL.vhd	(revision 473)
@@ -0,0 +1,252 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_MISC.all;
+
+LIBRARY work;
+
+ENTITY atari800core_eclaireXL IS 
+	PORT
+	(
+		CLOCK_5 :  IN  STD_LOGIC;
+
+		PS2CLK :  IN  STD_LOGIC;
+		PS2DAT :  IN  STD_LOGIC;
+
+		GPIOA :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIOB :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIOC:  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+
+		DRAM_BA_0 :  OUT  STD_LOGIC;
+		DRAM_BA_1 :  OUT  STD_LOGIC;
+		DRAM_CS_N :  OUT  STD_LOGIC;
+		DRAM_RAS_N :  OUT  STD_LOGIC;
+		DRAM_CAS_N :  OUT  STD_LOGIC;
+		DRAM_WE_N :  OUT  STD_LOGIC;
+		DRAM_LDQM :  OUT  STD_LOGIC;
+		DRAM_UDQM :  OUT  STD_LOGIC;
+		DRAM_CLK :  OUT  STD_LOGIC;
+		DRAM_CKE :  OUT  STD_LOGIC;
+		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		SD_WRITEPROTECT : IN STD_LOGIC;
+		SD_DETECT : IN STD_LOGIC;
+		SD_DAT1 : OUT STD_LOGIC;
+		SD_DAT0 :  IN  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_DAT3 :  OUT  STD_LOGIC;
+		SD_DAT2 : OUT STD_LOGIC;
+
+		--VGA_VS :  OUT  STD_LOGIC;
+		--VGA_HS :  OUT  STD_LOGIC;
+		--VGA_B :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		--VGA_G :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		--VGA_R :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		--TMDS :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+		VGA_BLANK_N : OUT STD_LOGIC;
+		VGA_CLK : OUT STD_LOGIC;
+		
+		AUDIO_LEFT : OUT STD_LOGIC;
+		AUDIO_RIGHT : OUT STD_LOGIC;
+
+		USB2DM: INOUT STD_LOGIC;
+		USB2DP: INOUT STD_LOGIC;
+		USB1DM: INOUT STD_LOGIC;
+		USB1DP: INOUT STD_LOGIC;
+		
+		ADC_SDA: INOUT STD_LOGIC;
+		ADC_SCL: INOUT STD_LOGIC
+	);
+END atari800core_eclaireXL;
+
+ARCHITECTURE vhdl OF atari800core_eclaireXL IS 
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+component pll2
+	port (
+		refclk   : in  std_logic := '0'; --  refclk.clk
+		rst      : in  std_logic := '0'; --   reset.reset
+		outclk_0 : out std_logic;        -- outclk0.clk
+		outclk_1 : out std_logic;        -- outclk1.clk
+		locked   : out std_logic         --  locked.export
+	);
+end component;
+
+-- SYSTEM
+SIGNAL CLK : STD_LOGIC;
+SIGNAL CLK_114 : STD_LOGIC;
+SIGNAL SVIDEO_ECS_CLK : STD_LOGIC;
+SIGNAL PLL_LOCKED : STD_LOGIC;
+
+-- ModeLine "720x576@50"      27     720  732  795  864  576  581  586  625 -hsync -vsync (576p)
+-- ModeLine "768x576@50"      29.5   768  789  858  944  576  581  586  625 -hsync -vsync
+-- ModeLine " 640x 480@60Hz"  25.20  640  656  752  800  480  490  492  525 -HSync -VSync
+-- ModeLine " 720x 480@60Hz"  27.00  720  736  798  858  480  489  495  525 -HSync -VSync
+-- Modeline " 800x 600@60Hz"  40.00  800  840  968 1056  600  601  605  628 +HSync +VSync
+-- ModeLine "1024x 768@60Hz"  65.00 1024 1048 1184 1344  768  771  777  806 -HSync -VSync
+-- ModeLine "1280x 720@60Hz"  74.25 1280 1390 1430 1650  720  725  730  750 +HSync +VSync
+-- ModeLine "1280x 768@60Hz"  80.14 1280 1344 1480 1680  768  769  772  795 +HSync +VSync
+-- ModeLine "1280x 800@60Hz"  83.46 1280 1344 1480 1680  800  801  804  828 +HSync +VSync
+-- ModeLine "1280x 960@60Hz" 108.00 1280 1376 1488 1800  960  961  964 1000 +HSync +VSync
+-- ModeLine "1280x1024@60Hz" 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +HSync +VSync
+-- ModeLine "1360x 768@60Hz"  85.50 1360 1424 1536 1792  768  771  778  795 -HSync -VSync
+-- ModeLine "1920x1080@25Hz"  74.25 1920 2448 2492 2640 1080 1084 1089 1125 +HSync +VSync
+-- ModeLine "1920x1080@30Hz"  89.01 1920 2448 2492 2640 1080 1084 1089 1125 +HSync +VSync
+
+-- Horizontal Timing constants  
+constant h_pixels_across	: integer := 720 - 1;
+constant h_sync_on		: integer := 732 - 1;
+constant h_sync_off		: integer := 795 - 1;
+constant h_end_count		: integer := 864 - 1;
+-- Vertical Timing constants
+constant v_pixels_down		: integer := 576 - 1;
+constant v_sync_on		: integer := 581 - 1;
+constant v_sync_off		: integer := 586 - 1;
+constant v_end_count		: integer := 625 - 1;
+
+signal hcnt		: std_logic_vector(11 downto 0) := "000000000000"; 	-- horizontal pixel counter
+signal vcnt		: std_logic_vector(11 downto 0) := "000000000000"; 	-- vertical line counter
+signal hsync		: std_logic;
+signal vsync		: std_logic;
+signal blank		: std_logic;
+signal shift		: std_logic_vector(7 downto 0);
+signal red		: std_logic_vector(7 downto 0);
+signal green		: std_logic_vector(7 downto 0);
+signal blue		: std_logic_vector(7 downto 0);
+signal clk_hdmi		: std_logic;
+signal clk_vga		: std_logic;
+
+
+signal TMDS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+BEGIN 
+
+DRAM_CS_N <= '1';
+DRAM_BA_0 <= 'Z';
+DRAM_BA_1 <= 'Z';
+DRAM_RAS_N <= 'Z';
+DRAM_CAS_N <= 'Z';
+DRAM_WE_N <= 'Z';
+DRAM_LDQM <= 'Z';
+DRAM_UDQM <= 'Z';
+DRAM_CKE <= 'Z';
+DRAM_ADDR <= (others=>'Z');
+DRAM_DQ <= (others=>'Z');
+
+SD_DAT1 <= 'Z';
+SD_DAT2 <= 'Z';
+SD_DAT3 <= 'Z';
+SD_CMD <= 'Z';
+SD_CLK <= 'Z';
+
+USB2DM <= 'Z';
+USB2DP <= 'Z';
+USB1DM <= 'Z';
+USB1DP <= 'Z';
+		
+ADC_SDA <= 'Z';
+ADC_SCL <= 'Z';
+
+--VGA_VS <= 'Z';
+--VGA_HS <= 'Z';
+--VGA_B <= (others=>'Z');
+--VGA_G <= (others=>'Z');
+--VGA_R <= (others=>'Z');
+VGA_BLANK_N <= '0';
+VGA_CLK <= '0';
+		
+AUDIO_LEFT <= 'Z';
+AUDIO_RIGHT <= 'Z';
+
+
+--GPIOA <= shift_reg(35 downto 0);
+GPIOB <= (others=>'0');
+GPIOC <= (others=>'0');
+
+GPIOA(35 downto 16) <= (others=>'0');
+GPIOA(0) <= '0';
+GPIOA(11 downto 5) <= (others=>'0');
+
+GPIOA(1) <= TMDS(7); -- D2P
+GPIOA(2) <= TMDS(6); -- D2N
+GPIOA(3) <= TMDS(5); -- D1P
+GPIOA(4) <= TMDS(4); -- D1N
+
+GPIOA(12) <= TMDS(2); -- D0N
+GPIOA(13) <= TMDS(3); -- D0P
+GPIOA(14) <= TMDS(0); -- C N
+GPIOA(15) <= TMDS(1); -- C P
+
+-- PLL
+pll2_inst: pll2
+port map (
+	refclk		=> CLOCK_5,		-- 5.0 MHz
+
+	-- out
+	locked		=> open,
+	outclk_0	=> clk_hdmi,	-- clk_vga * 5
+	outclk_1	=> clk_vga);
+
+-- HDMI
+hdmi_inst: entity work.hdmi
+port map (
+	I_CLK_PIXEL	=> clk_vga,
+	I_CLK_TMDS	=> clk_hdmi,	-- 472.6 MHz max
+
+	I_HSYNC		=> hsync,
+	I_VSYNC		=> vsync,
+	I_BLANK		=> blank,
+	I_RED		=> red,
+	I_GREEN		=> green,
+	I_BLUE		=> blue,
+	O_TMDS		=> TMDS);
+
+	process (clk_vga, hcnt)
+	begin
+		if clk_vga'event and clk_vga = '1' then
+			if hcnt = h_end_count then
+				hcnt <= (others => '0');
+			else
+				hcnt <= hcnt + 1;
+			end if;
+			if hcnt = h_sync_on then
+				if vcnt = v_end_count then
+					vcnt <= (others => '0');
+					shift <= shift + 1;
+				else
+					vcnt <= vcnt + 1;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	hsync	<= '0' when (hcnt <= h_sync_on) or (hcnt > h_sync_off) else '1';
+	vsync	<= '0' when (vcnt <= v_sync_on) or (vcnt > v_sync_off) else '1';
+	blank	<= '1' when (hcnt > h_pixels_across) or (vcnt > v_pixels_down) else '0';
+
+	red	<= "11111111" when hcnt = 0 or hcnt = h_pixels_across or vcnt = 0 or vcnt = v_pixels_down else (hcnt(7 downto 0) + shift) and "11111111";
+	green	<= "11111111" when hcnt = 0 or hcnt = h_pixels_across or vcnt = 0 or vcnt = v_pixels_down else (vcnt(7 downto 0) + shift) and "11111111";
+	blue	<= "11111111" when hcnt = 0 or hcnt = h_pixels_across or vcnt = 0 or vcnt = v_pixels_down else (hcnt(7 downto 0) + vcnt(7 downto 0) - shift) and "11111111";
+
+END vhdl;
Index: eclaireXL/hardware/test/test_hdmi/build.sh
===================================================================
--- eclaireXL/hardware/test/test_hdmi/build.sh	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/build.sh	(revision 473)
@@ -0,0 +1,68 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $wanted_variant = shift @ARGV;
+
+my $name="eclaireXL";
+
+#variants...
+my $PAL = 1;
+my $NTSC = 0;
+
+my $RGB = 1; # i.e. not scandoubled
+my $VGA = 2;
+
+#Added like this to the generated qsf
+#set_parameter -name TV 1
+
+my %variants = 
+(
+#	"PAL" => 
+#	{
+#		"TV" => $PAL
+#	},
+#	"NTSC" =>
+#	{
+#		"TV" => $NTSC
+#	},
+	"A2EBA_RGB" =>
+	{
+	}
+);
+
+if (not defined $wanted_variant or (not exists $variants{$wanted_variant} and $wanted_variant ne "ALL"))
+{
+	die "Provide variant of ALL or ".join ",",sort keys %variants;
+}
+
+foreach my $variant (sort keys %variants)
+{
+	next if ($wanted_variant ne $variant and $wanted_variant ne "ALL");
+	print "Building $variant of $name\n";
+
+	my $dir = "build_$variant";
+	`rm -rf $dir`;
+	mkdir $dir;
+	`cp -a hdmi $dir`;
+	`cp -a pll2* $dir`;
+	`cp *.v $dir`;
+	`cp *.vhd* $dir`;
+	`cp atari800core*.sdc $dir`;
+	`mkdir $dir/common`;
+
+	chdir $dir;
+	`../../../../makeqsf ../atari800core_eclaireXL.qsf ./hdmi`;
+
+	foreach my $key (sort keys %{$variants{$variant}})
+	{
+		my $val = $variants{$variant}->{$key};
+		`echo set_parameter -name $key $val >> atari800core_eclaireXL.qsf`;
+	}
+
+	`quartus_sh --flow compile atari800core_eclaireXL > build.log 2> build.err`;
+
+#	`quartus_cpf --convert ../output_file.cof`;
+	
+	chdir "..";
+}
+

Property changes on: eclaireXL/hardware/test/test_hdmi/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.ppf
===================================================================
--- eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.ppf	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.ppf	(revision 473)
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone V" variation_name="altddio_out1" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h[7..0]" direction="input" scope="external"  />
+<pin name="datain_l[7..0]" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout[7..0]" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.qip
===================================================================
--- eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.qip	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.qip	(revision 473)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "15.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"]
Index: eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.vhd
===================================================================
--- eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.vhd	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/hdmi/altddio_out1.vhd	(revision 473)
@@ -0,0 +1,111 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: ALTDDIO_OUT 
+
+-- ============================================================
+-- File Name: altddio_out1.vhd
+-- Megafunction Name(s):
+-- 			ALTDDIO_OUT
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 15.0.0 Build 145 04/22/2015 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus II License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY altddio_out1 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END altddio_out1;
+
+
+ARCHITECTURE SYN OF altddio_out1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	dataout    <= sub_wire0(7 DOWNTO 0);
+
+	ALTDDIO_OUT_component : ALTDDIO_OUT
+	GENERIC MAP (
+		extend_oe_disable => "OFF",
+		intended_device_family => "Cyclone V",
+		invert_output => "OFF",
+		lpm_hint => "UNUSED",
+		lpm_type => "altddio_out",
+		oe_reg => "UNREGISTERED",
+		power_up_high => "OFF",
+		width => 8
+	)
+	PORT MAP (
+		datain_h => datain_h,
+		datain_l => datain_l,
+		outclock => outclock,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "8"
+-- Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]"
+-- Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0
+-- Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]"
+-- Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0
+-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
+-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.vhd TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.qip TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf FALSE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.vhd FALSE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc FALSE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp FALSE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: eclaireXL/hardware/test/test_hdmi/hdmi/encoder.vhd
===================================================================
--- eclaireXL/hardware/test/test_hdmi/hdmi/encoder.vhd	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/hdmi/encoder.vhd	(revision 473)
@@ -0,0 +1,67 @@
+-------------------------------------------------------------------[21.06.2016]
+-- Encoder
+-------------------------------------------------------------------------------
+-- Engineer: MVV
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.std_logic_unsigned.all;
+
+
+entity encoder is
+port (
+	I_CLK		: in std_logic;
+	I_VD		: in std_logic_vector(7 downto 0);	-- video data (RED, GREEN or BLUE)
+	I_CD		: in std_logic_vector(1 downto 0);	-- control data
+	I_VDE		: in std_logic;				-- video data enable, to choose between CD (when VDE=0) and VD (when VDE=1)
+	O_TMDS		: out std_logic_vector(9 downto 0));
+end entity encoder;
+
+architecture rtl of encoder is
+   
+	signal nb1s		: std_logic_vector(3 downto 0);
+	signal x_nor		: std_logic;
+	signal balance_acc	: std_logic_vector(3 downto 0) := "0000";
+	signal balance		: std_logic_vector(3 downto 0);
+	signal balance_sign_eq	: std_logic;
+	signal invert_q_m	: std_logic;
+	signal balance_acc_inc	: std_logic_vector(3 downto 0);
+	signal balance_acc_new	: std_logic_vector(3 downto 0);
+	signal data		: std_logic_vector(9 downto 0);
+	signal code		: std_logic_vector(9 downto 0);
+	signal q_m		: std_logic_vector(8 downto 0);
+
+begin
+	
+	process (I_CLK)
+	begin
+		if (I_CLK'event and I_CLK = '1') then
+			if (I_VDE = '1') then 
+				O_TMDS <= data;
+				balance_acc <= balance_acc_new;
+			else
+				O_TMDS <= code;
+				balance_acc <= "0000";
+			end if;
+		end if;
+		
+		case I_CD is            
+			when "00"   => code <= "1101010100";
+			when "01"   => code <= "0010101011";
+			when "10"   => code <= "0101010100";
+			when others => code <= "1010101011";
+		end case;
+
+	end process;
+
+	nb1s		<= "000" & I_VD(0) + I_VD(1) + I_VD(2) + I_VD(3) + I_VD(4) + I_VD(5) + I_VD(6) + I_VD(7);
+	x_nor		<= '1' when (nb1s > "0100") or (nb1s = "0100" and I_VD(0) = '0') else '0';
+	q_m		<= not(x_nor) & (q_m(6 downto 0) xor I_VD(7 downto 1) xor (x_nor & x_nor & x_nor & x_nor & x_nor & x_nor & x_nor)) & I_VD(0);
+	balance		<= ("000" & q_m(0) + q_m(1) + q_m(2) + q_m(3) + q_m(4) + q_m(5) + q_m(6) + q_m(7)) - "0100";
+	data		<= invert_q_m & q_m(8) & q_m(7 downto 0) xor invert_q_m & invert_q_m & invert_q_m & invert_q_m & invert_q_m & invert_q_m & invert_q_m & invert_q_m;
+	balance_sign_eq	<= '1' when balance(3) = balance_acc(3) else '0';
+	invert_q_m	<= not(q_m(8)) when balance = "0000" or balance_acc = "0000" else balance_sign_eq;
+	balance_acc_inc	<= balance - ("000" & ((q_m(8) xor not(balance_sign_eq)) and (not((balance(3) or balance(2) or balance(1) or balance(0) or balance_acc(3) or balance_acc(2) or balance_acc(1) or balance_acc(0))))));
+	balance_acc_new	<= balance_acc - balance_acc_inc when invert_q_m = '1' else balance_acc + balance_acc_inc;
+	
+end architecture rtl;
Index: eclaireXL/hardware/test/test_hdmi/hdmi/hdmi.vhd
===================================================================
--- eclaireXL/hardware/test/test_hdmi/hdmi/hdmi.vhd	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/hdmi/hdmi.vhd	(revision 473)
@@ -0,0 +1,88 @@
+-------------------------------------------------------------------[09.05.2016]
+-- HDMI
+-------------------------------------------------------------------------------
+-- Engineer: MVV
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.std_logic_unsigned.all;
+
+entity hdmi is
+port (
+	I_CLK_PIXEL	: in std_logic;		-- pixelclock
+	I_CLK_TMDS	: in std_logic;		-- pixelclock*5
+	I_HSYNC		: in std_logic;
+	I_VSYNC		: in std_logic;
+	I_BLANK		: in std_logic;
+	I_RED		: in std_logic_vector(7 downto 0);
+	I_GREEN		: in std_logic_vector(7 downto 0);
+	I_BLUE		: in std_logic_vector(7 downto 0);
+	O_TMDS		: out std_logic_vector(7 downto 0));
+end entity hdmi;
+
+architecture rtl of hdmi is
+   
+	signal r	: std_logic_vector(9 downto 0);
+	signal g	: std_logic_vector(9 downto 0);
+	signal b	: std_logic_vector(9 downto 0);
+	signal mod5	: std_logic_vector(2 downto 0) := "000";	-- modulus 5 counter
+	signal shift_r	: std_logic_vector(9 downto 0) := "0000000000";
+	signal shift_g	: std_logic_vector(9 downto 0) := "0000000000";
+	signal shift_b	: std_logic_vector(9 downto 0) := "0000000000";
+	signal shift_clk : std_logic_vector(9 downto 0) := "0000000000";
+
+begin
+
+	encode_r : entity work.encoder
+	port map (
+		I_CLK	=> I_CLK_PIXEL,
+		I_VD	=> I_RED,
+		I_CD	=> "00",
+		I_VDE	=> not(I_BLANK),
+		O_TMDS	=> r);
+
+	encode_g : entity work.encoder
+	port map (
+		I_CLK   => I_CLK_PIXEL,
+		I_VD    => I_GREEN,
+		I_CD    => "00",
+		I_VDE   => not(I_BLANK),
+		O_TMDS  => g);
+
+	encode_b : entity work.encoder
+	port map (
+		I_CLK   => I_CLK_PIXEL,
+		I_VD    => I_BLUE,
+		I_CD    => (I_VSYNC & I_HSYNC),
+		I_VDE   => not(I_BLANK),
+		O_TMDS  => b);
+
+	process (I_CLK_TMDS)
+	begin
+		if (I_CLK_TMDS'event and I_CLK_TMDS = '1') then
+			if mod5(2) = '1' then
+				mod5 <= "000";
+				shift_r <= r;
+				shift_g <= g;
+				shift_b <= b;
+				shift_clk <= "0000011111";
+			else
+				mod5 <= mod5 + "001";
+				shift_r <= "00" & shift_r(9 downto 2);
+				shift_g <= "00" & shift_g(9 downto 2);
+				shift_b <= "00" & shift_b(9 downto 2);
+				shift_clk <= "00" & shift_clk(9 downto 2);
+			end if;
+		end if;
+	end process;
+	
+	ddio_inst : entity work.altddio_out1
+	port map (
+		datain_h => shift_r(0) & not(shift_r(0)) & shift_g(0) & not(shift_g(0)) & shift_b(0) & not(shift_b(0)) & shift_clk(0) & not(shift_clk(0)),
+		datain_l => shift_r(1) & not(shift_r(1)) & shift_g(1) & not(shift_g(1)) & shift_b(1) & not(shift_b(1)) & shift_clk(1) & not(shift_clk(1)),
+		outclock => I_CLK_TMDS,
+		dataout  => O_TMDS);
+
+end architecture rtl;
+
+
Index: eclaireXL/hardware/test/test_hdmi/pll2/pll2_0002.qip
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2/pll2_0002.qip	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2/pll2_0002.qip	(revision 473)
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll2_0002*|altera_pll:altera_pll_i*|*"
+ 
+set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll2_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll2_0002*|altera_pll:altera_pll_i*|*"
Index: eclaireXL/hardware/test/test_hdmi/pll2/pll2_0002.v
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2/pll2_0002.v	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2/pll2_0002.v	(revision 473)
@@ -0,0 +1,90 @@
+`timescale 1ns/10ps
+module  pll2_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("false"),
+		.reference_clock_frequency("5.0 MHz"),
+		.operation_mode("normal"),
+		.number_of_clocks(2),
+		.output_clock_frequency0("135.000000 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("27.000000 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("0 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
Index: eclaireXL/hardware/test/test_hdmi/pll2.bsf
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2.bsf	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2.bsf	(revision 473)
@@ -0,0 +1,93 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus II License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 184)
+	(text "pll2" (rect 71 -1 82 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 20 180)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
+		(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
+		(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 48 112)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
+		(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 112 72)(line_width 1))
+	)
+	(port
+		(pt 160 112)
+		(output)
+		(text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8)))
+		(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
+		(line (pt 160 112)(pt 112 112)(line_width 1))
+	)
+	(port
+		(pt 160 152)
+		(output)
+		(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
+		(text "locked" (rect 127 141 163 152)(font "Arial" (font_size 8)))
+		(line (pt 160 152)(pt 112 152)(line_width 1))
+	)
+	(drawing
+		(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
+		(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
+		(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
+		(text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0)))
+		(text "locked" (rect 113 123 262 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 82 147 200 304)(font "Arial" (color 0 0 0)))
+		(text " altera_pll " (rect 118 168 308 346)(font "Arial" ))
+		(line (pt 48 32)(pt 112 32)(line_width 1))
+		(line (pt 112 32)(pt 112 168)(line_width 1))
+		(line (pt 48 168)(pt 112 168)(line_width 1))
+		(line (pt 48 32)(pt 48 168)(line_width 1))
+		(line (pt 49 52)(pt 49 76)(line_width 1))
+		(line (pt 50 52)(pt 50 76)(line_width 1))
+		(line (pt 49 92)(pt 49 116)(line_width 1))
+		(line (pt 50 92)(pt 50 116)(line_width 1))
+		(line (pt 111 52)(pt 111 76)(line_width 1))
+		(line (pt 110 52)(pt 110 76)(line_width 1))
+		(line (pt 111 92)(pt 111 116)(line_width 1))
+		(line (pt 110 92)(pt 110 116)(line_width 1))
+		(line (pt 111 132)(pt 111 156)(line_width 1))
+		(line (pt 110 132)(pt 110 156)(line_width 1))
+		(line (pt 0 0)(pt 160 0)(line_width 1))
+		(line (pt 160 0)(pt 160 184)(line_width 1))
+		(line (pt 0 184)(pt 160 184)(line_width 1))
+		(line (pt 0 0)(pt 0 184)(line_width 1))
+	)
+)
Index: eclaireXL/hardware/test/test_hdmi/pll2.cmp
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2.cmp	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2.cmp	(revision 473)
@@ -0,0 +1,10 @@
+	component pll2 is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			outclk_1 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll2;
+
Index: eclaireXL/hardware/test/test_hdmi/pll2.ppf
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2.ppf	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2.ppf	(revision 473)
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan
+ variation_name="pll2"
+ megafunction_name="ALTERA_PLL"
+ intended_family="Cyclone V"
+ specifies="all_ports">
+ <global>
+  <pin name="refclk" direction="input" scope="external" />
+  <pin name="rst" direction="input" scope="external" />
+  <pin name="outclk_0" direction="output" scope="external" />
+  <pin name="outclk_1" direction="output" scope="external" />
+  <pin name="locked" direction="output" scope="external" />
+ </global>
+</pinplan>
Index: eclaireXL/hardware/test/test_hdmi/pll2.qip
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2.qip	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2.qip	(revision 473)
@@ -0,0 +1,338 @@
+set_global_assignment -entity "pll2" -library "pll2" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll2" -library "pll2" -name IP_TOOL_VERSION "15.0"
+set_global_assignment -entity "pll2" -library "pll2" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll2" -name MISC_FILE [file join $::quartus(qip_path) "pll2.cmp"]
+set_global_assignment -entity "pll2" -library "pll2" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll2" -library "pll2" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll2" -library "pll2" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_NAME "cGxsMg=="
+set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_VERSION "MTUuMA=="
+set_global_assignment -entity "pll2" -library "pll2" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_NAME "cGxsMl8wMDAy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_VERSION "MTUuMA=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::OA==::RGV2aWNlIFNwZWVkIEdyYWRl"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NS4w::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NS4wIE1Ieg==::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTM1LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTA4::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTA4::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MjA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTM1LjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjcuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NTQsNTQsMjU2LDI1NixmYWxzZSx0cnVlLGZhbHNlLGZhbHNlLDIsMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMCwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyLDIwLDE0MDAwLDU0MC4wIE1IeiwxLGdjbGssZ2xiLGZiXzEscGhfbXV4X2NsayxmYWxzZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll2" -name VHDL_FILE [file join $::quartus(qip_path) "pll2.vhd"]
+set_global_assignment -library "pll2" -name VERILOG_FILE [file join $::quartus(qip_path) "pll2/pll2_0002.v"]
+set_global_assignment -library "pll2" -name QIP_FILE [file join $::quartus(qip_path) "pll2/pll2_0002.qip"]
+
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_TOOL_VERSION "15.0"
+set_global_assignment -entity "pll2_0002" -library "pll2" -name IP_TOOL_ENV "mwpim"
Index: eclaireXL/hardware/test/test_hdmi/pll2.sip
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2.sip	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2.sip	(revision 473)
@@ -0,0 +1,6 @@
+set_global_assignment -entity "pll2" -library "lib_pll2" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll2" -library "lib_pll2" -name IP_TOOL_VERSION "15.0"
+set_global_assignment -entity "pll2" -library "lib_pll2" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_pll2" -name SPD_FILE [file join $::quartus(sip_path) "pll2.spd"]
+
+set_global_assignment -library "lib_pll2" -name MISC_FILE [file join $::quartus(sip_path) "pll2_sim/pll2.vho"]
Index: eclaireXL/hardware/test/test_hdmi/pll2.spd
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2.spd	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2.spd	(revision 473)
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file path="pll2_sim/pll2.vho" type="VHDL" />
+ <topLevel name="pll2" />
+ <deviceFamily name="cyclonev" />
+</simPackage>
Index: eclaireXL/hardware/test/test_hdmi/pll2.vhd
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2.vhd	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2.vhd	(revision 473)
@@ -0,0 +1,274 @@
+-- megafunction wizard: %Altera PLL v15.0%
+-- GENERATION: XML
+-- pll2.vhd
+
+-- Generated using ACDS version 15.0 145
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity pll2 is
+	port (
+		refclk   : in  std_logic := '0'; --  refclk.clk
+		rst      : in  std_logic := '0'; --   reset.reset
+		outclk_0 : out std_logic;        -- outclk0.clk
+		outclk_1 : out std_logic;        -- outclk1.clk
+		locked   : out std_logic         --  locked.export
+	);
+end entity pll2;
+
+architecture rtl of pll2 is
+	component pll2_0002 is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			outclk_1 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll2_0002;
+
+begin
+
+	pll2_inst : component pll2_0002
+		port map (
+			refclk   => refclk,   --  refclk.clk
+			rst      => rst,      --   reset.reset
+			outclk_0 => outclk_0, -- outclk0.clk
+			outclk_1 => outclk_1, -- outclk1.clk
+			locked   => locked    --  locked.export
+		);
+
+end architecture rtl; -- of pll2
+-- Retrieval info: <?xml version="1.0"?>
+--<!--
+--	Generated by Altera MegaWizard Launcher Utility version 1.0
+--	************************************************************
+--	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--	************************************************************
+--	Copyright (C) 1991-2016 Altera Corporation
+--	Any megafunction design, and related net list (encrypted or decrypted),
+--	support information, device programming or simulation file, and any other
+--	associated documentation or information provided by Altera or a partner
+--	under Altera's Megafunction Partnership Program may be used only to
+--	program PLD devices (but not masked PLD devices) from Altera.  Any other
+--	use of such megafunction design, net list, support information, device
+--	programming or simulation file, or any other related documentation or
+--	information is prohibited for any other purpose, including, but not
+--	limited to modification, reverse engineering, de-compiling, or use with
+--	any other silicon devices, unless such use is explicitly licensed under
+--	a separate agreement with Altera or a megafunction partner.  Title to
+--	the intellectual property, including patents, copyrights, trademarks,
+--	trade secrets, or maskworks, embodied in any such megafunction design,
+--	net list, support information, device programming or simulation file, or
+--	any other related documentation or information provided by Altera or a
+--	megafunction partner, remains with Altera, the megafunction partner, or
+--	their respective licensors.  No other licenses, including any licenses
+--	needed under any third party's intellectual property, are provided herein.
+---->
+-- Retrieval info: <instance entity-name="altera_pll" version="15.0" >
+-- Retrieval info: 	<generic name="debug_print_output" value="false" />
+-- Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+-- Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+-- Retrieval info: 	<generic name="device" value="Unknown" />
+-- Retrieval info: 	<generic name="gui_device_speed_grade" value="8" />
+-- Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
+-- Retrieval info: 	<generic name="gui_reference_clock_frequency" value="5.0" />
+-- Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+-- Retrieval info: 	<generic name="gui_operation_mode" value="normal" />
+-- Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+-- Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+-- Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+-- Retrieval info: 	<generic name="gui_use_locked" value="true" />
+-- Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+-- Retrieval info: 	<generic name="gui_number_of_clocks" value="2" />
+-- Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
+-- Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+-- Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+-- Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency0" value="135.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency1" value="27.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency4" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency5" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency6" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+-- Retrieval info: 	<generic name="gui_pll_auto_reset" value="Off" />
+-- Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+-- Retrieval info: 	<generic name="gui_en_reconf" value="false" />
+-- Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+-- Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+-- Retrieval info: 	<generic name="gui_phout_division" value="1" />
+-- Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+-- Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+-- Retrieval info: 	<generic name="gui_dps_num" value="1" />
+-- Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+-- Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+-- Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+-- Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+-- Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+-- Retrieval info: 	<generic name="gui_active_clk" value="false" />
+-- Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+-- Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+-- Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+-- Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+-- Retrieval info: </instance>
+-- IPFS_FILES : pll2.vho
+-- RELATED_FILES: pll2.vhd, pll2_0002.v
Index: eclaireXL/hardware/test/test_hdmi/pll2.xml
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2.xml	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2.xml	(revision 473)
@@ -0,0 +1,204 @@
+<?xml version="1.0"?>
+<instance entity-name="altera_pll" version="15.0" >
+<generic name="debug_print_output" value="false" />
+<generic name="debug_use_rbc_taf_method" value="false" />
+<generic name="device_family" value="Cyclone V" />
+<generic name="device" value="Unknown" />
+<generic name="gui_device_speed_grade" value="8" />
+<generic name="gui_pll_mode" value="Integer-N PLL" />
+<generic name="gui_reference_clock_frequency" value="5.0" />
+<generic name="gui_channel_spacing" value="0.0" />
+<generic name="gui_operation_mode" value="normal" />
+<generic name="gui_feedback_clock" value="Global Clock" />
+<generic name="gui_fractional_cout" value="32" />
+<generic name="gui_dsm_out_sel" value="1st_order" />
+<generic name="gui_use_locked" value="true" />
+<generic name="gui_en_adv_params" value="false" />
+<generic name="gui_number_of_clocks" value="2" />
+<generic name="gui_multiply_factor" value="1" />
+<generic name="gui_frac_multiply_factor" value="1" />
+<generic name="gui_divide_factor_n" value="1" />
+<generic name="gui_cascade_counter0" value="false" />
+<generic name="gui_output_clock_frequency0" value="200.0" />
+<generic name="gui_divide_factor_c0" value="1" />
+<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+<generic name="gui_ps_units0" value="ps" />
+<generic name="gui_phase_shift0" value="0" />
+<generic name="gui_phase_shift_deg0" value="0.0" />
+<generic name="gui_actual_phase_shift0" value="0" />
+<generic name="gui_duty_cycle0" value="50" />
+<generic name="gui_cascade_counter1" value="false" />
+<generic name="gui_output_clock_frequency1" value="40.0" />
+<generic name="gui_divide_factor_c1" value="1" />
+<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+<generic name="gui_ps_units1" value="ps" />
+<generic name="gui_phase_shift1" value="0" />
+<generic name="gui_phase_shift_deg1" value="0.0" />
+<generic name="gui_actual_phase_shift1" value="0" />
+<generic name="gui_duty_cycle1" value="50" />
+<generic name="gui_cascade_counter2" value="false" />
+<generic name="gui_output_clock_frequency2" value="100.0" />
+<generic name="gui_divide_factor_c2" value="1" />
+<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+<generic name="gui_ps_units2" value="ps" />
+<generic name="gui_phase_shift2" value="0" />
+<generic name="gui_phase_shift_deg2" value="0.0" />
+<generic name="gui_actual_phase_shift2" value="0" />
+<generic name="gui_duty_cycle2" value="50" />
+<generic name="gui_cascade_counter3" value="false" />
+<generic name="gui_output_clock_frequency3" value="100.0" />
+<generic name="gui_divide_factor_c3" value="1" />
+<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+<generic name="gui_ps_units3" value="ps" />
+<generic name="gui_phase_shift3" value="0" />
+<generic name="gui_phase_shift_deg3" value="0.0" />
+<generic name="gui_actual_phase_shift3" value="0" />
+<generic name="gui_duty_cycle3" value="50" />
+<generic name="gui_cascade_counter4" value="false" />
+<generic name="gui_output_clock_frequency4" value="100.0" />
+<generic name="gui_divide_factor_c4" value="1" />
+<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+<generic name="gui_ps_units4" value="ps" />
+<generic name="gui_phase_shift4" value="0" />
+<generic name="gui_phase_shift_deg4" value="0.0" />
+<generic name="gui_actual_phase_shift4" value="0" />
+<generic name="gui_duty_cycle4" value="50" />
+<generic name="gui_cascade_counter5" value="false" />
+<generic name="gui_output_clock_frequency5" value="100.0" />
+<generic name="gui_divide_factor_c5" value="1" />
+<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+<generic name="gui_ps_units5" value="ps" />
+<generic name="gui_phase_shift5" value="0" />
+<generic name="gui_phase_shift_deg5" value="0.0" />
+<generic name="gui_actual_phase_shift5" value="0" />
+<generic name="gui_duty_cycle5" value="50" />
+<generic name="gui_cascade_counter6" value="false" />
+<generic name="gui_output_clock_frequency6" value="100.0" />
+<generic name="gui_divide_factor_c6" value="1" />
+<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+<generic name="gui_ps_units6" value="ps" />
+<generic name="gui_phase_shift6" value="0" />
+<generic name="gui_phase_shift_deg6" value="0.0" />
+<generic name="gui_actual_phase_shift6" value="0" />
+<generic name="gui_duty_cycle6" value="50" />
+<generic name="gui_cascade_counter7" value="false" />
+<generic name="gui_output_clock_frequency7" value="100.0" />
+<generic name="gui_divide_factor_c7" value="1" />
+<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+<generic name="gui_ps_units7" value="ps" />
+<generic name="gui_phase_shift7" value="0" />
+<generic name="gui_phase_shift_deg7" value="0.0" />
+<generic name="gui_actual_phase_shift7" value="0" />
+<generic name="gui_duty_cycle7" value="50" />
+<generic name="gui_cascade_counter8" value="false" />
+<generic name="gui_output_clock_frequency8" value="100.0" />
+<generic name="gui_divide_factor_c8" value="1" />
+<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+<generic name="gui_ps_units8" value="ps" />
+<generic name="gui_phase_shift8" value="0" />
+<generic name="gui_phase_shift_deg8" value="0.0" />
+<generic name="gui_actual_phase_shift8" value="0" />
+<generic name="gui_duty_cycle8" value="50" />
+<generic name="gui_cascade_counter9" value="false" />
+<generic name="gui_output_clock_frequency9" value="100.0" />
+<generic name="gui_divide_factor_c9" value="1" />
+<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+<generic name="gui_ps_units9" value="ps" />
+<generic name="gui_phase_shift9" value="0" />
+<generic name="gui_phase_shift_deg9" value="0.0" />
+<generic name="gui_actual_phase_shift9" value="0" />
+<generic name="gui_duty_cycle9" value="50" />
+<generic name="gui_cascade_counter10" value="false" />
+<generic name="gui_output_clock_frequency10" value="100.0" />
+<generic name="gui_divide_factor_c10" value="1" />
+<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+<generic name="gui_ps_units10" value="ps" />
+<generic name="gui_phase_shift10" value="0" />
+<generic name="gui_phase_shift_deg10" value="0.0" />
+<generic name="gui_actual_phase_shift10" value="0" />
+<generic name="gui_duty_cycle10" value="50" />
+<generic name="gui_cascade_counter11" value="false" />
+<generic name="gui_output_clock_frequency11" value="100.0" />
+<generic name="gui_divide_factor_c11" value="1" />
+<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+<generic name="gui_ps_units11" value="ps" />
+<generic name="gui_phase_shift11" value="0" />
+<generic name="gui_phase_shift_deg11" value="0.0" />
+<generic name="gui_actual_phase_shift11" value="0" />
+<generic name="gui_duty_cycle11" value="50" />
+<generic name="gui_cascade_counter12" value="false" />
+<generic name="gui_output_clock_frequency12" value="100.0" />
+<generic name="gui_divide_factor_c12" value="1" />
+<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+<generic name="gui_ps_units12" value="ps" />
+<generic name="gui_phase_shift12" value="0" />
+<generic name="gui_phase_shift_deg12" value="0.0" />
+<generic name="gui_actual_phase_shift12" value="0" />
+<generic name="gui_duty_cycle12" value="50" />
+<generic name="gui_cascade_counter13" value="false" />
+<generic name="gui_output_clock_frequency13" value="100.0" />
+<generic name="gui_divide_factor_c13" value="1" />
+<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+<generic name="gui_ps_units13" value="ps" />
+<generic name="gui_phase_shift13" value="0" />
+<generic name="gui_phase_shift_deg13" value="0.0" />
+<generic name="gui_actual_phase_shift13" value="0" />
+<generic name="gui_duty_cycle13" value="50" />
+<generic name="gui_cascade_counter14" value="false" />
+<generic name="gui_output_clock_frequency14" value="100.0" />
+<generic name="gui_divide_factor_c14" value="1" />
+<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+<generic name="gui_ps_units14" value="ps" />
+<generic name="gui_phase_shift14" value="0" />
+<generic name="gui_phase_shift_deg14" value="0.0" />
+<generic name="gui_actual_phase_shift14" value="0" />
+<generic name="gui_duty_cycle14" value="50" />
+<generic name="gui_cascade_counter15" value="false" />
+<generic name="gui_output_clock_frequency15" value="100.0" />
+<generic name="gui_divide_factor_c15" value="1" />
+<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+<generic name="gui_ps_units15" value="ps" />
+<generic name="gui_phase_shift15" value="0" />
+<generic name="gui_phase_shift_deg15" value="0.0" />
+<generic name="gui_actual_phase_shift15" value="0" />
+<generic name="gui_duty_cycle15" value="50" />
+<generic name="gui_cascade_counter16" value="false" />
+<generic name="gui_output_clock_frequency16" value="100.0" />
+<generic name="gui_divide_factor_c16" value="1" />
+<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+<generic name="gui_ps_units16" value="ps" />
+<generic name="gui_phase_shift16" value="0" />
+<generic name="gui_phase_shift_deg16" value="0.0" />
+<generic name="gui_actual_phase_shift16" value="0" />
+<generic name="gui_duty_cycle16" value="50" />
+<generic name="gui_cascade_counter17" value="false" />
+<generic name="gui_output_clock_frequency17" value="100.0" />
+<generic name="gui_divide_factor_c17" value="1" />
+<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+<generic name="gui_ps_units17" value="ps" />
+<generic name="gui_phase_shift17" value="0" />
+<generic name="gui_phase_shift_deg17" value="0.0" />
+<generic name="gui_actual_phase_shift17" value="0" />
+<generic name="gui_duty_cycle17" value="50" />
+<generic name="gui_pll_auto_reset" value="Off" />
+<generic name="gui_pll_bandwidth_preset" value="Auto" />
+<generic name="gui_en_reconf" value="false" />
+<generic name="gui_en_dps_ports" value="false" />
+<generic name="gui_en_phout_ports" value="false" />
+<generic name="gui_phout_division" value="1" />
+<generic name="gui_mif_generate" value="false" />
+<generic name="gui_enable_mif_dps" value="false" />
+<generic name="gui_dps_cntr" value="C0" />
+<generic name="gui_dps_num" value="1" />
+<generic name="gui_dps_dir" value="Positive" />
+<generic name="gui_refclk_switch" value="false" />
+<generic name="gui_refclk1_frequency" value="100.0" />
+<generic name="gui_switchover_mode" value="Automatic Switchover" />
+<generic name="gui_switchover_delay" value="0" />
+<generic name="gui_active_clk" value="false" />
+<generic name="gui_clk_bad" value="false" />
+<generic name="gui_enable_cascade_out" value="false" />
+<generic name="gui_cascade_outclk_index" value="0" />
+<generic name="gui_enable_cascade_in" value="false" />
+<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+</instance>
Index: eclaireXL/hardware/test/test_hdmi/pll2_sim/aldec/rivierapro_setup.tcl
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2_sim/aldec/rivierapro_setup.tcl	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2_sim/aldec/rivierapro_setup.tcl	(revision 473)
@@ -0,0 +1,177 @@
+
+# (C) 2001-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 15.0 145 linux 2016.11.05.09:49:57
+
+# ----------------------------------------
+# Auto-generated simulation script
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "pll2"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/fpga/altera/15.0/quartus/"
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+  set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+  scripterconf -tcl
+  createdesign "$TOP_LEVEL_NAME"  "."
+  opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib      ./libraries     
+ensure_lib      ./libraries/work
+vmap       work ./libraries/work
+ensure_lib              ./libraries/altera      
+vmap       altera       ./libraries/altera      
+ensure_lib              ./libraries/lpm         
+vmap       lpm          ./libraries/lpm         
+ensure_lib              ./libraries/sgate       
+vmap       sgate        ./libraries/sgate       
+ensure_lib              ./libraries/altera_mf   
+vmap       altera_mf    ./libraries/altera_mf   
+ensure_lib              ./libraries/altera_lnsim
+vmap       altera_lnsim ./libraries/altera_lnsim
+ensure_lib              ./libraries/cyclonev    
+vmap       cyclonev     ./libraries/cyclonev    
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlog       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"    -work cyclonev    
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vcom       "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  vcom "$QSYS_SIMDIR/pll2.vho"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                     -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                       -- Compile device library files"
+  echo
+  echo "com                           -- Compile the design files in correct order"
+  echo
+  echo "elab                          -- Elaborate top level design"
+  echo
+  echo "elab_debug                    -- Elaborate the top level design with -dbg -O2 option"
+  echo
+  echo "ld                            -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                      -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                -- Top level module name."
+  echo
+  echo "SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                   -- Qsys base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR           -- Quartus installation directory."
+}
+file_copy
+h
Index: eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/cds.lib
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/cds.lib	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/cds.lib	(revision 473)
@@ -0,0 +1,17 @@
+
+DEFINE std            $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys       $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee           $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit          $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory   $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils        $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal     $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels       $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work           ./libraries/work/                         
+DEFINE altera         ./libraries/altera/                       
+DEFINE lpm            ./libraries/lpm/                          
+DEFINE sgate          ./libraries/sgate/                        
+DEFINE altera_mf      ./libraries/altera_mf/                    
+DEFINE altera_lnsim   ./libraries/altera_lnsim/                 
+DEFINE cyclonev       ./libraries/cyclonev/                     
Index: eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/hdl.var
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/hdl.var	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/hdl.var	(revision 473)
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
Index: eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/ncsim_setup.sh
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/ncsim_setup.sh	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/ncsim_setup.sh	(revision 473)
@@ -0,0 +1,107 @@
+
+# (C) 2001-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 15.0 145 linux 2016.11.05.09:49:57
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="pll2"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/home/markw/fpga/altera/15.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/cyclonev/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  ncvlog -sv  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  ncvlog      "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"  -work cyclonev    
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  ncvhdl -v93 "$QSYS_SIMDIR/pll2.vho"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi

Property changes on: eclaireXL/hardware/test/test_hdmi/pll2_sim/cadence/ncsim_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: eclaireXL/hardware/test/test_hdmi/pll2_sim/mentor/msim_setup.tcl
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2_sim/mentor/msim_setup.tcl	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2_sim/mentor/msim_setup.tcl	(revision 473)
@@ -0,0 +1,171 @@
+
+# (C) 2001-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 15.0 145 linux 2016.11.05.09:49:57
+
+# ----------------------------------------
+# Auto-generated simulation script
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "pll2"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/fpga/altera/15.0/quartus/"
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib          ./libraries/     
+ensure_lib          ./libraries/work/
+vmap       work     ./libraries/work/
+vmap       work_lib ./libraries/work/
+if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+  ensure_lib              ./libraries/altera/      
+  vmap       altera       ./libraries/altera/      
+  ensure_lib              ./libraries/lpm/         
+  vmap       lpm          ./libraries/lpm/         
+  ensure_lib              ./libraries/sgate/       
+  vmap       sgate        ./libraries/sgate/       
+  ensure_lib              ./libraries/altera_mf/   
+  vmap       altera_mf    ./libraries/altera_mf/   
+  ensure_lib              ./libraries/altera_lnsim/
+  vmap       altera_lnsim ./libraries/altera_lnsim/
+  ensure_lib              ./libraries/cyclonev/    
+  vmap       cyclonev     ./libraries/cyclonev/    
+}
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+    vlog -sv "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"  -work altera_lnsim
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+    vlog     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"   -work cyclonev    
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+  }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  vcom "$QSYS_SIMDIR/pll2.vho"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim -t ps $ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with novopt option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -novopt -t ps $ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -novopt
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                     -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                       -- Compile device library files"
+  echo
+  echo "com                           -- Compile the design files in correct order"
+  echo
+  echo "elab                          -- Elaborate top level design"
+  echo
+  echo "elab_debug                    -- Elaborate the top level design with novopt option"
+  echo
+  echo "ld                            -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                      -- Compile all the design files and elaborate the top level design with -novopt"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                -- Top level module name."
+  echo
+  echo "SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                   -- Qsys base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR           -- Quartus installation directory."
+}
+file_copy
+h
Index: eclaireXL/hardware/test/test_hdmi/pll2_sim/pll2.vho
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2_sim/pll2.vho	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2_sim/pll2.vho	(revision 473)
@@ -0,0 +1,309 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 15.0 cbx_mgl 2015:04:15:20:18:26:SJ cbx_simgen 2015:04:15:19:11:39:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, the Altera Quartus II License Agreement,
+-- the Altera MegaCore Function License Agreement, or other 
+-- applicable license agreement, including, without limitation, 
+-- that your use is for the sole purpose of programming logic 
+-- devices manufactured by Altera and sold by Altera or its 
+-- authorized distributors.  Please refer to the applicable 
+-- agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY altera_lnsim;
+ USE altera_lnsim.altera_lnsim_components.all;
+
+--synthesis_resources = altera_pll 1 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  pll2 IS 
+	 PORT 
+	 ( 
+		 locked	:	OUT  STD_LOGIC;
+		 outclk_0	:	OUT  STD_LOGIC;
+		 outclk_1	:	OUT  STD_LOGIC;
+		 refclk	:	IN  STD_LOGIC;
+		 rst	:	IN  STD_LOGIC
+	 ); 
+ END pll2;
+
+ ARCHITECTURE RTL OF pll2 IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+	 SIGNAL  wire_gnd	:	STD_LOGIC;
+	 SIGNAL  wire_pll2_altera_pll_altera_pll_i_1098_locked	:	STD_LOGIC;
+	 SIGNAL  wire_pll2_altera_pll_altera_pll_i_1098_outclk	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
+ BEGIN
+
+	wire_gnd <= '0';
+	locked <= wire_pll2_altera_pll_altera_pll_i_1098_locked;
+	outclk_0 <= wire_pll2_altera_pll_altera_pll_i_1098_outclk(0);
+	outclk_1 <= wire_pll2_altera_pll_altera_pll_i_1098_outclk(1);
+	pll2_altera_pll_altera_pll_i_1098 :  altera_pll
+	  GENERIC MAP (
+		c_cnt_bypass_en0 => "false",
+		c_cnt_bypass_en1 => "false",
+		c_cnt_bypass_en10 => "false",
+		c_cnt_bypass_en11 => "false",
+		c_cnt_bypass_en12 => "false",
+		c_cnt_bypass_en13 => "false",
+		c_cnt_bypass_en14 => "false",
+		c_cnt_bypass_en15 => "false",
+		c_cnt_bypass_en16 => "false",
+		c_cnt_bypass_en17 => "false",
+		c_cnt_bypass_en2 => "false",
+		c_cnt_bypass_en3 => "false",
+		c_cnt_bypass_en4 => "false",
+		c_cnt_bypass_en5 => "false",
+		c_cnt_bypass_en6 => "false",
+		c_cnt_bypass_en7 => "false",
+		c_cnt_bypass_en8 => "false",
+		c_cnt_bypass_en9 => "false",
+		c_cnt_hi_div0 => 1,
+		c_cnt_hi_div1 => 1,
+		c_cnt_hi_div10 => 1,
+		c_cnt_hi_div11 => 1,
+		c_cnt_hi_div12 => 1,
+		c_cnt_hi_div13 => 1,
+		c_cnt_hi_div14 => 1,
+		c_cnt_hi_div15 => 1,
+		c_cnt_hi_div16 => 1,
+		c_cnt_hi_div17 => 1,
+		c_cnt_hi_div2 => 1,
+		c_cnt_hi_div3 => 1,
+		c_cnt_hi_div4 => 1,
+		c_cnt_hi_div5 => 1,
+		c_cnt_hi_div6 => 1,
+		c_cnt_hi_div7 => 1,
+		c_cnt_hi_div8 => 1,
+		c_cnt_hi_div9 => 1,
+		c_cnt_in_src0 => "ph_mux_clk",
+		c_cnt_in_src1 => "ph_mux_clk",
+		c_cnt_in_src10 => "ph_mux_clk",
+		c_cnt_in_src11 => "ph_mux_clk",
+		c_cnt_in_src12 => "ph_mux_clk",
+		c_cnt_in_src13 => "ph_mux_clk",
+		c_cnt_in_src14 => "ph_mux_clk",
+		c_cnt_in_src15 => "ph_mux_clk",
+		c_cnt_in_src16 => "ph_mux_clk",
+		c_cnt_in_src17 => "ph_mux_clk",
+		c_cnt_in_src2 => "ph_mux_clk",
+		c_cnt_in_src3 => "ph_mux_clk",
+		c_cnt_in_src4 => "ph_mux_clk",
+		c_cnt_in_src5 => "ph_mux_clk",
+		c_cnt_in_src6 => "ph_mux_clk",
+		c_cnt_in_src7 => "ph_mux_clk",
+		c_cnt_in_src8 => "ph_mux_clk",
+		c_cnt_in_src9 => "ph_mux_clk",
+		c_cnt_lo_div0 => 1,
+		c_cnt_lo_div1 => 1,
+		c_cnt_lo_div10 => 1,
+		c_cnt_lo_div11 => 1,
+		c_cnt_lo_div12 => 1,
+		c_cnt_lo_div13 => 1,
+		c_cnt_lo_div14 => 1,
+		c_cnt_lo_div15 => 1,
+		c_cnt_lo_div16 => 1,
+		c_cnt_lo_div17 => 1,
+		c_cnt_lo_div2 => 1,
+		c_cnt_lo_div3 => 1,
+		c_cnt_lo_div4 => 1,
+		c_cnt_lo_div5 => 1,
+		c_cnt_lo_div6 => 1,
+		c_cnt_lo_div7 => 1,
+		c_cnt_lo_div8 => 1,
+		c_cnt_lo_div9 => 1,
+		c_cnt_odd_div_duty_en0 => "false",
+		c_cnt_odd_div_duty_en1 => "false",
+		c_cnt_odd_div_duty_en10 => "false",
+		c_cnt_odd_div_duty_en11 => "false",
+		c_cnt_odd_div_duty_en12 => "false",
+		c_cnt_odd_div_duty_en13 => "false",
+		c_cnt_odd_div_duty_en14 => "false",
+		c_cnt_odd_div_duty_en15 => "false",
+		c_cnt_odd_div_duty_en16 => "false",
+		c_cnt_odd_div_duty_en17 => "false",
+		c_cnt_odd_div_duty_en2 => "false",
+		c_cnt_odd_div_duty_en3 => "false",
+		c_cnt_odd_div_duty_en4 => "false",
+		c_cnt_odd_div_duty_en5 => "false",
+		c_cnt_odd_div_duty_en6 => "false",
+		c_cnt_odd_div_duty_en7 => "false",
+		c_cnt_odd_div_duty_en8 => "false",
+		c_cnt_odd_div_duty_en9 => "false",
+		c_cnt_ph_mux_prst0 => 0,
+		c_cnt_ph_mux_prst1 => 0,
+		c_cnt_ph_mux_prst10 => 0,
+		c_cnt_ph_mux_prst11 => 0,
+		c_cnt_ph_mux_prst12 => 0,
+		c_cnt_ph_mux_prst13 => 0,
+		c_cnt_ph_mux_prst14 => 0,
+		c_cnt_ph_mux_prst15 => 0,
+		c_cnt_ph_mux_prst16 => 0,
+		c_cnt_ph_mux_prst17 => 0,
+		c_cnt_ph_mux_prst2 => 0,
+		c_cnt_ph_mux_prst3 => 0,
+		c_cnt_ph_mux_prst4 => 0,
+		c_cnt_ph_mux_prst5 => 0,
+		c_cnt_ph_mux_prst6 => 0,
+		c_cnt_ph_mux_prst7 => 0,
+		c_cnt_ph_mux_prst8 => 0,
+		c_cnt_ph_mux_prst9 => 0,
+		c_cnt_prst0 => 1,
+		c_cnt_prst1 => 1,
+		c_cnt_prst10 => 1,
+		c_cnt_prst11 => 1,
+		c_cnt_prst12 => 1,
+		c_cnt_prst13 => 1,
+		c_cnt_prst14 => 1,
+		c_cnt_prst15 => 1,
+		c_cnt_prst16 => 1,
+		c_cnt_prst17 => 1,
+		c_cnt_prst2 => 1,
+		c_cnt_prst3 => 1,
+		c_cnt_prst4 => 1,
+		c_cnt_prst5 => 1,
+		c_cnt_prst6 => 1,
+		c_cnt_prst7 => 1,
+		c_cnt_prst8 => 1,
+		c_cnt_prst9 => 1,
+		clock_name_0 => "UNUSED",
+		clock_name_1 => "UNUSED",
+		clock_name_2 => "UNUSED",
+		clock_name_3 => "UNUSED",
+		clock_name_4 => "UNUSED",
+		clock_name_5 => "UNUSED",
+		clock_name_6 => "UNUSED",
+		clock_name_7 => "UNUSED",
+		clock_name_8 => "UNUSED",
+		clock_name_global_0 => "false",
+		clock_name_global_1 => "false",
+		clock_name_global_2 => "false",
+		clock_name_global_3 => "false",
+		clock_name_global_4 => "false",
+		clock_name_global_5 => "false",
+		clock_name_global_6 => "false",
+		clock_name_global_7 => "false",
+		clock_name_global_8 => "false",
+		data_rate => 0,
+		deserialization_factor => 4,
+		duty_cycle0 => 50,
+		duty_cycle1 => 50,
+		duty_cycle10 => 50,
+		duty_cycle11 => 50,
+		duty_cycle12 => 50,
+		duty_cycle13 => 50,
+		duty_cycle14 => 50,
+		duty_cycle15 => 50,
+		duty_cycle16 => 50,
+		duty_cycle17 => 50,
+		duty_cycle2 => 50,
+		duty_cycle3 => 50,
+		duty_cycle4 => 50,
+		duty_cycle5 => 50,
+		duty_cycle6 => 50,
+		duty_cycle7 => 50,
+		duty_cycle8 => 50,
+		duty_cycle9 => 50,
+		fractional_vco_multiplier => "false",
+		m_cnt_bypass_en => "false",
+		m_cnt_hi_div => 1,
+		m_cnt_lo_div => 1,
+		m_cnt_odd_div_duty_en => "false",
+		mimic_fbclk_type => "gclk",
+		n_cnt_bypass_en => "false",
+		n_cnt_hi_div => 1,
+		n_cnt_lo_div => 1,
+		n_cnt_odd_div_duty_en => "false",
+		number_of_clocks => 2,
+		operation_mode => "normal",
+		output_clock_frequency0 => "135.000000 MHz",
+		output_clock_frequency1 => "27.000000 MHz",
+		output_clock_frequency10 => "0 MHz",
+		output_clock_frequency11 => "0 MHz",
+		output_clock_frequency12 => "0 MHz",
+		output_clock_frequency13 => "0 MHz",
+		output_clock_frequency14 => "0 MHz",
+		output_clock_frequency15 => "0 MHz",
+		output_clock_frequency16 => "0 MHz",
+		output_clock_frequency17 => "0 MHz",
+		output_clock_frequency2 => "0 MHz",
+		output_clock_frequency3 => "0 MHz",
+		output_clock_frequency4 => "0 MHz",
+		output_clock_frequency5 => "0 MHz",
+		output_clock_frequency6 => "0 MHz",
+		output_clock_frequency7 => "0 MHz",
+		output_clock_frequency8 => "0 MHz",
+		output_clock_frequency9 => "0 MHz",
+		phase_shift0 => "0 ps",
+		phase_shift1 => "0 ps",
+		phase_shift10 => "0 ps",
+		phase_shift11 => "0 ps",
+		phase_shift12 => "0 ps",
+		phase_shift13 => "0 ps",
+		phase_shift14 => "0 ps",
+		phase_shift15 => "0 ps",
+		phase_shift16 => "0 ps",
+		phase_shift17 => "0 ps",
+		phase_shift2 => "0 ps",
+		phase_shift3 => "0 ps",
+		phase_shift4 => "0 ps",
+		phase_shift5 => "0 ps",
+		phase_shift6 => "0 ps",
+		phase_shift7 => "0 ps",
+		phase_shift8 => "0 ps",
+		phase_shift9 => "0 ps",
+		pll_auto_clk_sw_en => "false",
+		pll_bw_sel => "low",
+		pll_bwctrl => 0,
+		pll_clk_loss_sw_en => "false",
+		pll_clk_sw_dly => 0,
+		pll_clkin_0_src => "clk_0",
+		pll_clkin_1_src => "clk_0",
+		pll_cp_current => 0,
+		pll_dsm_out_sel => "1st_order",
+		pll_extclk_0_cnt_src => "pll_extclk_cnt_src_vss",
+		pll_extclk_1_cnt_src => "pll_extclk_cnt_src_vss",
+		pll_fbclk_mux_1 => "glb",
+		pll_fbclk_mux_2 => "fb_1",
+		pll_fractional_cout => 24,
+		pll_fractional_division => 1,
+		pll_m_cnt_in_src => "ph_mux_clk",
+		pll_manu_clk_sw_en => "false",
+		pll_output_clk_frequency => "0 MHz",
+		pll_slf_rst => "false",
+		pll_subtype => "General",
+		pll_type => "General",
+		pll_vco_div => 1,
+		pll_vcoph_div => 1,
+		refclk1_frequency => "0 MHz",
+		reference_clock_frequency => "5.0 MHz",
+		sim_additional_refclk_cycles_to_lock => 0
+	  )
+	  PORT MAP ( 
+		fbclk => wire_gnd,
+		locked => wire_pll2_altera_pll_altera_pll_i_1098_locked,
+		outclk => wire_pll2_altera_pll_altera_pll_i_1098_outclk,
+		refclk => refclk,
+		rst => rst
+	  );
+
+ END RTL; --pll2
+--synopsys translate_on
+--VALID FILE
Index: eclaireXL/hardware/test/test_hdmi/pll2_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- eclaireXL/hardware/test/test_hdmi/pll2_sim/synopsys/vcsmx/vcsmx_setup.sh	(nonexistent)
+++ eclaireXL/hardware/test/test_hdmi/pll2_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 473)
@@ -0,0 +1,107 @@
+
+# (C) 2001-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 15.0 145 linux 2016.11.05.09:49:57
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="pll2"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/home/markw/fpga/altera/15.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/cyclonev/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlogan +v2k -sverilog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlogan +v2k           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev    
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  vhdlan -xlrm "$QSYS_SIMDIR/pll2.vho"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

Property changes on: eclaireXL/hardware/test/test_hdmi/pll2_sim/synopsys/vcsmx/vcsmx_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
