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---------------------------------------------------------------------------
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-- (c) 2013,2015 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY sram IS
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PORT
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(
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ADDRESS : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
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DIN : IN STD_LOGIC_vector(31 downto 0);
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WREN : IN STD_LOGIC;
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clk : in std_logic;
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reset_n : in std_logic;
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request : in std_logic;
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width32bit : in std_logic; -- 32-bit read/write
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-- SRAM interface
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SRAM_ADDR: OUT STD_LOGIC_VECTOR(20 downto 0);
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SRAM_CE_N: OUT STD_LOGIC;
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SRAM_OE_N: OUT STD_LOGIC;
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SRAM_WE_N: OUT STD_LOGIC;
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SRAM_DQ: INOUT STD_LOGIC_VECTOR(7 downto 0);
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-- Provide data to system
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DOUT : OUT STD_LOGIC_VECTOR(31 downto 0);
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complete : out std_logic
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);
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END sram;
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-- first cycle, capture inputs
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-- second cycle, sram access
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ARCHITECTURE slow OF sram IS
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signal oe_n_next : std_logic;
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signal oe_n_reg : std_logic;
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signal we_n_next : std_logic;
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signal we_n_reg : std_logic;
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signal address_next : std_logic_vector(20 downto 0);
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signal address_reg : std_logic_vector(20 downto 0);
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signal data_write_next : std_logic_vector(31 downto 0);
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signal data_write_reg : std_logic_vector(31 downto 0);
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signal data_read_next : std_logic_vector(31 downto 0);
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signal data_read_reg : std_logic_vector(31 downto 0);
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signal complete_next : std_logic;
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signal complete_reg : std_logic;
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constant state_idle : std_logic_vector(3 downto 0) := "0000";
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constant state_read_byte1 : std_logic_vector(3 downto 0) := "0001";
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constant state_read_byte2 : std_logic_vector(3 downto 0) := "0010";
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constant state_read_byte3 : std_logic_vector(3 downto 0) := "0011";
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constant state_read_byte4 : std_logic_vector(3 downto 0) := "0100";
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constant state_write_byte1a : std_logic_vector(3 downto 0) := "0101";
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constant state_write_byte1b : std_logic_vector(3 downto 0) := "0110";
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constant state_write_byte2a : std_logic_vector(3 downto 0) := "0111";
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constant state_write_byte2b : std_logic_vector(3 downto 0) := "1000";
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constant state_write_byte3a : std_logic_vector(3 downto 0) := "1001";
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constant state_write_byte3b : std_logic_vector(3 downto 0) := "1010";
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constant state_write_byte4a : std_logic_vector(3 downto 0) := "1011";
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constant state_read_byte4b : std_logic_vector(3 downto 0) := "1101";
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signal state_next : std_logic_vector(3 downto 0);
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signal state_reg : std_logic_vector(3 downto 0);
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BEGIN
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-- registers
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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oe_n_reg <= '1';
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we_n_reg <= '1';
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data_write_reg <= (others=>'0');
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data_read_reg <= (others=>'0');
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complete_reg <= '0';
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state_reg <= state_idle;
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address_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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oe_n_reg <= oe_n_next;
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we_n_reg <= we_n_next;
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data_write_reg <= data_write_next;
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data_read_reg <= data_read_next;
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complete_reg <= complete_next;
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state_reg <= state_next;
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address_reg <= address_next;
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end if;
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end process;
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-- next state
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process(din,wren,request,state_reg,width32bit,sram_dq,data_read_reg,data_write_reg,address_reg,address)
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begin
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state_next <= state_reg;
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data_write_next <= data_write_reg;
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data_read_next <= data_read_reg;
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complete_next <= '0';
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oe_n_next <= '0';
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we_n_next <= '1';
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address_next <= address_reg;
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-- on second cycle do write - address/data stable by now guaranteed (normal timequest...)
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case state_reg is
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when state_idle =>
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if (request = '1') then
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data_write_next <= din;
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address_next <= address;
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if (width32bit = '1') then
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if (wren = '1') then
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address_next(1 downto 0) <= "00";
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state_next <= state_write_byte1a;
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else
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address_next(1 downto 0) <= "11";
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state_next <= state_read_byte1;
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end if;
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else
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if (wren = '1') then
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state_next <= state_write_byte4a;
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else
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state_next <= state_read_byte4;
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end if;
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end if;
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end if;
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when state_read_byte1 =>
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address_next(1 downto 0) <= "10";
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data_read_next(31 downto 24) <= SRAM_DQ;
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state_next <= state_read_byte2;
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when state_read_byte2 =>
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address_next(1 downto 0) <= "01";
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data_read_next(23 downto 16) <= SRAM_DQ;
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state_next <= state_read_byte3;
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when state_read_byte3 =>
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address_next(1 downto 0) <= "00";
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data_read_next(15 downto 8) <= SRAM_DQ;
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state_next <= state_read_byte4;
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when state_read_byte4 =>
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data_read_next(7 downto 0) <= SRAM_DQ;
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state_next <= state_idle;
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complete_next <= '1';
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when state_write_byte1a =>
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state_next <= state_write_byte1b;
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we_n_next <= '0';
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oe_n_next <= '1';
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when state_write_byte1b =>
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address_next(1 downto 0) <= "01";
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data_write_next(23 downto 0) <= data_write_reg(31 downto 8);
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state_next <= state_write_byte2a;
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we_n_next <= '1';
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oe_n_next <= '1';
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when state_write_byte2a =>
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state_next <= state_write_byte2b;
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we_n_next <= '0';
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oe_n_next <= '1';
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when state_write_byte2b =>
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address_next(1 downto 0) <= "10";
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data_write_next(23 downto 0) <= data_write_reg(31 downto 8);
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state_next <= state_write_byte3a;
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we_n_next <= '1';
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oe_n_next <= '1';
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when state_write_byte3a =>
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state_next <= state_write_byte3b;
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we_n_next <= '0';
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oe_n_next <= '1';
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when state_write_byte3b =>
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address_next(1 downto 0) <= "11";
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data_write_next(23 downto 0) <= data_write_reg(31 downto 8);
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state_next <= state_write_byte4a;
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we_n_next <= '1';
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oe_n_next <= '1';
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when state_write_byte4a =>
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we_n_next <= '0';
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oe_n_next <= '1';
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complete_next <= '1';
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state_next <= state_idle;
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when others =>
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state_next <= state_idle;
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end case;
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end process;
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-- output
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SRAM_CE_N <= '0';
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SRAM_OE_N <= oe_n_reg;
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SRAM_WE_N <= we_n_reg;
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SRAM_DQ <= data_write_reg(7 downto 0) when we_n_reg = '0' else (others=>'Z');
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SRAM_ADDR <= address_reg;
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DOUT <= data_read_next;
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complete <= complete_reg;
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--GPIO <= (others=>'0');
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END slow;
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