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---------------------------------------------------------------------------
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-- (c) 2015 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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LIBRARY work;
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-- Return to the spi boot core
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-- Could also be the basis of a boot menu...
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ENTITY delayed_reconfig IS
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PORT
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(
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CLK_5MHZ : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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RECONFIG_BUTTON : IN STD_LOGIC
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);
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END delayed_reconfig;
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ARCHITECTURE altera OF delayed_reconfig IS
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-- return to menu
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signal reconfig_trigger : std_logic;
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signal reconfig_delayed : std_logic;
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signal reconfig_count_next : std_logic_vector(24 downto 0);
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signal reconfig_count_reg : std_logic_vector(24 downto 0);
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BEGIN
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-- Return to the boot menu
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remote: entity work.remote_update_rmtupdt_51n
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PORT MAP
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(
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busy => open,
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clock => CLK_5MHZ,
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data_in => (others=>'0'),
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data_out => open,
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param => (others=>'0'),
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reconfig => reconfig_delayed,
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reset => not(reset_n),
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write_param => '0'
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);
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reboot_synchronizer : entity work.synchronizer
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port map (clk=>CLK_5MHZ, raw=>reconfig_button, sync=>reconfig_trigger);
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process(CLK_5MHZ,reset_n)
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begin
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if (reset_n='0') then
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reconfig_count_reg <= (others=>'1');
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elsif (CLK_5MHZ'event and CLK_5MHZ = '1') then
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reconfig_count_reg <= reconfig_count_next;
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end if;
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end process;
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process(reconfig_count_reg,reconfig_trigger)
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begin
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reconfig_count_next <= std_logic_vector(unsigned(reconfig_count_reg)-1);
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if (reconfig_trigger = '0') then
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reconfig_count_next <= "1011111010111100001000000";
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end if;
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reconfig_delayed <= not(or_reduce(reconfig_count_reg));
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end process;
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-- write to param 4 -> 0x00050000 (NOT REQUIRED)
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-- write to param 3 -> 0 (MAYBE? WORKS WITHOUT, BUT WILL I GET SPURIOUS REBOOTS?)
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-- raise reconfig high (YIPPEE!)
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END altera;
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