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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY zpu_config_regs IS
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GENERIC
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(
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platform : integer := 1; -- So ROM can detect which type of system...
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spi_clock_div : integer := 4; -- Quite conservative by default - probably want to use 1 with 28MHz input clock, 2 for 57MHz input clock, 4 for 114MHz input clock etc
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usb : integer :=0 -- USB host slave instances
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);
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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POKEY_ENABLE : in std_logic;
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ADDR : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
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CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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RD_EN : IN STD_LOGIC;
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WR_EN : IN STD_LOGIC;
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-- GENERIC INPUT REGS (need to synchronize upstream...)
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IN1 : in std_logic_vector(31 downto 0);
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IN2 : in std_logic_vector(31 downto 0);
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IN3 : in std_logic_vector(31 downto 0);
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IN4 : in std_logic_vector(31 downto 0);
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-- GENERIC OUTPUT REGS
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OUT1 : out std_logic_vector(31 downto 0);
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OUT2 : out std_logic_vector(31 downto 0);
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OUT3 : out std_logic_vector(31 downto 0);
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OUT4 : out std_logic_vector(31 downto 0);
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OUT5 : out std_logic_vector(31 downto 0);
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OUT6 : out std_logic_vector(31 downto 0);
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-- SDCARD
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SDCARD_CLK : out std_logic;
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SDCARD_CMD : out std_logic;
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SDCARD_DAT : in std_logic;
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SDCARD_DAT3 : out std_logic;
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-- SD DMA
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sd_addr : out std_logic_vector(15 downto 0);
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sd_data : out std_logic_vector(7 downto 0);
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sd_write : out std_logic;
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-- ATARI interface (in future we can also turbo load by directly hitting memory...)
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SIO_DATA_IN : out std_logic;
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SIO_COMMAND : in std_logic;
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SIO_DATA_OUT : in std_logic;
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-- CPU interface
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DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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PAUSE_ZPU : out std_logic;
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-- USB host
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CLK_USB : in std_logic;
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USBWireVPin :in std_logic_vector(usb-1 downto 0);
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USBWireVMin :in std_logic_vector(usb-1 downto 0);
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USBWireVPout :out std_logic_vector(usb-1 downto 0);
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USBWireVMout :out std_logic_vector(usb-1 downto 0);
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USBWireOE_n :out std_logic_vector(usb-1 downto 0)
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);
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END zpu_config_regs;
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ARCHITECTURE vhdl OF zpu_config_regs IS
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component usbHostCyc2Wrap_usb1t11
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port (
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clk_i :in std_logic;
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rst_i :in std_logic;
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address_i : in std_logic_vector(7 downto 0);
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data_i : in std_logic_vector(7 downto 0);
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data_o : out std_logic_vector(7 downto 0);
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we_i :in std_logic;
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strobe_i :in std_logic;
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ack_o :out std_logic;
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irq :out std_logic;
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usbClk :in std_logic;
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USBWireVPin :in std_logic;
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USBWireVMin :in std_logic;
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USBWireVPout :out std_logic;
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USBWireVMout :out std_logic;
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USBWireOE_n :out std_logic;
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USBFullSpeed :out std_logic
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);
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end component;
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function vectorize(s: std_logic) return std_logic_vector is
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variable v: std_logic_vector(0 downto 0);
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begin
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v(0) := s;
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return v;
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end;
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signal device_decoded : std_logic_vector(7 downto 0);
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signal device_wr_en : std_logic_vector(7 downto 0);
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signal device_rd_en : std_logic_vector(7 downto 0);
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signal addr_decoded : std_logic_vector(15 downto 0);
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signal out1_next : std_logic_vector(31 downto 0);
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signal out1_reg : std_logic_vector(31 downto 0);
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signal out2_next : std_logic_vector(31 downto 0);
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signal out2_reg : std_logic_vector(31 downto 0);
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signal out3_next : std_logic_vector(31 downto 0);
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signal out3_reg : std_logic_vector(31 downto 0);
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signal out4_next : std_logic_vector(31 downto 0);
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signal out4_reg : std_logic_vector(31 downto 0);
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signal out5_next : std_logic_vector(31 downto 0);
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signal out5_reg : std_logic_vector(31 downto 0);
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signal out6_next : std_logic_vector(31 downto 0);
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signal out6_reg : std_logic_vector(31 downto 0);
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signal spi_miso : std_logic;
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signal spi_mosi : std_logic;
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signal spi_busy : std_logic;
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signal spi_enable : std_logic;
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signal spi_chip_select : std_logic_vector(0 downto 0);
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signal spi_clk_out : std_logic;
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signal spi_tx_data : std_logic_vector(7 downto 0);
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signal spi_rx_data : std_logic_vector(7 downto 0);
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signal spi_addr_next : std_logic;
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signal spi_addr_reg : std_logic;
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signal spi_addr_reg_integer : integer;
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signal spi_speed_next : std_logic_vector(7 downto 0);
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signal spi_speed_reg : std_logic_vector(7 downto 0);
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signal spi_speed_reg_integer : integer;
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signal pokey_data_out : std_logic_vector(7 downto 0);
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signal pause_next : std_logic_vector(31 downto 0);
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signal pause_reg : std_logic_vector(31 downto 0);
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signal paused_next : std_logic;
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signal paused_reg : std_logic;
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signal subtimer_next : std_logic_vector(10 downto 0);
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signal subtimer_reg : std_logic_vector(10 downto 0);
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signal timer_next : std_logic_vector(31 downto 0);
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signal timer_reg : std_logic_vector(31 downto 0);
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signal spi_dma_addr_next : std_logic_vector(15 downto 0);
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signal spi_dma_addrend_next : std_logic_vector(15 downto 0);
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signal spi_dma_wr : std_logic;
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signal spi_dma_next : std_logic;
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signal spi_dma_addr_reg : std_logic_vector(15 downto 0);
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signal spi_dma_addrend_reg : std_logic_vector(15 downto 0);
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signal spi_dma_reg : std_logic;
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signal spi_clk_div_integer : integer;
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signal spi_addr_integer : integer;
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subtype usb_data_type is std_logic_vector(7 downto 0);
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type usb_data_array is array(0 to USB-1) of usb_data_type;
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signal usb_data : usb_data_array;
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signal data_out_regs : std_logic_vector(31 downto 0);
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signal data_out_mux : std_logic_vector(31 downto 0);
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begin
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-- register
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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out1_reg <= (others=>'0');
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out2_reg <= (others=>'0');
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out3_reg <= (others=>'0');
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out4_reg <= (others=>'0');
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out5_reg <= (others=>'0');
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out6_reg <= (others=>'0');
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spi_addr_reg <= '1';
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spi_speed_reg <= X"80";
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pause_reg <= (others=>'0');
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paused_reg <= '0';
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subtimer_reg <= (others=>'0');
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timer_reg <= (others=>'0');
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spi_dma_addr_reg <= (others=>'0');
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spi_dma_addrend_reg <= (others=>'0');
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spi_dma_reg <= '0';
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elsif (clk'event and clk='1') then
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out1_reg <= out1_next;
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out2_reg <= out2_next;
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out3_reg <= out3_next;
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out4_reg <= out4_next;
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out5_reg <= out5_next;
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out6_reg <= out6_next;
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spi_addr_reg <= spi_addr_next;
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spi_speed_reg <= spi_speed_next;
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pause_reg <= pause_next;
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paused_reg <= paused_next;
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subtimer_reg <= subtimer_next;
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timer_reg <= timer_next;
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spi_dma_addr_reg <= spi_dma_addr_next;
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spi_dma_addrend_reg <= spi_dma_addrend_next;
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spi_dma_reg <= spi_dma_next;
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end if;
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end process;
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-- decode address
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decode_addr : entity work.complete_address_decoder
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generic map(width=>4)
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port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
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decode_device : entity work.complete_address_decoder
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generic map(width=>3)
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port map (addr_in=>addr(10 downto 8), addr_decoded=>device_decoded);
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-- spi - for sd card access without bit banging...
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-- 200KHz to start with - probably fine for 8-bit, can up it later after init
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spi_clk_div_integer <= to_integer(unsigned(spi_speed_reg));
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spi_addr_integer <= to_integer(unsigned(vectorize(spi_addr_reg)));
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spi_master1 : entity work.spi_master
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generic map(slaves=>1,d_width=>8)
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port map (clock=>clk,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>spi_clk_div_integer,addr=>spi_addr_integer,
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tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
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rx_data=>spi_rx_data,busy=>spi_busy);
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-- spi-programming model:
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-- reg for write/read
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-- data (send/receive)
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-- busy
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-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
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-- chip select
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-- device decode
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-- 0x000 - own regs (0)
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-- 0x100 - pokey (1)
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-- 0x200 - usb1 (2)
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-- 0x300 - usb2 (3)
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-- 0x400 - usb3 (4)
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-- 0x500 - usb4 (5)
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-- 0x600 - usb5 (6)
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-- 0x700 - usb6 (7)
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device_wr_en <= device_decoded and (wr_en&wr_en&wr_en&wr_en&wr_en&wr_en&wr_en&wr_en);
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device_rd_en <= device_decoded and (rd_en&rd_en&rd_en&rd_en&rd_en&rd_en&rd_en&rd_en);
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-- uart - another Pokey! Running at atari frequency.
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-- with a state machine to capture command packets
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-- can not easily poll frequently enough with zpu when also polling usb
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-- pokey1 : entity work.pokey
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-- port map (clk=>clk,ENABLE_179=>pokey_enable,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>device_wr_en(1),
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-- reset_n=>reset_n,keyboard_response=>"11",pot_in=>X"00",
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-- sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
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-- data_out=>pokey_data_out,
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-- sio_out1=>sio_data_in);
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pokey1 : entity work.sio_device
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PORT MAP
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(
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CLK => CLK,
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ADDR => addr(4 downto 0),
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CPU_DATA_IN => cpu_data_in(7 downto 0),
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EN => device_rd_en(1),
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WR_EN => device_wr_en(1),
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RESET_N => reset_n,
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POKEY_ENABLE => pokey_enable,
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SIO_DATA_IN => sio_data_in,
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SIO_COMMAND => sio_command,
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SIO_DATA_OUT => sio_data_out,
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-- CPU interface
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DATA_OUT => pokey_data_out
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);
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-- timer for approx ms
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process(timer_reg,subtimer_reg, pokey_enable)
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begin
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timer_next <= timer_reg;
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subtimer_next <= subtimer_reg;
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if (pokey_enable = '1') then
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subtimer_next <= std_logic_vector(unsigned(subtimer_reg)-1);
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end if;
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if (subtimer_reg = "000"&x"00") then
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subtimer_next <= std_logic_vector(to_unsigned(11#1790#,11));
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timer_next <= std_logic_vector(unsigned(timer_reg)+1);
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end if;
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end process;
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-- USB host
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USBGEN:
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for I in 0 to USB-1 generate
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usbcon : usbHostCyc2Wrap_usb1t11
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port map
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(
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clk_i => clk,
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rst_i => not(reset_n),
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address_i => addr(7 downto 0),
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data_i => cpu_data_in(7 downto 0),
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data_o => usb_data(I), -- 2D array
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we_i => device_wr_en(I+2),
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strobe_i => device_wr_en(I+2) or device_rd_en(I+2),
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ack_o => open, -- always right away - checked in sim
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irq => open,
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usbClk => CLK_USB,
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USBWireVPin => USBWireVPin(I),
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USBWireVMin => USBWireVMin(I),
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USBWireVPout => USBWireVPout(I),
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USBWireVMout => USBWireVMout(I),
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USBWireOE_n => USBWireOE_n(I),
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USBFullSpeed => open
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);
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end generate USBGEN;
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process(device_decoded, data_out_regs, pokey_data_out, usb_data)
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begin
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data_out_mux <= (others=>'0');
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if (device_decoded(0) = '1') then
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data_out_mux <= data_out_regs;
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end if;
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if (device_decoded(1) = '1') then
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data_out_mux(7 downto 0) <= pokey_data_out;
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end if;
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for I in 0 to USB-1 loop
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if (device_decoded(I+2) = '1') then
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data_out_mux(7 downto 0) <= usb_data(I);
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end if;
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end loop;
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end process;
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-- hardware regs for ZPU
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--
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-- 0-3: GENERIC INPUT (RO)
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-- 4-7: GENERIC OUTPUT (R/W)
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-- 8: W:PAUSE, R:Timer (1ms)
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-- 9: SPI_DATA
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-- SPI_DATA (DONE)
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-- W - write data (starts transmission)
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-- R - read data (wait for complete first)
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-- 10: SPI_STATE
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-- SPI_STATE/SPI_CTRL (DONE)
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-- R: 0=busy
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-- W: 0=select_n, speed
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-- 11: SIO
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-- SIO
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-- R: 0=CMD
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-- 12: TYPE
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-- FPGA board (DONE)
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-- R(32 bits) 0=DE1
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-- 13 : SPI_DMA
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-- W(15 downto 0 = addr),(31 downto 16 = endAddr)
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-- 14-15 : GENERIC OUTPUT (R/W)
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-- 16-31: POKEY! Low bytes only... i.e. pokey reg every 4 bytes...
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-- Writes to registers
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process(cpu_data_in,device_wr_en,addr,addr_decoded, spi_speed_reg, spi_addr_reg, out1_reg, out2_reg, out3_reg, out4_reg, out5_reg, out6_reg, pause_reg, pokey_enable, spi_dma_addr_reg, spi_dma_addrend_reg, spi_dma_reg, spi_busy, spi_dma_addr_next)
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begin
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spi_speed_next <= spi_speed_reg;
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spi_addr_next <= spi_addr_reg;
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spi_tx_data <= (others=>'0');
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spi_enable <= '0';
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out1_next <= out1_reg;
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out2_next <= out2_reg;
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out3_next <= out3_reg;
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out4_next <= out4_reg;
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out5_next <= out5_reg;
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out6_next <= out6_reg;
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paused_next <= '0';
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pause_next <= pause_reg;
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if (not(pause_reg = X"00000000")) then
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if (POKEY_ENABLE='1') then
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pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
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end if;
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paused_next <= '1';
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end if;
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spi_dma_addr_next <= spi_dma_addr_reg;
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spi_dma_addrend_next <= spi_dma_addrend_reg;
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spi_dma_wr <= '0';
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spi_dma_next <= spi_dma_reg;
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if (spi_dma_reg = '1') then
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paused_next <= '1';
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if (spi_busy = '0') then
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spi_dma_wr <= '1';
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spi_dma_addr_next <= std_logic_vector(unsigned(spi_dma_addr_reg)+to_unsigned(1,16));
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spi_dma_next <= '0';
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if (not(spi_dma_addr_next = spi_dma_addrend_reg)) then
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spi_tx_data <= X"ff";
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spi_enable <= '1';
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spi_dma_next <= '1';
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end if;
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end if;
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end if;
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if (device_wr_en(0) = '1') then
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if(addr_decoded(4) = '1') then
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out1_next <= cpu_data_in;
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end if;
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if(addr_decoded(5) = '1') then
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out2_next <= cpu_data_in;
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end if;
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if(addr_decoded(6) = '1') then
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out3_next <= cpu_data_in;
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end if;
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if(addr_decoded(7) = '1') then
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out4_next <= cpu_data_in;
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end if;
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if(addr_decoded(14) = '1') then
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out5_next <= cpu_data_in;
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end if;
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if(addr_decoded(15) = '1') then
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out6_next <= cpu_data_in;
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end if;
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if(addr_decoded(8) = '1') then
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pause_next <= cpu_data_in;
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paused_next <= '1';
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end if;
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if(addr_decoded(9) = '1') then
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-- TODO, check overrun?
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spi_tx_data <= cpu_data_in(7 downto 0);
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spi_enable <= '1';
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end if;
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if(addr_decoded(10) = '1') then
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spi_addr_next <= cpu_data_in(0);
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if (cpu_data_in(1) = '1') then
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spi_speed_next <= X"80"; -- slow, for init
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else
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spi_speed_next <= std_logic_vector(to_unsigned(spi_clock_div,8)); -- turbo - up to 25MHz for SD, 20MHz for MMC I believe... If 1 then clock is half input, if 2 then clock is 1/4 input etc.
|
|
end if;
|
|
end if;
|
|
|
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if(addr_decoded(13) = '1') then
|
|
paused_next <= '1';
|
|
spi_dma_addr_next <= cpu_data_in(15 downto 0);
|
|
spi_dma_addrend_next <= cpu_data_in(31 downto 16);
|
|
|
|
spi_dma_next <= '1';
|
|
|
|
spi_tx_data <= X"ff";
|
|
spi_enable <= '1';
|
|
end if;
|
|
|
|
end if;
|
|
end process;
|
|
|
|
-- Read from registers
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process(addr,addr_decoded, in1, in2, in3, in4, out1_reg, out2_reg, out3_reg, out4_reg, out5_reg, out6_reg, SIO_COMMAND, spi_rx_data, spi_busy, timer_reg)
|
|
begin
|
|
data_out_regs <= (others=>'0');
|
|
|
|
if (addr_decoded(0) = '1') then
|
|
data_out_regs <= in1;
|
|
end if;
|
|
|
|
if (addr_decoded(1) = '1') then
|
|
data_out_regs <= in2;
|
|
end if;
|
|
|
|
if (addr_decoded(2) = '1') then
|
|
data_out_regs <= in3;
|
|
end if;
|
|
|
|
if (addr_decoded(3) = '1') then
|
|
data_out_regs <= in4;
|
|
end if;
|
|
|
|
if (addr_decoded(4) = '1') then
|
|
data_out_regs <= out1_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(5) = '1') then
|
|
data_out_regs <= out2_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(6) = '1') then
|
|
data_out_regs <= out3_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(7) = '1') then
|
|
data_out_regs <= out4_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(14) = '1') then
|
|
data_out_regs <= out5_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(15) = '1') then
|
|
data_out_regs <= out6_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(8) = '1') then
|
|
data_out_regs <= timer_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(9) = '1') then
|
|
data_out_regs(7 downto 0) <= spi_rx_data;
|
|
end if;
|
|
|
|
if (addr_decoded(10) = '1') then
|
|
data_out_regs(0) <= spi_busy;
|
|
end if;
|
|
|
|
if(addr_decoded(11) = '1') then
|
|
data_out_regs(0) <= SIO_COMMAND;
|
|
end if;
|
|
|
|
if (addr_decoded(12) = '1') then
|
|
data_out_regs <= std_logic_vector(to_unsigned(platform,32));
|
|
end if;
|
|
end process;
|
|
|
|
-- outputs
|
|
PAUSE_ZPU <= paused_reg;
|
|
|
|
out1 <= out1_reg;
|
|
out2 <= out2_reg;
|
|
out3 <= out3_reg;
|
|
out4 <= out4_reg;
|
|
out5 <= out5_reg;
|
|
out6 <= out6_reg;
|
|
|
|
SDCARD_CLK <= spi_clk_out;
|
|
SDCARD_CMD <= spi_mosi;
|
|
spi_miso <= SDCARD_DAT; -- INPUT!! XXX
|
|
SDCARD_DAT3 <= spi_chip_select(0);
|
|
|
|
data_out <= data_out_mux;
|
|
|
|
sd_addr <= spi_dma_addr_reg;
|
|
sd_data <= spi_rx_data;
|
|
sd_write <= spi_dma_wr;
|
|
end vhdl;
|
|
|
|
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