EclaireXL

//////////////////////////////////////////////////////////////////////

//// ////

//// RxFifo.v ////

//// ////

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//> ////

//// ////

//// Module Description: ////

//// parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536

//// fifo read access via bus interface, fifo write access is direct

////

//// ////

//// To Do: ////

////

//// ////

//// Author(s): ////

//// - Steve Fielding, sfielding@base2designs.com ////

//// ////

//////////////////////////////////////////////////////////////////////

//// ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////

//// ////

//// This source file may be used and distributed without ////

//// restriction provided that this copyright statement is not ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer. ////

//// ////

//// This source file is free software; you can redistribute it ////

//// and/or modify it under the terms of the GNU Lesser General ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any ////

//// later version. ////

//// ////

//// This source is distributed in the hope that it will be ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

//// PURPOSE. See the GNU Lesser General Public License for more ////

//// details. ////

//// ////

//// You should have received a copy of the GNU Lesser General ////

//// Public License along with this source; if not, download it ////

//// from <http://www.opencores.org/lgpl.shtml> ////

//// ////

//////////////////////////////////////////////////////////////////////

//

// $Id: RxFifo.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`timescale 1ns / 1ps

module RxFifo(

clk,

rst,

fifoWEn,

fifoFull,

busAddress,

busWriteEn,

busStrobe_i,

busFifoSelect,

busDataIn,

busDataOut,

fifoDataIn );

//FIFO_DEPTH = ADDR_WIDTH^2

parameter FIFO_DEPTH = 64;

parameter ADDR_WIDTH = 6;

input clk;

input rst;

input fifoWEn;

output fifoFull;

input [2:0] busAddress;

input busWriteEn;

input busStrobe_i;

input busFifoSelect;

input [7:0] busDataIn;

output [7:0] busDataOut;

input [7:0] fifoDataIn;

wire clk;

wire rst;

wire fifoWEn;

wire fifoFull;

wire [2:0] busAddress;

wire busWriteEn;

wire busStrobe_i;

wire busFifoSelect;

wire [7:0] busDataIn;

wire [7:0] busDataOut;

wire [7:0] fifoDataIn;

//internal wires and regs

wire [7:0] dataFromFifoToBus;

wire fifoREn;

wire forceEmpty;

wire [15:0] numElementsInFifo;

wire fifoEmpty;

fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(

.clk(clk),

.rst(rst),

.dataIn(fifoDataIn),

.dataOut(dataFromFifoToBus),

.fifoWEn(fifoWEn),

.fifoREn(fifoREn),

.fifoFull(fifoFull),

.fifoEmpty(fifoEmpty),

.forceEmpty(forceEmpty),

.numElementsInFifo(numElementsInFifo) );

RxfifoBI u_RxfifoBI(

.address(busAddress),

.writeEn(busWriteEn),

.strobe_i(busStrobe_i),

.clk(clk),

.rst(rst),

.fifoSelect(busFifoSelect),

.fifoDataIn(dataFromFifoToBus),

.busDataIn(busDataIn),

.busDataOut(busDataOut),

.fifoREn(fifoREn),

.fifoEmpty(fifoEmpty),

.forceEmpty(forceEmpty),

.numElementsInFifo(numElementsInFifo)

);

endmodule

//////////////////////////////////////////////////////////////////////

//// ////

//// RxfifoBI.v ////

//// ////

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//> ////

//// ////

//// Module Description: ////

////

//// ////

//// To Do: ////

////

//// ////

//// Author(s): ////

//// - Steve Fielding, sfielding@base2designs.com ////

//// ////

//////////////////////////////////////////////////////////////////////

//// ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////

//// ////

//// This source file may be used and distributed without ////

//// restriction provided that this copyright statement is not ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer. ////

//// ////

//// This source file is free software; you can redistribute it ////

//// and/or modify it under the terms of the GNU Lesser General ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any ////

//// later version. ////

//// ////

//// This source is distributed in the hope that it will be ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

//// PURPOSE. See the GNU Lesser General Public License for more ////

//// details. ////

//// ////

//// You should have received a copy of the GNU Lesser General ////

//// Public License along with this source; if not, download it ////

//// from <http://www.opencores.org/lgpl.shtml> ////

//// ////

//////////////////////////////////////////////////////////////////////

//

// $Id: RxFifoBI.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`include "wishBoneBus_h.v"

module RxfifoBI (

address,

writeEn,

strobe_i,

clk,

rst,

fifoSelect,

fifoDataIn,

busDataIn,

busDataOut,

fifoREn,

fifoEmpty,

forceEmpty,

numElementsInFifo

);

input [2:0] address;

input writeEn;

input strobe_i;

input clk;

input rst;

input [7:0] fifoDataIn;

input [7:0] busDataIn;

output [7:0] busDataOut;

output fifoREn;

input fifoEmpty;

output forceEmpty;

input [15:0] numElementsInFifo;

input fifoSelect;

wire [2:0] address;

wire writeEn;

wire strobe_i;

wire clk;

wire rst;

wire [7:0] fifoDataIn;

wire [7:0] busDataIn;

reg [7:0] busDataOut;

reg fifoREn;

wire fifoEmpty;

reg forceEmpty;

wire [15:0] numElementsInFifo;

wire fifoSelect;

//sync write

always @(posedge clk)

begin

if (writeEn == 1'b1 && fifoSelect == 1'b1 &&

address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)

forceEmpty <= 1'b1;

else

forceEmpty <= 1'b0;

end

// async read mux

always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)

begin

case (address)

`FIFO_DATA_REG : busDataOut <= fifoDataIn;

`FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};

`FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];

`FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];

default: busDataOut <= 8'h00;

endcase

end

//generate fifo read strobe

always @(address or writeEn or strobe_i or fifoSelect) begin

if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&

strobe_i == 1'b1 && fifoSelect == 1'b1)

fifoREn <= 1'b1;

else

fifoREn <= 1'b0;

end

endmodule

//////////////////////////////////////////////////////////////////////

//// ////

//// TxFifo.v ////

//// ////

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//> ////

//// ////

//// Module Description: ////

//// parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536

//// fifo write access via bus interface, fifo read access is direct

////

//// ////

//// To Do: ////

////

//// ////

//// Author(s): ////

//// - Steve Fielding, sfielding@base2designs.com ////

//// ////

//////////////////////////////////////////////////////////////////////

//// ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////

//// ////

//// This source file may be used and distributed without ////

//// restriction provided that this copyright statement is not ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer. ////

//// ////

//// This source file is free software; you can redistribute it ////

//// and/or modify it under the terms of the GNU Lesser General ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any ////

//// later version. ////

//// ////

//// This source is distributed in the hope that it will be ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

//// PURPOSE. See the GNU Lesser General Public License for more ////

//// details. ////

//// ////

//// You should have received a copy of the GNU Lesser General ////

//// Public License along with this source; if not, download it ////

//// from <http://www.opencores.org/lgpl.shtml> ////

//// ////

//////////////////////////////////////////////////////////////////////

//

// $Id: TxFifo.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`timescale 1ns / 1ps

module TxFifo(

clk,

rst,

fifoREn,

fifoEmpty,

busAddress,

busWriteEn,

busStrobe_i,

busFifoSelect,

busDataIn,

busDataOut,

fifoDataOut );

//FIFO_DEPTH = ADDR_WIDTH^2

parameter FIFO_DEPTH = 64;

parameter ADDR_WIDTH = 6;

input clk;

input rst;

input fifoREn;

output fifoEmpty;

input [2:0] busAddress;

input busWriteEn;

input busStrobe_i;

input busFifoSelect;

input [7:0] busDataIn;

output [7:0] busDataOut;

output [7:0] fifoDataOut;

wire clk;

wire rst;

wire fifoREn;

wire fifoEmpty;

wire [2:0] busAddress;

wire busWriteEn;

wire busStrobe_i;

wire busFifoSelect;

wire [7:0] busDataIn;

wire [7:0] busDataOut;

wire [7:0] fifoDataOut;

//internal wires and regs

wire fifoWEn;

wire forceEmpty;

wire [15:0] numElementsInFifo;

wire fifoFull;

fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(

.clk(clk),

.rst(rst),

.dataIn(busDataIn),

.dataOut(fifoDataOut),

.fifoWEn(fifoWEn),

.fifoREn(fifoREn),

.fifoFull(fifoFull),

.fifoEmpty(fifoEmpty),

.forceEmpty(forceEmpty),

.numElementsInFifo(numElementsInFifo) );

TxfifoBI u_TxfifoBI(

.address(busAddress),

.writeEn(busWriteEn),

.strobe_i(busStrobe_i),

.clk(clk),

.rst(rst),

.fifoSelect(busFifoSelect),

.busDataIn(busDataIn),

.busDataOut(busDataOut),

.fifoWEn(fifoWEn),

.fifoFull(fifoFull),

.forceEmpty(forceEmpty),

.numElementsInFifo(numElementsInFifo)

);

endmodule

//////////////////////////////////////////////////////////////////////

//// ////

//// TxfifoBI.v ////

//// ////

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//> ////

//// ////

//// Module Description: ////

////

//// ////

//// To Do: ////

////

//// ////

//// Author(s): ////

//// - Steve Fielding, sfielding@base2designs.com ////

//// ////

//////////////////////////////////////////////////////////////////////

//// ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////

//// ////

//// This source file may be used and distributed without ////

//// restriction provided that this copyright statement is not ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer. ////

//// ////

//// This source file is free software; you can redistribute it ////

//// and/or modify it under the terms of the GNU Lesser General ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any ////

//// later version. ////

//// ////

//// This source is distributed in the hope that it will be ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

//// PURPOSE. See the GNU Lesser General Public License for more ////

//// details. ////

//// ////

//// You should have received a copy of the GNU Lesser General ////

//// Public License along with this source; if not, download it ////

//// from <http://www.opencores.org/lgpl.shtml> ////

//// ////

//////////////////////////////////////////////////////////////////////

//

// $Id: TxFifoBI.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`include "wishBoneBus_h.v"

module TxfifoBI (

address, writeEn, strobe_i,

clk, rst, fifoSelect,

busDataIn,

busDataOut,

fifoWEn,

fifoFull,

forceEmpty,

numElementsInFifo

);

input [2:0] address;

input writeEn;

input strobe_i;

input clk;

input rst;

input [7:0] busDataIn;

output [7:0] busDataOut;

output fifoWEn;

input fifoFull;

output forceEmpty;

input [15:0] numElementsInFifo;

input fifoSelect;

wire [2:0] address;

wire writeEn;

wire strobe_i;

wire clk;

wire rst;

wire [7:0] busDataIn;

reg [7:0] busDataOut;

reg fifoWEn;

wire fifoFull;

reg forceEmpty;

wire [15:0] numElementsInFifo;

wire fifoSelect;

//sync write

always @(posedge clk)

begin

if (writeEn == 1'b1 && fifoSelect == 1'b1 &&

address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)

forceEmpty <= 1'b1;

else

forceEmpty <= 1'b0;

end

// async read mux

always @(address or fifoFull or numElementsInFifo)

begin

case (address)

`FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};

`FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];

`FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];

default: busDataOut <= 8'h00;

endcase

end

//generate fifo write strobe

always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin

if (address == `FIFO_DATA_REG && writeEn == 1'b1 &&

strobe_i == 1'b1 && fifoSelect == 1'b1)

fifoWEn <= 1'b1;

else

fifoWEn <= 1'b0;

end

endmodule

//////////////////////////////////////////////////////////////////////

//// ////

//// fifoMem.v ////

//// ////

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//> ////

//// ////

//// Module Description: ////

////

//// ////

//// To Do: ////

////

//// ////

//// Author(s): ////

//// - Steve Fielding, sfielding@base2designs.com ////

//// ////

//////////////////////////////////////////////////////////////////////

//// ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////

//// ////

//// This source file may be used and distributed without ////

//// restriction provided that this copyright statement is not ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer. ////

//// ////

//// This source file is free software; you can redistribute it ////

//// and/or modify it under the terms of the GNU Lesser General ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any ////

//// later version. ////

//// ////

//// This source is distributed in the hope that it will be ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

//// PURPOSE. See the GNU Lesser General Public License for more ////

//// details. ////

//// ////

//// You should have received a copy of the GNU Lesser General ////

//// Public License along with this source; if not, download it ////

//// from <http://www.opencores.org/lgpl.shtml> ////

//// ////

//////////////////////////////////////////////////////////////////////

//

// $Id: fifoMem.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`timescale 1ns / 1ps

module fifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);

//FIFO_DEPTH = ADDR_WIDTH^2

parameter FIFO_WIDTH = 8;

parameter FIFO_DEPTH = 64;

parameter ADDR_WIDTH = 6;

input clk;

input [FIFO_WIDTH-1:0] dataIn;

output [FIFO_WIDTH-1:0] dataOut;

input writeEn;

input readEn;

input [ADDR_WIDTH-1:0] addrIn;

input [ADDR_WIDTH-1:0] addrOut;

wire clk;

wire [FIFO_WIDTH-1:0] dataIn;

wire [FIFO_WIDTH-1:0] dataOut;

wire writeEn;

wire readEn;

wire [ADDR_WIDTH-1:0] addrIn;

wire [ADDR_WIDTH-1:0] addrOut;

/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(

// Generic synchronous dual-port RAM interface

.rclk(clk),

.rrst(1'b0),

.rce(1'b1),

.oe(readEn),

.raddr(addrOut),

.do(dataOut),

.wclk(clk),

.wrst(1'b0),

.wce(1'b1),

.we(writeEn),

.waddr(addrIn),

.di(dataIn)

); */

simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_simFifoMem (

.addrIn(addrIn),

.addrOut(addrOut),

.clk(clk),

.dataIn(dataIn),

.writeEn(writeEn),

.readEn(readEn),

.dataOut(dataOut));

endmodule

//////////////////////////////////////////////////////////////////////

//// ////

//// fifoRTL.v ////

//// ////

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//> ////

//// ////

//// Module Description: ////

//// parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH

//// No protection against over runs and under runs.

//// User must check full and empty flags before accessing fifo

////

//// ////

//// To Do: ////

////

//// ////

//// Author(s): ////

//// - Steve Fielding, sfielding@base2designs.com ////

//// ////

//////////////////////////////////////////////////////////////////////

//// ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////

//// ////

//// This source file may be used and distributed without ////

//// restriction provided that this copyright statement is not ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer. ////

//// ////

//// This source file is free software; you can redistribute it ////

//// and/or modify it under the terms of the GNU Lesser General ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any ////

//// later version. ////

//// ////

//// This source is distributed in the hope that it will be ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

//// PURPOSE. See the GNU Lesser General Public License for more ////

//// details. ////

//// ////

//// You should have received a copy of the GNU Lesser General ////

//// Public License along with this source; if not, download it ////

//// from <http://www.opencores.org/lgpl.shtml> ////

//// ////

//////////////////////////////////////////////////////////////////////

//

// $Id: fifoRTL.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`timescale 1ns / 1ps

module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);

//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536

parameter FIFO_WIDTH = 8;

parameter FIFO_DEPTH = 64;

parameter ADDR_WIDTH = 6;

input clk;

input rst;

input [FIFO_WIDTH-1:0] dataIn;

output [FIFO_WIDTH-1:0] dataOut;

input fifoWEn;

input fifoREn;

output fifoFull;

output fifoEmpty;

input forceEmpty;

output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536

wire clk;

wire rst;

wire [FIFO_WIDTH-1:0] dataIn;

reg [FIFO_WIDTH-1:0] dataOut;

wire fifoWEn;

wire fifoREn;

reg fifoFull;

reg fifoEmpty;

wire forceEmpty;

reg [15:0]numElementsInFifo;

// local registers

reg [ADDR_WIDTH-1:0]bufferInIndex;

reg [ADDR_WIDTH-1:0]bufferOutIndex;

reg [ADDR_WIDTH:0]bufferCnt;

reg fifoREnDelayed;

wire [FIFO_WIDTH-1:0] dataFromMem;

always @(posedge clk)

begin

if (rst == 1'b1 || forceEmpty == 1'b1)

begin

bufferCnt <= 0;

fifoFull <= 1'b0;

fifoEmpty <= 1'b1;

bufferInIndex <= 0;

bufferOutIndex <= 0;

fifoREnDelayed <= 1'b0;

end

else

begin

if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin

dataOut <= dataFromMem;

end

fifoREnDelayed <= fifoREn;

if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin

bufferCnt <= bufferCnt + 1;

bufferInIndex <= bufferInIndex + 1;

end

else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin

bufferCnt <= bufferCnt - 1;

bufferOutIndex <= bufferOutIndex + 1;

end

else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin

bufferOutIndex <= bufferOutIndex + 1;

bufferInIndex <= bufferInIndex + 1;

end

if (bufferCnt[ADDR_WIDTH] == 1'b1)

fifoFull <= 1'b1;

else

fifoFull <= 1'b0;

if (|bufferCnt == 1'b0)

fifoEmpty <= 1'b1;

else

fifoEmpty <= 1'b0;

end

end

//pad bufferCnt with leading zeroes

always @(bufferCnt) begin

numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };

end

fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_fifoMem (

.addrIn(bufferInIndex),

.addrOut(bufferOutIndex),

.clk(clk),

.dataIn(dataIn),

.writeEn(fifoWEn),

.readEn(fifoREn),

.dataOut(dataFromMem));

endmodule

//////////////////////////////////////////////////////////////////////

//// ////

//// simFifoMem.v ////

//// ////

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//> ////

//// ////

//// Module Description: ////

////

//// ////

//// To Do: ////

////

//// ////

//// Author(s): ////

//// - Steve Fielding, sfielding@base2designs.com ////

//// ////

//////////////////////////////////////////////////////////////////////

//// ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////

//// ////

//// This source file may be used and distributed without ////

//// restriction provided that this copyright statement is not ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer. ////

//// ////

//// This source file is free software; you can redistribute it ////

//// and/or modify it under the terms of the GNU Lesser General ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any ////

//// later version. ////

//// ////

//// This source is distributed in the hope that it will be ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

//// PURPOSE. See the GNU Lesser General Public License for more ////

//// details. ////

//// ////

//// You should have received a copy of the GNU Lesser General ////

//// Public License along with this source; if not, download it ////

//// from <http://www.opencores.org/lgpl.shtml> ////

//// ////

//////////////////////////////////////////////////////////////////////

//

// $Id: simFifoMem.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`timescale 1ns / 1ps

module simFifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);

//FIFO_DEPTH = ADDR_WIDTH^2

parameter FIFO_WIDTH = 8;

parameter FIFO_DEPTH = 64;

parameter ADDR_WIDTH = 6;

input clk;

input [FIFO_WIDTH-1:0] dataIn;

output [FIFO_WIDTH-1:0] dataOut;

input writeEn;

input readEn;

input [ADDR_WIDTH-1:0] addrIn;

input [ADDR_WIDTH-1:0] addrOut;

wire clk;

wire [FIFO_WIDTH-1:0] dataIn;

reg [FIFO_WIDTH-1:0] dataOut;

wire writeEn;

wire readEn;

wire [ADDR_WIDTH-1:0] addrIn;

wire [ADDR_WIDTH-1:0] addrOut;

reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];

// synchronous read. Introduces one clock cycle delay

always @(posedge clk) begin

dataOut <= buffer[addrOut];

end

// synchronous write

always @(posedge clk) begin

if (writeEn == 1'b1)

buffer[addrIn] <= dataIn;

end

endmodule

//////////////////////////////////////////////////////////////////////

//// ////

//// usbSerialInterfaceEngine_h.v ////

//// ////

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//> ////

//// ////

//// Module Description: ////

////

//// ////

//// To Do: ////

////

//// ////

//// Author(s): ////

//// - Steve Fielding, sfielding@base2designs.com ////

//// ////

//////////////////////////////////////////////////////////////////////

//// ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////

//// ////

//// This source file may be used and distributed without ////

//// restriction provided that this copyright statement is not ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer. ////

//// ////

//// This source file is free software; you can redistribute it ////

//// and/or modify it under the terms of the GNU Lesser General ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any ////

//// later version. ////

//// ////

//// This source is distributed in the hope that it will be ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

//// PURPOSE. See the GNU Lesser General Public License for more ////

//// details. ////

//// ////

//// You should have received a copy of the GNU Lesser General ////

//// Public License along with this source; if not, download it ////

//// from <http://www.opencores.org/lgpl.shtml> ////

//// ////

//////////////////////////////////////////////////////////////////////

//

// $Id: usbSerialInterfaceEngine_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

// Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate

`define OVER_SAMPLE_RATE 4

//timeOuts

`define RX_PACKET_TOUT 18

//TXStreamControlTypes

`define TX_DIRECT_CONTROL 8'h00

`define TX_RESUME_START 8'h01

`define TX_PACKET_START 8'h02

`define TX_PACKET_STREAM 8'h03

`define TX_PACKET_STOP 8'h04

`define TX_IDLE 8'h05

//RXStreamControlTypes

`define RX_PACKET_START 0

`define RX_PACKET_STREAM 1

`define RX_PACKET_STOP 2

//USBLineStates

// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo

`define ONE_ZERO 2'b10

`define ZERO_ONE 2'b01

`define SE0 2'b00

`define SE1 2'b11

//RXStatusIndices

`define CRC_ERROR_BIT 0

`define BIT_STUFF_ERROR_BIT 1

`define RX_OVERFLOW_BIT 2

`define NAK_RXED_BIT 3

`define STALL_RXED_BIT 4

`define ACK_RXED_BIT 5

`define DATA_SEQUENCE_BIT 6

//usbWireControlStates

`define TRI_STATE 1'b0

`define DRIVE 1'b1

//limits

`define MAX_CONSEC_SAME_BITS 6

`define RESUME_WAIT_TIME 10

`define RESUME_WAIT_TIME_MINUS1 9

`define RESUME_LEN 20

`define CONNECT_WAIT_TIME 8'd20

`define DISCONNECT_WAIT_TIME 8'd20

//RXConnectStates

`define DISCONNECT 2'b00

`define LOW_SPEED_CONNECT 2'b01

`define FULL_SPEED_CONNECT 2'b10

//TX_RX_InternalStreamTypes

`define DATA_START 8'h00

`define DATA_STOP 8'h01

`define DATA_STREAM 8'h02

`define DATA_BIT_STUFF_ERROR 8'h03

//RXStMach states

`define DISCONNECT_ST 4'h0

`define WAIT_FULL_SPEED_CONN_ST 4'h1

`define WAIT_LOW_SPEED_CONN_ST 4'h2

`define CONNECT_LOW_SPEED_ST 4'h3

`define CONNECT_FULL_SPEED_ST 4'h4

`define WAIT_LOW_SP_DISCONNECT_ST 4'h5

`define WAIT_FULL_SP_DISCONNECT_ST 4'h6

//RXBitStateMachStates

`define IDLE_BIT_ST 2'b00

`define DATA_RECEIVE_BIT_ST 2'b01

`define WAIT_RESUME_ST 2'b10

`define RESUME_END_WAIT_ST 2'b11

//RXByteStateMachStates

`define IDLE_BYTE_ST 3'b000

`define CHECK_SYNC_ST 3'b001

`define CHECK_PID_ST 3'b010

`define HS_BYTE_ST 3'b011

`define TOKEN_BYTE_ST 3'b100

`define DATA_BYTE_ST 3'b101

//--------------------------------------------------------------------------------------------------

//

// Title : No Title

// Design : usbhostslave

// Author : Steve

// Company : Base2Designs

//

//-------------------------------------------------------------------------------------------------

//

// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sofcontroller.v

// Generated : 09/08/04 06:24:36

// From : c:\projects\USBHostSlave\RTL\hostController\sofcontroller.asf

// By : FSM2VHDL ver. 4.0.3.8

//

//-------------------------------------------------------------------------------------------------

//

// Description :

//

//-------------------------------------------------------------------------------------------------

`timescale 1ns / 1ps

`include "usbSerialInterfaceEngine_h.v"

module SOFController (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, SOFEnable, SOFTimerClr, SOFTimer, clk, rst);

input HCTxPortGnt;

input HCTxPortRdy;

input SOFEnable;

input SOFTimerClr;

input clk;

input rst;

output [7:0] HCTxPortCntl;

output [7:0] HCTxPortData;

output HCTxPortReq;

output HCTxPortWEn;

output [15:0] SOFTimer;

reg [7:0] HCTxPortCntl, next_HCTxPortCntl;

reg [7:0] HCTxPortData, next_HCTxPortData;

wire HCTxPortGnt;

wire HCTxPortRdy;

reg HCTxPortReq, next_HCTxPortReq;

reg HCTxPortWEn, next_HCTxPortWEn;

wire SOFEnable;

wire SOFTimerClr;

reg [15:0] SOFTimer, next_SOFTimer;

wire clk;

wire rst;

// BINARY ENCODED state machine: sofCntl

// State codes definitions:

`define START_SC 3'b000

`define WAIT_SOF_EN 3'b001

`define WAIT_SEND_RESUME 3'b010

`define INC_TIMER 3'b011

`define SC_WAIT_GNT 3'b100

`define CLR_WEN 3'b101

reg [2:0] CurrState_sofCntl;

reg [2:0] NextState_sofCntl;

//--------------------------------------------------------------------

// Machine: sofCntl

//--------------------------------------------------------------------

//----------------------------------

// NextState logic (combinatorial)

//----------------------------------

always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl)

begin : sofCntl_NextState

NextState_sofCntl <= CurrState_sofCntl;

// Set default values for outputs and signals

next_HCTxPortReq <= HCTxPortReq;

next_HCTxPortWEn <= HCTxPortWEn;

next_HCTxPortData <= HCTxPortData;

next_HCTxPortCntl <= HCTxPortCntl;

next_SOFTimer <= SOFTimer;

case (CurrState_sofCntl) // synopsys parallel_case full_case

`START_SC:

NextState_sofCntl <= `WAIT_SOF_EN;

`WAIT_SOF_EN:

if (SOFEnable == 1'b1)

begin

NextState_sofCntl <= `SC_WAIT_GNT;

next_HCTxPortReq <= 1'b1;

end

`WAIT_SEND_RESUME:

if (HCTxPortRdy == 1'b1)

begin

NextState_sofCntl <= `CLR_WEN;

next_HCTxPortWEn <= 1'b1;

next_HCTxPortData <= 8'h00;

next_HCTxPortCntl <= `TX_RESUME_START;

end

`INC_TIMER:

begin

next_HCTxPortReq <= 1'b0;

if (SOFTimerClr == 1'b1)

next_SOFTimer <= 16'h0000;

else

next_SOFTimer <= SOFTimer + 1'b1;

if (SOFEnable == 1'b0)

begin

NextState_sofCntl <= `WAIT_SOF_EN;

next_SOFTimer <= 16'h0000;

end

end

`SC_WAIT_GNT:

if (HCTxPortGnt == 1'b1)

NextState_sofCntl <= `WAIT_SEND_RESUME;

`CLR_WEN:

begin

next_HCTxPortWEn <= 1'b0;

NextState_sofCntl <= `INC_TIMER;

end

endcase

end

//----------------------------------

// Current State Logic (sequential)

//----------------------------------

always @ (posedge clk)

begin : sofCntl_CurrentState

if (rst)

CurrState_sofCntl <= `START_SC;

else

CurrState_sofCntl <= NextState_sofCntl;

end

//----------------------------------

// Registered outputs logic

//----------------------------------

always @ (posedge clk)

begin : sofCntl_RegOutput

if (rst)

begin

SOFTimer <= 16'h0000;

HCTxPortCntl <= 8'h00;

HCTxPortData <= 8'h00;

HCTxPortWEn <= 1'b0;

HCTxPortReq <= 1'b0;

end

else

begin

SOFTimer <= next_SOFTimer;

HCTxPortCntl <= next_HCTxPortCntl;

HCTxPortData <= next_HCTxPortData;

HCTxPortWEn <= next_HCTxPortWEn;

HCTxPortReq <= next_HCTxPortReq;

end

end

endmodule

//--------------------------------------------------------------------------------------------------

//

// Title : No Title

// Design : usbhostslave

// Author :

// Company :

//

//-------------------------------------------------------------------------------------------------

//

// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\softransmit.v

// Generated : 09/14/04 21:51:27

// From : c:\projects\USBHostSlave\RTL\hostController\softransmit.asf

// By : FSM2VHDL ver. 4.0.3.8

//

//-------------------------------------------------------------------------------------------------

//

// Description :

//

//-------------------------------------------------------------------------------------------------

`timescale 1ns / 1ps

`include "usbHostControl_h.v"

module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn);

input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn

input SOFSyncEn;

input [15:0] SOFTimer;

input clk;

input rst;

input sendPacketArbiterGnt;

input sendPacketRdy;

output SOFSent; // single cycle pulse

output SOFTimerClr; // Single cycle pulse

output sendPacketArbiterReq;

output sendPacketWEn;

wire SOFEnable;

reg SOFSent, next_SOFSent;

wire SOFSyncEn;

reg SOFTimerClr, next_SOFTimerClr;

wire [15:0] SOFTimer;

wire clk;

wire rst;

wire sendPacketArbiterGnt;

reg sendPacketArbiterReq, next_sendPacketArbiterReq;

wire sendPacketRdy;

reg sendPacketWEn, next_sendPacketWEn;

// BINARY ENCODED state machine: SOFTx

// State codes definitions:

`define START_STX 3'b000

`define WAIT_SOF_NEAR 3'b001

`define WAIT_SP_GNT 3'b010

`define WAIT_SOF_NOW 3'b011

`define SOF_FIN 3'b100

reg [2:0] CurrState_SOFTx;

reg [2:0] NextState_SOFTx;

//--------------------------------------------------------------------

// Machine: SOFTx

//--------------------------------------------------------------------

//----------------------------------

// NextState logic (combinatorial)

//----------------------------------

always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)

begin : SOFTx_NextState

NextState_SOFTx <= CurrState_SOFTx;

// Set default values for outputs and signals

next_sendPacketArbiterReq <= sendPacketArbiterReq;

next_sendPacketWEn <= sendPacketWEn;

next_SOFTimerClr <= SOFTimerClr;

next_SOFSent <= SOFSent;

case (CurrState_SOFTx) // synopsys parallel_case full_case

`START_STX:

NextState_SOFTx <= `WAIT_SOF_NEAR;

`WAIT_SOF_NEAR:

if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||

(SOFSyncEn == 1'b1 &&

SOFEnable == 1'b1))

begin

NextState_SOFTx <= `WAIT_SP_GNT;

next_sendPacketArbiterReq <= 1'b1;

end

`WAIT_SP_GNT:

if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)

NextState_SOFTx <= `WAIT_SOF_NOW;

`WAIT_SOF_NOW:

if (SOFTimer >= `SOF_TX_TIME)

begin

NextState_SOFTx <= `SOF_FIN;

next_sendPacketWEn <= 1'b1;

next_SOFTimerClr <= 1'b1;

next_SOFSent <= 1'b1;

end

else if (SOFEnable == 1'b0)

begin

NextState_SOFTx <= `SOF_FIN;

next_SOFTimerClr <= 1'b1;

end

`SOF_FIN:

begin

next_sendPacketWEn <= 1'b0;

next_SOFTimerClr <= 1'b0;

next_SOFSent <= 1'b0;

NextState_SOFTx <= `WAIT_SOF_NEAR;

next_sendPacketArbiterReq <= 1'b0;

end

endcase

end

//----------------------------------

// Current State Logic (sequential)

//----------------------------------

always @ (posedge clk)

begin : SOFTx_CurrentState

if (rst)

CurrState_SOFTx <= `START_STX;

else

CurrState_SOFTx <= NextState_SOFTx;

end

//----------------------------------

// Registered outputs logic

//----------------------------------

always @ (posedge clk)

begin : SOFTx_RegOutput

if (rst)

begin

SOFSent <= 1'b0;

SOFTimerClr <= 1'b0;

sendPacketArbiterReq <= 1'b0;

sendPacketWEn <= 1'b0;

end

else

begin

SOFSent <= next_SOFSent;

SOFTimerClr <= next_SOFTimerClr;

sendPacketArbiterReq <= next_sendPacketArbiterReq;

sendPacketWEn <= next_sendPacketWEn;

end

end

endmodule

//////////////////////////////////////////////////////////////////////

//// ////

//// usbHostControl.v ////

//// ////

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//> ////

//// ////

//// Module Description: ////

////

//// ////

//// To Do: ////

////

//// ////

//// Author(s): ////

//// - Steve Fielding, sfielding@base2designs.com ////

//// ////

//////////////////////////////////////////////////////////////////////

//// ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////

//// ////

//// This source file may be used and distributed without ////

//// restriction provided that this copyright statement is not ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer. ////

//// ////

//// This source file is free software; you can redistribute it ////

//// and/or modify it under the terms of the GNU Lesser General ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any ////

//// later version. ////

//// ////

//// This source is distributed in the hope that it will be ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////

//// PURPOSE. See the GNU Lesser General Public License for more ////

//// details. ////

//// ////

//// You should have received a copy of the GNU Lesser General ////

//// Public License along with this source; if not, download it ////

//// from <http://www.opencores.org/lgpl.shtml> ////

//// ////

//////////////////////////////////////////////////////////////////////

//

// $Id: usbHostControl.v,v 1.1.1.1 2004-10-11 04:00:56 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

module usbHostControl(

clk, rst,

//sendPacket

TxFifoRE, TxFifoData, TxFifoEmpty,

//getPacket

RxFifoWE, RxFifoData, RxFifoFull,

RxByteStatus, RxData, RxDataValid,

SIERxTimeOut,

//speedCtrlMux

fullSpeedRate, fullSpeedPol,

//HCTxPortArbiter

HCTxPortEn, HCTxPortRdy,

HCTxPortData, HCTxPortCtrl,

//rxStatusMonitor

connectStateIn,

resumeDetectedIn,

//USBHostControlBI

busAddress,

busDataIn,

busDataOut,

busWriteEn,

busStrobe_i,

SOFSentIntOut,

connEventIntOut,

resumeIntOut,

transDoneIntOut,

hostControlSelect

);

input clk, rst;

//sendPacket

output TxFifoRE;

input [7:0] TxFifoData;

input TxFifoEmpty;

//getPacket

output RxFifoWE;

output [7:0] RxFifoData;