EclaireXL

===========================================

MCCTV Atari 800XL core v0.60 release note

===========================================

Mark Watson

scrameta@gmail.com

-------------------------------------------

All control is via the MCC controller.

Currently games are limited to those that can be played with start/select/option/reset and joystick.

Special/console keys (joystick 1):

Start button or button 4 - Start

Select button or button 3 - Select

button 2 - Option

left shoulder 1 - Reset

left shoulder 2 - Cold start (clear base 64KB RAM and reset)

right shoulder 1 - Select drive 1 and cold start

Use joystick to make selection in menu

Left - up several lines

Right - down several lines

Up - up 1 line

Down - down 1 line

Fire - select

Remember many titles require holding 'option'

Select "DIR .." to go up a directory

Select "DIR xxx" to go down a directory

right shoulder 2 - System settings menu

Use joystick to make selection

Turbo - system speed

Left/right to select

1x (default): is very compatible - speed closely matches original hardware ~1.7MHz

2x: ~3.4MHz - less compatible

4x: ~6.8MHz - less compatible

8x/16x: 13MHz, 27MHZ - limited by SDRAM latency, not quicker than 4x yet.

RAM

Left/right to select

64KB: like 65XE

128KB: like 130XE, 64KB ext ram, switchable by antic/cpu

320KB(Compy shop)(default): 256KB ext ram, switchable by antic/cpu

320KB(Rambo): 256KB ext ram, both antic/cpu switch together

576KB(Compy shop): 512KB ext ram, switchable by antic/cpu

576KB(Rambo): 512KB ext ram, both antic/cpu switch together

1088KB: 1024KB ext ram, both antic/cpu switch together

4160KB: - very imcompatible!

ROM

Right/fire: File selector

Select a different system OS ROM - can by 16KB or 10KB

Drive

Left: Remove disk

Right: File selector

Fire: Put this disk in F1

Cartridge 8K simple

Fire: select file

This allows a ROM to be loaded in the place of BASIC

Some simple ROM cartridges can be used

This is temporary until proper cartridge support is implemented

System ROM:

Loaded from /System/rom/atari800/atarixl.rom

Basic:

Loaded from /System/rom/atari800/ataribas.rom

Disk images:

Default dir: /atari800/user

Supported types:

.ATR - Atari disk image with header. single/medium/double density.

.XFD - Atari disk image without header.

.XEX - Atari executable. A simple bootloader is loaded, not 100% compatible.

Important notes:

When running Atari software a lot of programs need to have basic disable. Hold option when pressing reset.

Features

* Acid 800 test pass

* 99% of software runs

* Version for PAL/NTSC VGA/SVIDEO

* Write support

* Drive emulation

Known issues

* No keyboard support yet

* ~1% of programs fail

* Copymate write verify fails

* Entering menu during disk access may hang ZPU (used for drive emulation/menus)

* Hardware matches Atari very closely - including overscan corruption - this often shows up on VGA monitors.

* Cartridge support may be broken

Enjoy !

Merge with mcc216 core - with generic to select composite, sdram size, keyboard/usb etc.

USB keyboard support?

On screen keyboard support?

<sld_project_info>

<project>

<hash md5_digest_80b="00000000000000000000"/>

</project>

<file_info/>

</sld_project_info>

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2012 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors. Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II 64-Bit

# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition

# Date created = 13:58:38 April 11, 2013

#

# -------------------------------------------------------------------------- #

QUARTUS_VERSION = "12.1"

DATE = "13:58:38 April 11, 2013"

# Revisions

PROJECT_REVISION = "atari800core"

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2009 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors. Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II

# Version 9.0 Build 132 02/25/2009 SJ Web Edition

# Date created = 20:12:08 December 25, 2009

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

# atari800core_mcc_assignment_defaults.qdf

# If this file doesn't exist, see file:

# assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

# file is updated automatically by the Quartus II software

# and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name DEVICE EP4CE15E22C7

set_global_assignment -name FAMILY "Cyclone IV E"

set_global_assignment -name TOP_LEVEL_ENTITY atari800core_mcc

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:12:08 DECEMBER 25, 2009"

set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"

set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS128

set_global_assignment -name GENERATE_RBF_FILE ON

set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"

set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON

set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

set_global_assignment -name ENABLE_SIGNALTAP ON

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF

set_global_assignment -name SIMULATION_MODE TIMING

set_location_assignment PIN_46 -to AUDIO_L

set_location_assignment PIN_49 -to AUDIO_R

set_location_assignment PIN_55 -to FPGA_CLK

set_location_assignment PIN_42 -to SD_CLK

set_location_assignment PIN_43 -to SD_CMD

set_location_assignment PIN_44 -to SD_DAT3

set_location_assignment PIN_52 -to SD_DAT0

set_location_assignment PIN_59 -to SDRAM_A[0]

set_location_assignment PIN_58 -to SDRAM_A[1]

set_location_assignment PIN_51 -to SDRAM_A[2]

set_location_assignment PIN_50 -to SDRAM_A[3]

set_location_assignment PIN_132 -to SDRAM_A[4]

set_location_assignment PIN_125 -to SDRAM_A[5]

set_location_assignment PIN_121 -to SDRAM_A[6]

set_location_assignment PIN_120 -to SDRAM_A[7]

set_location_assignment PIN_119 -to SDRAM_A[8]

set_location_assignment PIN_115 -to SDRAM_A[9]

set_location_assignment PIN_60 -to SDRAM_A[10]

set_location_assignment PIN_114 -to SDRAM_A[11]

set_location_assignment PIN_113 -to SDRAM_A[12]

set_location_assignment PIN_111 -to SDRAM_CLK

set_location_assignment PIN_110 -to SDRAM_DQMH_n

set_location_assignment PIN_71 -to SDRAM_DQML_n

set_location_assignment PIN_106 -to SDRAM_DQ[8]

set_location_assignment PIN_105 -to SDRAM_DQ[9]

set_location_assignment PIN_104 -to SDRAM_DQ[10]

set_location_assignment PIN_103 -to SDRAM_DQ[11]

set_location_assignment PIN_101 -to SDRAM_DQ[12]

set_location_assignment PIN_100 -to SDRAM_DQ[13]

set_location_assignment PIN_99 -to SDRAM_DQ[14]

set_location_assignment PIN_98 -to SDRAM_DQ[15]

set_location_assignment PIN_72 -to SDRAM_DQ[7]

set_location_assignment PIN_76 -to SDRAM_DQ[6]

set_location_assignment PIN_77 -to SDRAM_DQ[5]

set_location_assignment PIN_80 -to SDRAM_DQ[4]

set_location_assignment PIN_83 -to SDRAM_DQ[3]

set_location_assignment PIN_85 -to SDRAM_DQ[2]

set_location_assignment PIN_86 -to SDRAM_DQ[1]

set_location_assignment PIN_87 -to SDRAM_DQ[0]

set_location_assignment PIN_68 -to SDRAM_CAS_n

set_location_assignment PIN_66 -to SDRAM_CS_n

set_location_assignment PIN_64 -to SDRAM_BA[1]

set_location_assignment PIN_65 -to SDRAM_BA[0]

set_location_assignment PIN_67 -to SDRAM_RAS_n

set_location_assignment PIN_69 -to SDRAM_WE_n

set_location_assignment PIN_112 -to SDRAM_CKE

set_location_assignment PIN_144 -to VGA_G[0]

set_location_assignment PIN_143 -to VGA_G[1]

set_location_assignment PIN_142 -to VGA_G[2]

set_location_assignment PIN_141 -to VGA_G[3]

set_location_assignment PIN_137 -to VGA_B[0]

set_location_assignment PIN_136 -to VGA_B[1]

set_location_assignment PIN_135 -to VGA_B[2]

set_location_assignment PIN_133 -to VGA_B[3]

set_location_assignment PIN_12 -to CFG_CLK

set_location_assignment PIN_8 -to CFG_CS_n

set_location_assignment PIN_13 -to CFG_DIN

set_location_assignment PIN_6 -to CFG_DOUT

set_location_assignment PIN_31 -to dplus1

set_location_assignment PIN_30 -to dminus1

set_location_assignment PIN_33 -to dplus2

set_location_assignment PIN_32 -to dminus2

set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH_n

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML_n

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS

set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]

set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"

set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

set_global_assignment -name USE_SIGNALTAP_FILE atari.stp

set_location_assignment PLL_2 -to "clk_reset:clk_rst_inst|pll_main:main_inst"

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQMH_n

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQML_n

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n

set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n

set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON

set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS

set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON

set_global_assignment -name IGNORE_LCELL_BUFFERS ON

set_global_assignment -name IGNORE_CASCADE_BUFFERS ON

set_location_assignment PLL_4 -to "clk_reset:clk_rst_inst|pll_5M_pal_ntsc:pll_5m_inst" -disable

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name QIP_FILE pll_usb.qip

set_global_assignment -name QIP_FILE pal_pll.qip

set_global_assignment -name QIP_FILE pll_downstream_pal.qip

set_global_assignment -name QIP_FILE ntsc_pll.qip

set_global_assignment -name QIP_FILE pll_downstream_ntsc.qip

set_global_assignment -name SDC_FILE atari800core.sdc

set_global_assignment -name VERILOG_FILE sdram_ctrl_3_ports.v

set_global_assignment -name VHDL_FILE zpu_rom.vhdl

set_global_assignment -name VHDL_FILE atari800core_mcc.vhd

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name USE_CONFIGURATION_DEVICE OFF

set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

create_clock -period 5MHz [get_ports FPGA_CLK]

derive_pll_clocks

derive_clock_uncertainty

#onerror {resume}

# GAME

#=====================

#run 18871970 ns

#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns

#run 200 ms

-- megafunction wizard: %ALTPLL%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altpll

-- ============================================================

-- File Name: pll_usb.vhd

-- Megafunction Name(s):

-- altpll

--

-- Simulation Library Files(s):

-- altera_mf

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition

-- ************************************************************

--Copyright (C) 1991-2013 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, Altera MegaCore Function License

--Agreement, or other applicable license agreement, including,

--without limitation, that your use is for the sole purpose of

--programming logic devices manufactured by Altera and sold by

--Altera or its authorized distributors. Please refer to the

--applicable agreement for further details.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY pll_usb IS

PORT

(

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

END pll_usb;

ARCHITECTURE SYN OF pll_usb IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC ;

SIGNAL sub_wire2 : STD_LOGIC ;

SIGNAL sub_wire3 : STD_LOGIC ;

SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);

SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);

SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);

COMPONENT altpll

GENERIC (

bandwidth_type : STRING;

clk0_divide_by : NATURAL;

clk0_duty_cycle : NATURAL;

clk0_multiply_by : NATURAL;

clk0_phase_shift : STRING;

compensate_clock : STRING;

inclk0_input_frequency : NATURAL;

intended_device_family : STRING;

lpm_hint : STRING;

lpm_type : STRING;

operation_mode : STRING;

pll_type : STRING;

port_activeclock : STRING;

port_areset : STRING;

port_clkbad0 : STRING;

port_clkbad1 : STRING;

port_clkloss : STRING;

port_clkswitch : STRING;

port_configupdate : STRING;

port_fbin : STRING;

port_inclk0 : STRING;

port_inclk1 : STRING;

port_locked : STRING;

port_pfdena : STRING;

port_phasecounterselect : STRING;

port_phasedone : STRING;

port_phasestep : STRING;

port_phaseupdown : STRING;

port_pllena : STRING;

port_scanaclr : STRING;

port_scanclk : STRING;

port_scanclkena : STRING;

port_scandata : STRING;

port_scandataout : STRING;

port_scandone : STRING;

port_scanread : STRING;

port_scanwrite : STRING;

port_clk0 : STRING;

port_clk1 : STRING;

port_clk2 : STRING;

port_clk3 : STRING;

port_clk4 : STRING;

port_clk5 : STRING;

port_clkena0 : STRING;

port_clkena1 : STRING;

port_clkena2 : STRING;

port_clkena3 : STRING;

port_clkena4 : STRING;

port_clkena5 : STRING;

port_extclk0 : STRING;

port_extclk1 : STRING;

port_extclk2 : STRING;

port_extclk3 : STRING;

self_reset_on_loss_lock : STRING;

width_clock : NATURAL

);

PORT (

clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);

inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

locked : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

sub_wire5_bv(0 DOWNTO 0) <= "0";

sub_wire5 <= To_stdlogicvector(sub_wire5_bv);

sub_wire1 <= sub_wire0(0);

c0 <= sub_wire1;

locked <= sub_wire2;

sub_wire3 <= inclk0;

sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;

altpll_component : altpll

GENERIC MAP (

bandwidth_type => "AUTO",

clk0_divide_by => 1,

clk0_duty_cycle => 50,

clk0_multiply_by => 3,

clk0_phase_shift => "0",

compensate_clock => "CLK0",

inclk0_input_frequency => 200000,

intended_device_family => "Cyclone IV E",

lpm_hint => "CBX_MODULE_PREFIX=pll_usb",

lpm_type => "altpll",

operation_mode => "NORMAL",

pll_type => "AUTO",

port_activeclock => "PORT_UNUSED",

port_areset => "PORT_UNUSED",

port_clkbad0 => "PORT_UNUSED",

port_clkbad1 => "PORT_UNUSED",

port_clkloss => "PORT_UNUSED",

port_clkswitch => "PORT_UNUSED",

port_configupdate => "PORT_UNUSED",

port_fbin => "PORT_UNUSED",

port_inclk0 => "PORT_USED",

port_inclk1 => "PORT_UNUSED",

port_locked => "PORT_USED",

port_pfdena => "PORT_UNUSED",

port_phasecounterselect => "PORT_UNUSED",

port_phasedone => "PORT_UNUSED",

port_phasestep => "PORT_UNUSED",

port_phaseupdown => "PORT_UNUSED",

port_pllena => "PORT_UNUSED",

port_scanaclr => "PORT_UNUSED",

port_scanclk => "PORT_UNUSED",

port_scanclkena => "PORT_UNUSED",

port_scandata => "PORT_UNUSED",

port_scandataout => "PORT_UNUSED",

port_scandone => "PORT_UNUSED",

port_scanread => "PORT_UNUSED",

port_scanwrite => "PORT_UNUSED",

port_clk0 => "PORT_USED",

port_clk1 => "PORT_UNUSED",

port_clk2 => "PORT_UNUSED",

port_clk3 => "PORT_UNUSED",

port_clk4 => "PORT_UNUSED",

port_clk5 => "PORT_UNUSED",

port_clkena0 => "PORT_UNUSED",

port_clkena1 => "PORT_UNUSED",

port_clkena2 => "PORT_UNUSED",

port_clkena3 => "PORT_UNUSED",

port_clkena4 => "PORT_UNUSED",

port_clkena5 => "PORT_UNUSED",

port_extclk0 => "PORT_UNUSED",

port_extclk1 => "PORT_UNUSED",

port_extclk2 => "PORT_UNUSED",

port_extclk3 => "PORT_UNUSED",

self_reset_on_loss_lock => "OFF",

width_clock => 5

)

PORT MAP (

inclk => sub_wire4,

clk => sub_wire0,

locked => sub_wire2

);

END SYN;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"

-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"

-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"

-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"

-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"

-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"

-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"

-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"

-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"

-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"

-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"

-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"

-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"

-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"

-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"

-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"

-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"

-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"

-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "15.000000"

-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"

-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"

-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"

-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"

-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"

-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"

-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"

-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"

-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"

-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"

-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"

-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"

-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"

-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"

-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"

-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"

-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"

-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"

-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"

-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"

-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"

-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"

-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"

-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "15.00000000"

-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"

-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"

-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"

-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"

-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"

-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"

-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"

-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"

-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"

-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"

-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"

-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"

-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"

-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"

-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"

-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"

-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"

-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_usb.mif"

-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"

-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"

-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"

-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"

-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"

-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"

-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"

-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"

-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"

-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"

-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"

-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"

-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"

-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"

-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"

-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"

-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"

-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"

-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"

-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"

-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"

-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"

-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"

-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"

-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"

-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"

-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"

-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"

-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"

-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"

-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"

-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"

-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"

-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"

-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"

-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0

-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0

-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0

-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.ppf TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.cmp TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb_inst.vhd FALSE

-- Retrieval info: LIB_FILE: altera_mf

-- Retrieval info: CBX_MODULE_PREFIX: ON

---------------------------------------------------------------------------

-- (c) 2013 mark watson

-- I am happy for anyone to use this for non-commercial use.

-- If my vhdl files are used commercially or otherwise sold,

-- please contact me for explicit permission at scrameta (gmail).

-- This applies for source and binary form and derived works.

---------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

use ieee.numeric_std.all;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

use WORK.USBF_Declares.all;

LIBRARY work;

ENTITY atari800core_mcc IS

GENERIC

(

TV : integer; -- 1 = PAL, 0=NTSC

internal_rom : integer;

internal_ram : integer;

ext_clock : integer

);

PORT

(

FPGA_CLK : IN STD_LOGIC; -- crystal appears to be still 5MHz despite comment in file I was sent...

-- For test bench

EXT_CLK_SDRAM : in std_logic_vector(ext_clock downto 1);

EXT_CLK : in std_logic_vector(ext_clock downto 1);

EXT_SDRAM_CLK : in std_logic_vector(ext_clock downto 1);

EXT_SVIDEO_DAC_CLK : in std_logic_vector(ext_clock downto 1);

EXT_PLL_LOCKED : in std_logic_vector(ext_clock downto 1);

--PS2K_CLK : IN STD_LOGIC;

--PS2K_DAT : IN STD_LOGIC;

--PS2M_CLK : IN STD_LOGIC;

--PS2M_DAT : IN STD_LOGIC;

-- VGA/cough cough... (composite...)

--VGA_VS : OUT STD_LOGIC;

--VGA_HS : OUT STD_LOGIC;

VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- high bits composite

VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- low bits composite

--VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

--JOY1_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);

--JOY2_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);

----USB CONNECTIONS (with one 1.5K pull up to 3.3v) ---------------

dplus1 : inout std_logic; --D+ data line , pin D16

dminus1 : inout std_logic; --D- data line, pin E14

----USB CONNECTIONS (with one 1.5K pull up to 3.3v) ---------------

dplus2 : inout std_logic; --D+ data line , pin D16

dminus2 : inout std_logic; --D- data line, pin E14

AUDIO_L : OUT std_logic;

AUDIO_R : OUT std_logic;

SDRAM_BA : OUT STD_LOGIC_VECTOR(1 downto 0);

SDRAM_CS_N : OUT STD_LOGIC;

SDRAM_RAS_N : OUT STD_LOGIC;

SDRAM_CAS_N : OUT STD_LOGIC;

SDRAM_WE_N : OUT STD_LOGIC;

SDRAM_DQMH_n : OUT STD_LOGIC;

SDRAM_DQML_n : OUT STD_LOGIC;

SDRAM_CLK : OUT STD_LOGIC;

SDRAM_CKE : OUT STD_LOGIC;

SDRAM_A : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);

SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

SD_DAT0 : IN STD_LOGIC;

SD_CLK : OUT STD_LOGIC;

SD_CMD : OUT STD_LOGIC;

SD_DAT3 : OUT STD_LOGIC;

-- SPI flash clock

CFG_CLK : OUT STD_LOGIC;

CFG_CS_n : OUT STD_LOGIC;

CFG_DOUT : OUT STD_LOGIC;

CFG_DIN : IN STD_LOGIC

);

END atari800core_mcc;

ARCHITECTURE vhdl OF atari800core_mcc IS

component hq_dac

port (

reset :in std_logic;

clk :in std_logic;

clk_ena : in std_logic;

pcm_in : in std_logic_vector(19 downto 0);

dac_out : out std_logic

);

end component;

COMPONENT sdram_ctrl

port

(

--//--------------------

--// Clocks and reset --

--//--------------------

--// Global reset

rst : in std_logic;

--// Controller clock

clk : in std_logic;

--// Sequencer cycles

seq_cyc : in std_logic_vector(11 downto 0);

--// Sequencer phase

seq_ph : in std_logic;

--// Refresh cycle

refr_cyc : in std_logic;

--//------------------------

--// Access port #1 (CPU) --

--//------------------------

--// RAM select

ap1_ram_sel : in std_logic;

--// Address bus

ap1_address : in std_logic_vector(23 downto 1);

--// Read enable

ap1_rden : in std_logic;

--// Write enable

ap1_wren : in std_logic;

--// Byte enable

ap1_bena : in std_logic_vector(1 downto 0);

--// Data bus (read)

ap1_rddata : out std_logic_vector(15 downto 0);

--// Data bus (write)

ap1_wrdata : in std_logic_vector(15 downto 0);

--// Burst size

ap1_bst_siz : in std_logic_vector(2 downto 0);

--// Read burst active

ap1_rd_bst_act : out std_logic;

--// Write burst active

ap1_wr_bst_act : out std_logic;

--//------------------------

--// Access port #2 (GPU) --

--//------------------------

--// RAM select

ap2_ram_sel : in std_logic;

--// Address bus

ap2_address : in std_logic_vector(23 downto 1);

--// Read enable

ap2_rden : in std_logic;

--// Write enable

ap2_wren : in std_logic;

--// Byte enable

ap2_bena : in std_logic_vector(1 downto 0);

--// Data bus (read)

ap2_rddata : out std_logic_vector(15 downto 0);

--// Data bus (write)

ap2_wrdata : in std_logic_vector(15 downto 0);

--// Burst size

ap2_bst_siz : in std_logic_vector(2 downto 0);

--// Read burst active

ap2_rd_bst_act : out std_logic;

--// Write burst active

ap2_wr_bst_act : out std_logic;

--//------------------------

--// Access port #3 (CTL) --

--//------------------------

--// RAM select

ap3_ram_sel : in std_logic;

--// Address bus

ap3_address : in std_logic_vector(23 downto 1);

--// Read enable

ap3_rden : in std_logic;

--// Write enable

ap3_wren : in std_logic;

--// Byte enable

ap3_bena : in std_logic_vector(1 downto 0);

--// Data bus (read)

ap3_rddata : out std_logic_vector(15 downto 0);

--// Data bus (write)

ap3_wrdata : in std_logic_vector(15 downto 0);

--// Burst size

ap3_bst_siz : in std_logic_vector(2 downto 0);

--// Read burst active

ap3_rd_bst_act : out std_logic;

--// Write burst active

ap3_wr_bst_act : out std_logic;

--//------------------------

--// SDRAM memory signals --

--//------------------------

--// SDRAM controller ready

sdram_rdy : out std_logic;

--// SDRAM chip select

sdram_cs_n : out std_logic;

--// SDRAM row address strobe

sdram_ras_n : out std_logic;

--// SDRAM column address strobe

sdram_cas_n : out std_logic;

--// SDRAM write enable

sdram_we_n : out std_logic;

--// SDRAM DQ masks

sdram_dqm_n : out std_logic_vector(1 downto 0);

--// SDRAM bank address

sdram_ba : out std_logic_vector(1 downto 0);

--// SDRAM address

sdram_addr : out std_logic_vector(11 downto 0);

--// SDRAM data

sdram_dq_oe : out std_logic;

sdram_dq_o : out std_logic_vector(15 downto 0);

sdram_dq_i : in std_logic_vector(15 downto 0)

);

END COMPONENT;

signal AUDIO_L_PCM : std_logic_vector(15 downto 0);

signal AUDIO_R_PCM : std_logic_vector(15 downto 0);

signal VIDEO_VS : std_logic;

signal VIDEO_HS : std_logic;

signal VIDEO_R : std_logic_vector(7 downto 0);

signal VIDEO_G : std_logic_vector(7 downto 0);

signal VIDEO_B : std_logic_vector(7 downto 0);

signal VIDEO_BLANK : std_logic;

signal VIDEO_BURST : std_logic;

signal VIDEO_START_OF_FIELD : std_logic;

signal VIDEO_ODD_LINE : std_logic;

signal PAL : std_logic;

signal JOY1_IN_n : std_logic_vector(4 downto 0);

signal JOY2_IN_n : std_logic_vector(4 downto 0);

signal PLL1_LOCKED : std_logic;

signal CLK_PLL1 : std_logic;

signal RESET_n : std_logic;

signal PLL_LOCKED : std_logic;

signal CLK : std_logic;

signal CLK_SDRAM : std_logic;

-- SDRAM

signal SDRAM_REQUEST : std_logic;

signal SDRAM_REQUEST_COMPLETE : std_logic;

signal SDRAM_READ_ENABLE : STD_LOGIC;

signal SDRAM_WRITE_ENABLE : std_logic;

signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);

SIGNAL SDRAM_DI : std_logic_vector(31 downto 0);

SIGNAL SDRAM_WIDTH_32BIT_ACCESS : std_logic;

SIGNAL SDRAM_WIDTH_16BIT_ACCESS : std_logic;

SIGNAL SDRAM_WIDTH_8BIT_ACCESS : std_logic;

signal SDRAM_REFRESH : std_logic;

signal SYSTEM_RESET_REQUEST: std_logic;

signal seq_reg : std_logic_vector(11 downto 0);

signal seq_next : std_logic_vector(11 downto 0);

signal seq_ph_reg : std_logic;

signal seq_ph_next : std_logic;

signal ref_reg : std_logic;

signal ref_next : std_logic;

signal sdram_request_complete_next : std_logic;

signal sdram_request_complete_reg : std_logic;

signal sdram_request_next : std_logic;

signal sdram_request_reg : std_logic;

signal ram_di_next : std_logic_vector(15 downto 0);

signal ram_di_reg : std_logic_vector(15 downto 0);

signal ram_do_next : std_logic_vector(31 downto 0);

signal ram_do_reg : std_logic_vector(31 downto 0);

signal ram_do : std_logic_vector(15 downto 0);

signal ram_bena_next : std_logic_vector(1 downto 0);

signal ram_bena_reg : std_logic_vector(1 downto 0);

signal ram_rd_active : std_logic;

signal ram_wr_active : std_logic;

signal sdram_dq_oe : std_logic;

signal sdram_dq_o : std_logic_vector(15 downto 0);

signal sdram_dq_i : std_logic_vector(15 downto 0);

signal sdram_dqm_n_temp : std_logic_vector(1 downto 0);

signal sdram_rdy : std_logic;

signal sdram_reset_ctrl_n_next : std_logic;

signal sdram_reset_ctrl_n_reg : std_logic;

signal sdram_reset_n_next : std_logic;

signal sdram_reset_n_reg : std_logic;

-- pokey keyboard

SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);

SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);

-- gtia consol keys

SIGNAL CONSOL_START : std_logic;

SIGNAL CONSOL_SELECT : std_logic;

SIGNAL CONSOL_OPTION : std_logic;

SIGNAL FKEYS : std_logic_vector(11 downto 0);

-- svideo

signal svideo_dac_clk : std_logic;

signal svideo_y : std_logic_vector(7 downto 0);

signal svideo_c : std_logic_vector(5 downto 0);

-- composite

SIGNAL svideo_yout : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL svideo_yout_dly1 : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL svideo_yout_dly2 : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL svideo_yout_dly3 : STD_LOGIC_VECTOR(7 DOWNTO 0);

--SIGNAL svideo_cout : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL cvbs1_out : STD_LOGIC_VECTOR(9 DOWNTO 0);

SIGNAL cvbs2_out : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL luma : STD_LOGIC_VECTOR(9 DOWNTO 0);

SIGNAL chroma : STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL luma_saturated : STD_LOGIC_VECTOR(9 DOWNTO 0);

-- dma/virtual drive

signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);

signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);

signal DMA_FETCH : std_logic;

signal DMA_32BIT_WRITE_ENABLE : std_logic;

signal DMA_16BIT_WRITE_ENABLE : std_logic;

signal DMA_8BIT_WRITE_ENABLE : std_logic;

signal DMA_READ_ENABLE : std_logic;

signal DMA_MEMORY_READY : std_logic;

signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);

signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);

signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);

signal ZPU_OUT1 : std_logic_vector(31 downto 0);

signal ZPU_OUT2 : std_logic_vector(31 downto 0);

signal ZPU_OUT3 : std_logic_vector(31 downto 0);

signal ZPU_OUT4 : std_logic_vector(31 downto 0);

signal zpu_pokey_enable : std_logic;

signal zpu_sio_txd : std_logic;

signal zpu_sio_rxd : std_logic;

signal zpu_sio_command : std_logic;

-- system control from zpu

signal ram_select : std_logic_vector(2 downto 0);

signal rom_select : std_logic_vector(5 downto 0);

signal reset_atari : std_logic;

signal pause_atari : std_logic;

SIGNAL speed_6502 : std_logic_vector(5 downto 0);

-- USB joystick

SIGNAL joyright1_2 : STD_LOGIC := '1';

SIGNAL joyright1_4 : STD_LOGIC := '1';

SIGNAL joyright1_3 : STD_LOGIC := '1';

SIGNAL joyright1_1 : STD_LOGIC := '1';

SIGNAL joy1_start_fire : STD_LOGIC := '1';

SIGNAL joyright1_r2 : STD_LOGIC := '1';

SIGNAL joyright1_r1 : STD_LOGIC := '1';

-- joystick 1 left side

SIGNAL joyleft1_arrow_right : STD_LOGIC := '1';

SIGNAL joyleft1_arrow_left : STD_LOGIC := '1';

SIGNAL joyleft1_arrow_down : STD_LOGIC := '1';

SIGNAL joyleft1_arrow_up : STD_LOGIC := '1';

SIGNAL joy1_select_fire : STD_LOGIC := '1';

SIGNAL joyleft1_l2 : STD_LOGIC := '1';

SIGNAL joyleft1_l1 : STD_LOGIC := '1';

SIGNAL joyright2_2 : STD_LOGIC := '1';

SIGNAL joyright2_4 : STD_LOGIC := '1';

SIGNAL joyright2_3 : STD_LOGIC := '1';

SIGNAL joyright2_1 : STD_LOGIC := '1';

SIGNAL joy2_start_fire : STD_LOGIC := '1';

SIGNAL joyright2_r2 : STD_LOGIC := '1';

SIGNAL joyright2_r1 : STD_LOGIC := '1';

-- joystick 1 left side

SIGNAL joyleft2_arrow_right : STD_LOGIC := '1';

SIGNAL joyleft2_arrow_left : STD_LOGIC := '1';

SIGNAL joyleft2_arrow_down : STD_LOGIC := '1';

SIGNAL joyleft2_arrow_up : STD_LOGIC := '1';

SIGNAL joy2_select_fire : STD_LOGIC := '1';

SIGNAL joyleft2_l2 : STD_LOGIC := '1';

SIGNAL joyleft2_l1 : STD_LOGIC := '1';

signal joyleft1_dummy : std_logic;

signal joyright1_dummy : std_logic;

signal joyleft2_dummy : std_logic;

signal joyright2_dummy : std_logic;

SIGNAL reset_usbdrv : STD_LOGIC := '0';

SIGNAL cntr_reset : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111";

signal usb_clk : std_logic;

signal usb_reset_n : std_logic;

BEGIN

-- disable flash (not used)

CFG_CLK <= 'Z';

CFG_CS_n <= '1';

CFG_DOUT <= 'Z';

-- disable usb

--dplus1 <= 'Z';

--dminus1 <= 'Z';

--dplus2 <= 'Z';

--dminus2 <= 'Z';

dac_left : hq_dac

port map

(

reset => not(reset_n),

clk => clk,

clk_ena => '1',

pcm_in => AUDIO_L_PCM&"0000",

dac_out => audio_l

);

dac_right : hq_dac

port map

(

reset => not(reset_n),

clk => clk,

clk_ena => '1',

pcm_in => AUDIO_R_PCM&"0000",

dac_out => audio_r

);

gen_fake_pll : if ext_clock=1 generate

CLK_SDRAM <= EXT_CLK_SDRAM(1);

CLK <= EXT_CLK(1);

SDRAM_CLK <= EXT_CLK_SDRAM(1);

SVIDEO_DAC_CLK <= EXT_SVIDEO_DAC_CLK(1);

--SCANDOUBLE_CLK <= EXT_SCANDOUBLE_CLK(1);

PLL_LOCKED <= EXT_PLL_LOCKED(1);

end generate;

gen_real_pll : if ext_clock=0 generate

gen_tv_pal : if tv=1 generate

mcc_pll : entity work.pal_pll

PORT MAP(inclk0 => FPGA_CLK,

c0 => CLK_PLL1,

locked => PLL1_LOCKED);

mcc_pll2 : entity work.pll_downstream_pal

PORT MAP(inclk0 => CLK_PLL1,

c0 => CLK_SDRAM,

c1 => CLK,

c2 => SDRAM_CLK,

c3 => SVIDEO_DAC_CLK,

c4 => open, --SCANDOUBLE_CLK,

areset => not(PLL1_LOCKED),

locked => PLL_LOCKED);

end generate;

gen_tv_ntsc : if tv=0 generate

mcc_pll : entity work.ntsc_pll

PORT MAP(inclk0 => FPGA_CLK,

c0 => CLK_PLL1,

locked => PLL1_LOCKED);

mcc_pll2 : entity work.pll_downstream_ntsc

PORT MAP(inclk0 => CLK_PLL1,

c0 => CLK_SDRAM,

c1 => CLK,

c2 => SDRAM_CLK,

c3 => SVIDEO_DAC_CLK,

c4 => open, --SCANDOUBLE_CLK,

areset => not(PLL1_LOCKED),

locked => PLL_LOCKED);

end generate;

end generate;

reset_n <= PLL_LOCKED;

-- Keyboard (will be USB I hope, though component does not appear to support it...)

--CONSOL_START <= '0';

--CONSOL_SELECT <= '0';

--CONSOL_OPTION <= '0';

--FKEYS <= (others=>'0');

KEYBOARD_RESPONSE <= (others=>'1');

PAL <= '1' when TV=1 else '0';

atarixl_simple_sdram1 : entity work.atari800core_simple_sdram

GENERIC MAP

(

cycle_length => 16,

internal_rom => 0, --internal_rom,

internal_ram => 0, --internal_ram,

video_bits => 8,

palette => 1

)

PORT MAP

(

CLK => CLK,

--RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),

RESET_N => RESET_N and SDRAM_RESET_N_REG,

VIDEO_VS => VIDEO_VS,

VIDEO_HS => VIDEO_HS,

VIDEO_B => VIDEO_B,

VIDEO_G => VIDEO_G,

VIDEO_R => VIDEO_R,

VIDEO_BLANK =>VIDEO_BLANK,

VIDEO_BURST =>VIDEO_BURST,

VIDEO_START_OF_FIELD =>VIDEO_START_OF_FIELD,

VIDEO_ODD_LINE =>VIDEO_ODD_LINE,

AUDIO_L => AUDIO_L_PCM,

AUDIO_R => AUDIO_R_PCM,

JOY1_n => JOY1_IN_n,

JOY2_n => JOY2_IN_n,

KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,

KEYBOARD_SCAN => KEYBOARD_SCAN,

SIO_COMMAND => zpu_sio_command,

SIO_RXD => zpu_sio_txd,

SIO_TXD => zpu_sio_rxd,

CONSOL_OPTION => CONSOL_OPTION,

CONSOL_SELECT => CONSOL_SELECT,

CONSOL_START => CONSOL_START,

SDRAM_REQUEST => SDRAM_REQUEST,

SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,

SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,

SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,

SDRAM_ADDR => SDRAM_ADDR,

SDRAM_DO => ram_do_reg,

SDRAM_DI => SDRAM_DI,

SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,

SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,

SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,

SDRAM_REFRESH => SDRAM_REFRESH,

DMA_FETCH => dma_fetch,

DMA_READ_ENABLE => dma_read_enable,

DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,

DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,

DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,

DMA_ADDR => dma_addr_fetch,

DMA_WRITE_DATA => dma_write_data,

MEMORY_READY_DMA => dma_memory_ready,

DMA_MEMORY_DATA => dma_memory_data,

RAM_SELECT => ram_select,

ROM_SELECT => rom_select,

PAL => PAL,

HALT => pause_atari,

THROTTLE_COUNT_6502 => speed_6502

);

process(clk_sdram,sdram_reset_ctrl_n_reg)

begin

if (sdram_reset_ctrl_n_reg='0') then

seq_reg <= "100000000000";

seq_ph_reg <= '1';

ref_reg <= '0';

ram_do_reg <= (others=>'0');

ram_di_reg <= (others=>'0');

ram_bena_reg <= (others=>'0');

sdram_request_complete_reg <= '0';

sdram_request_reg <= '0';

elsif (clk_sdram'event and clk_sdram = '1') then

seq_reg <= seq_next;

seq_ph_reg <= seq_ph_next;

ref_reg <= ref_next;

ram_do_reg <= ram_do_next;

ram_di_reg <= ram_di_next;

ram_bena_reg <= ram_bena_next;

sdram_request_complete_reg <= sdram_request_complete_next;

sdram_request_reg <= sdram_request_next;

end if;

end process;

process(clk,reset_n)

begin

if (reset_n='0') then

sdram_reset_n_reg <= '0';

sdram_reset_ctrl_n_reg <= '0';

elsif (clk'event and clk = '1') then

sdram_reset_n_reg <= sdram_reset_n_next;

sdram_reset_ctrl_n_reg <= reset_n;

end if;

end process;

-- Generate sdram sequence

process(seq_reg, seq_ph_reg, ref_reg)

begin

seq_next <= seq_reg(10 downto 0)&seq_reg(11);

seq_ph_next <= seq_ph_reg;

ref_next <= ref_reg;

if (seq_reg(11) = '1') then

seq_ph_next <= not(seq_ph_reg);

ref_next <= not(ref_reg);

end if;

end process;

process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)

begin

sdram_reset_n_next <= sdram_reset_n_reg;

if (sdram_rdy = '1' and seq_next(8)='1' and seq_reg(8)='0') then

sdram_reset_n_next <= '1';

end if;

if (reset_atari = '1') then

sdram_reset_n_next <= '0';

end if;

end process;

-- Adapt SDRAM

process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)

begin

sdram_request_next <= sdram_request_reg or sdram_request;

sdram_request_complete_next <= sdram_request_complete_reg;

ram_bena_next <= "00";

ram_di_next <= (others=>'0');

ram_do_next <= ram_do_reg;

case seq_reg is

when "000000000001" =>

-- nop

when "000000000010" => -- write data from next...

if (SDRAM_WRITE_ENABLE = '1') then

if (SDRAM_WIDTH_8BIT_ACCESS = '1') then

ram_di_next <= SDRAM_DI(7 downto 0)&SDRAM_DI(7 downto 0);

ram_bena_next <= SDRAM_ADDR(0)&not(SDRAM_ADDR(0));

else

ram_di_next <= SDRAM_DI(15 downto 0);

ram_bena_next <= "11";

end if;

end if;

when "000000000100" =>

if (SDRAM_WRITE_ENABLE = '1') then

if (SDRAM_WIDTH_8BIT_ACCESS = '1') then

ram_di_next <= (others=>'0');

else

ram_di_next <= SDRAM_DI(31 downto 16);

ram_bena_next <= "11";

end if;

end if;

if ((ram_wr_active)='1') then

sdram_request_complete_next <= '1';

sdram_request_next <= '0';

end if;

when "000000001000" =>

-- nop

when "000000010000" =>

sdram_request_complete_next <= '0';

-- nop

when "000000100000" =>

-- nop

when "000001000000" =>

if (SDRAM_READ_ENABLE = '1') then

if (SDRAM_WIDTH_8BIT_ACCESS = '1') then

if (SDRAM_ADDR(0) = '0') then

ram_do_next(15 downto 0) <= ram_do(7 downto 0)&ram_do(7 downto 0);

else

ram_do_next(15 downto 0) <= ram_do(15 downto 8)&ram_do(15 downto 8);

end if;

else

ram_do_next(15 downto 0) <= ram_do;

end if;

end if;

when "000010000000" =>

if (SDRAM_READ_ENABLE = '1') then

if (SDRAM_WIDTH_8BIT_ACCESS = '1') then

ram_do_next(31 downto 16) <= (others=>'0');

else

ram_do_next(31 downto 16) <= ram_do;

end if;

end if;

if ((ram_rd_active)='1') then

sdram_request_complete_next <= '1';

sdram_request_next <= '0';

end if;

when "000100000000" =>

-- nop

when "001000000000" =>

-- nop

when "010000000000" =>

sdram_request_complete_next <= '0';

-- nop

when "100000000000" =>

-- nop

when others =>

-- never

end case;

end process;

SDRAM_REQUEST_COMPLETE <= SDRAM_REQUEST_COMPLETE_REG;

sdram_controller : sdram_ctrl

PORT MAP

(

CLK => CLK_SDRAM,

rst => not(sdram_reset_ctrl_n_reg),

seq_cyc => seq_reg(11 downto 0),

seq_ph => seq_ph_reg,

--refr_cyc => ref_reg,

refr_cyc => SDRAM_REFRESH,

ap1_ram_sel => SDRAM_REQUEST_NEXT,

ap1_address => '0'&SDRAM_ADDR(22 downto 1),

ap1_rden => SDRAM_READ_ENABLE,

ap1_wren => SDRAM_WRITE_ENABLE,

ap1_bena => ram_bena_reg,

ap1_rddata => ram_do,

ap1_wrdata => ram_di_reg,

ap1_bst_siz => "001",

ap1_rd_bst_act => ram_rd_active,

ap1_wr_bst_act => ram_wr_active,

ap2_ram_sel => '0',

ap2_address => "00000000000000000000000",

ap2_rden => '0',

ap2_wren => '0',

ap2_bena => "11",

ap2_rddata => open,

ap2_wrdata => X"0000",

ap2_bst_siz => "111",

ap2_rd_bst_act => open,

ap2_wr_bst_act => open,

ap3_ram_sel => '0',

ap3_address => "00000000000000000000000",

ap3_rden => '0',

ap3_wren => '0',

ap3_bena => "11",

ap3_rddata => open,

ap3_wrdata => X"0000",

ap3_bst_siz => "111",