Index: mcctv/pll_downstream_ntsc.qip
===================================================================
--- mcctv/pll_downstream_ntsc.qip	(nonexistent)
+++ mcctv/pll_downstream_ntsc.qip	(revision 181)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.ppf"]
Index: mcctv/pll_downstream_pal.cmp
===================================================================
--- mcctv/pll_downstream_pal.cmp	(nonexistent)
+++ mcctv/pll_downstream_pal.cmp	(revision 181)
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_downstream_pal
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcctv/pll_downstream_pal.qip
===================================================================
--- mcctv/pll_downstream_pal.qip	(nonexistent)
+++ mcctv/pll_downstream_pal.qip	(revision 181)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_downstream_pal.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_pal.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_pal.ppf"]
Index: mcctv/pll_usb.cmp
===================================================================
--- mcctv/pll_usb.cmp	(nonexistent)
+++ mcctv/pll_usb.cmp	(revision 181)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_usb
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcctv/pll_usb.qip
===================================================================
--- mcctv/pll_usb.qip	(nonexistent)
+++ mcctv/pll_usb.qip	(revision 181)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_usb.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_usb.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_usb.ppf"]
Index: mcctv/sdram_clock_sync.wcfg
===================================================================
--- mcctv/sdram_clock_sync.wcfg	(nonexistent)
+++ mcctv/sdram_clock_sync.wcfg	(revision 181)
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="26" />
+   <wvobject fp_name="/atari800core_mcc_tb/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/clk_two" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_two</obj_property>
+      <obj_property name="ObjectShortName">clk_two</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/clk_three" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_three</obj_property>
+      <obj_property name="ObjectShortName">clk_three</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/clk_four" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_four</obj_property>
+      <obj_property name="ObjectShortName">clk_four</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/enable_179" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enable_179</obj_property>
+      <obj_property name="ObjectShortName">enable_179</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/sdram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request</obj_property>
+      <obj_property name="ObjectShortName">sdram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_complete_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/seq_ph_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_ph_reg</obj_property>
+      <obj_property name="ObjectShortName">seq_ph_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/seq_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/throttle_count_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">throttle_count_reg[5:0]</obj_property>
+      <obj_property name="ObjectShortName">throttle_count_reg[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_ras_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ras_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_ras_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_cas_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cas_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cas_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_we_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_we_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_we_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/memory_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">memory_ready</obj_property>
+      <obj_property name="ObjectShortName">memory_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/r_psel" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_psel[2:0]</obj_property>
+      <obj_property name="ObjectShortName">r_psel[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/r_psel_dly" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_psel_dly[2:0]</obj_property>
+      <obj_property name="ObjectShortName">r_psel_dly[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_reset_n_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_reset_n_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_reset_n_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_reset_n_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_rdy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_rdy</obj_property>
+      <obj_property name="ObjectShortName">sdram_rdy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_refresh" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_refresh</obj_property>
+      <obj_property name="ObjectShortName">sdram_refresh</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv/sdram_ctrl_3_ports.wcfg
===================================================================
--- mcctv/sdram_ctrl_3_ports.wcfg	(nonexistent)
+++ mcctv/sdram_ctrl_3_ports.wcfg	(revision 181)
@@ -0,0 +1,130 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="sdram_ctrl_3_ports.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="numeric_std" />
+            <top_module name="sdram_ctrl_3_ports_tb" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="24" />
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/clk_a" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_a</obj_property>
+      <obj_property name="ObjectShortName">clk_a</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_rdy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_rdy</obj_property>
+      <obj_property name="ObjectShortName">sdram_rdy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_cs_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cs_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cs_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_ras_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ras_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_ras_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_cas_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cas_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cas_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_we_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_we_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_we_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dqm_n" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_ba" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_addr[11:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_addr[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dq_oe" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq_oe</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq_oe</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dq_o" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq_o[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq_o[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dq_i" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq_i[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq_i[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/seq_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/seq_ph_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_ph_reg</obj_property>
+      <obj_property name="ObjectShortName">seq_ph_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_rd_active" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_rd_active[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_rd_active[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_wr_active" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_wr_active[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_wr_active[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ref_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ref_reg</obj_property>
+      <obj_property name="ObjectShortName">ref_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_controller/r_refr_req" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">r_refr_req</obj_property>
+      <obj_property name="ObjectShortName">r_refr_req</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_controller/r_psel" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_psel[2:0]</obj_property>
+      <obj_property name="ObjectShortName">r_psel[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_di" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_di[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_di[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_di2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_di2[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_di2[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_do" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_do[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_do[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#0000ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_do2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_do2[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_do2[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#0000ff</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv/spi_dma.wcfg
===================================================================
--- mcctv/spi_dma.wcfg	(nonexistent)
+++ mcctv/spi_dma.wcfg	(revision 181)
@@ -0,0 +1,176 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+            <top_module name="zpupkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="33" />
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/cpu_data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/wr_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">wr_en</obj_property>
+      <obj_property name="ObjectShortName">wr_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">addr[4:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[4:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.b_inst" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">.b_inst</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.b_inst</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.opcode" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.opcode</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.opcode</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.pc" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.pc</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.pc</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.sp" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.sp</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.sp</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_a</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_a</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_b" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_b</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_b</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_addr[15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_write</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_write_bits" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_write_bits[3:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_write_bits[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_stack_write" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_stack_write[3:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_stack_write[3:0]</obj_property>
+      <obj_property name="Radix">BINARYRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_do" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_do[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_do[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_addr_rom_ram" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_rom_ram[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_rom_ram[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_stack_write_dma" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_stack_write_dma[3:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_stack_write_dma[3:0]</obj_property>
+      <obj_property name="Radix">BINARYRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_do_dma" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_do_dma[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_do_dma[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_addr_rom_ram_dma" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_rom_ram_dma[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_rom_ram_dma[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/paused_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">paused_reg</obj_property>
+      <obj_property name="ObjectShortName">paused_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_dma_addr_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_dma_addr_reg[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_dma_addr_reg[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_dma_addrend_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_dma_addrend_reg[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_dma_addrend_reg[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_dma_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_dma_reg</obj_property>
+      <obj_property name="ObjectShortName">spi_dma_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sd_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_write</obj_property>
+      <obj_property name="ObjectShortName">sd_write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sd_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sd_addr[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_clk</obj_property>
+      <obj_property name="ObjectShortName">sdcard_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_cmd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_cmd</obj_property>
+      <obj_property name="ObjectShortName">sdcard_cmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_dat" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_dat</obj_property>
+      <obj_property name="ObjectShortName">sdcard_dat</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_dat3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_dat3</obj_property>
+      <obj_property name="ObjectShortName">sdcard_dat3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/rx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/ram_7_0/data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/zpu_8bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_8bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_8bit_write_enable</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv/svideo/sin_rom.qip
===================================================================
--- mcctv/svideo/sin_rom.qip	(nonexistent)
+++ mcctv/svideo/sin_rom.qip	(revision 181)
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "9.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sin_rom.vhd"]
Index: mcctv/pll_usb.vhd
===================================================================
--- mcctv/pll_usb.vhd	(nonexistent)
+++ mcctv/pll_usb.vhd	(revision 181)
@@ -0,0 +1,360 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_usb.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_usb IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_usb;
+
+
+ARCHITECTURE SYN OF pll_usb IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	locked    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 3,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone IV E",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_usb",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "15.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "15.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_usb.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcctv/sdram_ctrl_3_ports.cmd
===================================================================
--- mcctv/sdram_ctrl_3_ports.cmd	(nonexistent)
+++ mcctv/sdram_ctrl_3_ports.cmd	(revision 181)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: mcctv/sdram_ctrl_4_ports.v
===================================================================
--- mcctv/sdram_ctrl_4_ports.v	(nonexistent)
+++ mcctv/sdram_ctrl_4_ports.v	(revision 181)
@@ -0,0 +1,561 @@
+`timescale 1 ns / 1 ps
+
+module sdram_ctrl /* verilator tracing_off */
+(
+    //-----------------------------
+    // Clock and reset
+    //-----------------------------
+    input         rst,             // Global reset
+    input         clk,             // Master clock (72 MHz)
+    	 
+    output        ram_rdy_n,       // SDRAM ready
+    output        ram_ref,         // SDRAM refresh
+    output  [3:0] ram_cyc,         // SDRAM cycles
+    output  [3:0] ram_ph,          // SDRAM phases
+    output  [8:0] ram_ph_ctr,      // Phase counter
+    
+    //-----------------------------
+    // Access bank #0
+    //-----------------------------
+    input         rden_b0,         // Read enable
+    input         wren_b0,         // Write enable
+    input  [22:2] addr_b0,         // Address (up to 8 MB)
+    output        valid_b0,        // Read data valid
+    output        fetch_b0,        // Write data fetch
+    output [15:0] rdata_b0,        // Read data
+    input  [15:0] wdata_b0,        // Write data
+    input   [1:0] bena_b0,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #1
+    //-----------------------------
+    input         rden_b1,         // Read enable
+    input         wren_b1,         // Write enable
+    input  [22:2] addr_b1,         // Address (up to 8 MB)
+    output        valid_b1,        // Read data valid
+    output        fetch_b1,        // Write data fetch
+    output [15:0] rdata_b1,        // Read data
+    input  [15:0] wdata_b1,        // Write data
+    input   [1:0] bena_b1,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #2
+    //-----------------------------
+    input         rden_b2,         // Read enable
+    input         wren_b2,         // Write enable
+    input  [22:2] addr_b2,         // Address (up to 8 MB)
+    output        valid_b2,        // Read data valid
+    output        fetch_b2,        // Write data fetch
+    output [15:0] rdata_b2,        // Read data
+    input  [15:0] wdata_b2,        // Write data
+    input   [1:0] bena_b2,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #3
+    //-----------------------------
+    input         rden_b3,         // Read enable
+    input         wren_b3,         // Write enable
+    input  [22:2] addr_b3,         // Address (up to 8 MB)
+    output        valid_b3,        // Read data valid
+    output        fetch_b3,        // Write data fetch
+    output [15:0] rdata_b3,        // Read data
+    input  [15:0] wdata_b3,        // Write data
+    input   [1:0] bena_b3,         // Byte enable
+    
+    //-----------------------------
+    // SDRAM memory signals
+    //-----------------------------
+    output            sdram_cs_n,  // SDRAM chip select
+    output reg        sdram_ras_n, // SDRAM row address strobe
+    output reg        sdram_cas_n, // SDRAM column address strobe
+    output reg        sdram_we_n,  // SDRAM write enable
+    //
+    output reg  [1:0] sdram_ba,    // SDRAM bank address
+    output reg [12:0] sdram_addr,  // SDRAM address
+    //
+    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+    output reg        sdram_dq_oe, // SDRAM data output enable
+    output reg [31:0] sdram_dq_o,  // SDRAM data output
+    input      [31:0] sdram_dq_i   // SDRAM data input
+);
+    // SDRAM memory size (16 or 32 MB)
+    parameter SDRAM_SIZE  = 16;
+    // SDRAM memory width (16 or 32 bits)
+    parameter SDRAM_WIDTH = 16;
+    // Clock-to-output delay (for simulation)
+    parameter Tco_dly = 4.5;
+    // SDRAM commands
+    localparam [2:0]
+        CMD_LMR = 3'b000,
+        CMD_REF = 3'b001,
+        CMD_PRE = 3'b010,
+        CMD_ACT = 3'b011,
+        CMD_WR  = 3'b100,
+        CMD_RD  = 3'b101,
+        CMD_BST = 3'b110,
+        CMD_NOP = 3'b111;
+        
+    // ======================================================
+    // SDRAM sequencer control
+    // ======================================================
+    
+    reg [3:0] r_ram_cyc;
+    reg [3:0] r_ram_ph;
+    reg [1:0] r_ba0_ctr;
+    reg [1:0] r_ba1_ctr;
+    reg [8:0] r_ph_ctr;
+    reg [2:0] r_ini_ctr;
+    reg       r_ref_ena;
+    wire      w_bus_eol;
+    
+    assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
+    
+    always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
+        
+        if (rst) begin
+            r_ram_cyc <= 4'b1000;
+            r_ram_ph  <= 4'b1000;
+            r_ba0_ctr <= 2'd0;
+            r_ba1_ctr <= 2'd3;
+            r_ph_ctr  <= 9'd3;
+            r_ini_ctr <= 3'd0;
+            r_ref_ena <= 1'b0;
+        end
+        else begin
+            r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
+            if (r_ram_cyc[3]) begin
+                r_ram_ph  <= { r_ram_ph[2:0], r_ram_ph[3] };
+                r_ba0_ctr <= r_ba0_ctr + 2'd1;
+                r_ba1_ctr <= r_ba1_ctr + 2'd1;
+                // Phase counter : 3 - 288
+                if (r_ram_ph[3]) begin
+                    r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
+                end
+                // Initialization done after 4 scanlines
+                if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
+                    r_ini_ctr <= r_ini_ctr + 3'd1;
+                // Refreshes are enabled during phase 284 - 288
+					 //r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+                r_ref_ena <= r_ram_ph[1]; // r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+            end
+        end
+    end
+    
+    assign ram_ref    = r_ref_ena;
+    assign ram_cyc    = r_ram_cyc;
+    assign ram_ph     = r_ram_ph;
+    assign ram_ph_ctr = r_ph_ctr;
+    assign ram_rdy_n  = ~r_ini_ctr[2];
+    
+    // ======================================================
+    // SDRAM phase generation
+    // ======================================================
+    
+    reg [3:0] r_rd_act;
+    reg [3:0] r_wr_act;
+    
+    reg       r_act_ph; // Activate phase
+    reg       r_rd_ph;  // Burst read phase
+    reg       r_wr_ph;  // Burst write phase
+    reg       r_ref_ph; // Auto-refresh phase
+    reg [3:0] r_ini_ph; // Initialization phases
+    reg       r_pre_ph; // Precharge phase
+    reg       r_lmr_ph; // Load mode register phase
+    
+    always@(posedge rst or posedge clk) begin : PHASE_GEN
+    
+        if (rst) begin
+            r_rd_act <= 4'b0000;
+            r_wr_act <= 4'b0000;
+            
+            r_act_ph <= 1'b0;
+            r_rd_ph  <= 1'b0;
+            r_wr_ph  <= 1'b0;
+            r_ref_ph <= 1'b0;
+            r_ini_ph <= 4'b0000;
+            r_pre_ph <= 1'b0;
+            r_lmr_ph <= 1'b0;
+        end
+        else begin
+            if (r_ram_cyc[0]) begin
+                // Access port #0 read/write
+                if (r_ram_ph[0]) begin
+                    r_rd_act[0] <= rden_b0 & ~r_ref_ena;
+                    r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
+                end
+                else if (r_ram_ph[2]) begin
+                    r_rd_act[0] <= 1'b0;
+                    r_wr_act[0] <= 1'b0;
+                end
+                // Access port #1 read/write
+                if (r_ram_ph[1]) begin
+                    r_rd_act[1] <= rden_b1 & ~r_ref_ena;
+                    r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
+                end
+                else if (r_ram_ph[3]) begin
+                    r_rd_act[1] <= 1'b0;
+                    r_wr_act[1] <= 1'b0;
+                end
+                // Access port #2 read/write
+                if (r_ram_ph[2]) begin
+                    r_rd_act[2] <= rden_b2 & ~r_ref_ena;
+                    r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
+                end
+                else if (r_ram_ph[0]) begin
+                    r_rd_act[2] <= 1'b0;
+                    r_wr_act[2] <= 1'b0;
+                end
+                // Access port #3 read/write
+                if (r_ram_ph[3]) begin
+                    r_rd_act[3] <= rden_b3 & ~r_ref_ena;
+                    r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
+                end
+                else if (r_ram_ph[1]) begin
+                    r_rd_act[3] <= 1'b0;
+                    r_wr_act[3] <= 1'b0;
+                end
+            end
+            
+            if (r_ram_cyc[0] & r_ini_ctr[2]) begin
+                // Activate phase
+                r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
+                          | (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
+                          | (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
+                          | (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
+            end
+            
+            if (r_ram_cyc[3] & r_ini_ctr[2]) begin
+                // Read phase
+                r_rd_ph  <= (r_ram_ph[0] & r_rd_act[0])
+                          | (r_ram_ph[1] & r_rd_act[1])
+                          | (r_ram_ph[2] & r_rd_act[2])
+                          | (r_ram_ph[3] & r_rd_act[3]);
+                // Write phase
+                r_wr_ph  <= (r_ram_ph[0] & r_wr_act[0])
+                          | (r_ram_ph[1] & r_wr_act[1])
+                          | (r_ram_ph[2] & r_wr_act[2])
+                          | (r_ram_ph[3] & r_wr_act[3]);
+            end
+
+            // Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
+            if (r_ram_cyc[3] & r_ram_ph[2]) begin
+                if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
+                    r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
+                end
+                else begin
+                    r_ini_ph <= 4'b0000;
+                end
+            end
+            
+            // Precharge phase
+            r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
+            
+            // Refresh phase
+            //r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
+            //          | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            r_ref_ph <= r_ref_ena & r_ini_ctr[2] // Normal
+                      | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            
+            // Load mode register phase
+            r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
+            
+        end
+    end
+    
+    // ======================================================
+    // SDRAM address generation
+    // ======================================================
+    
+    reg  [22:2] r_addr_mux;
+    reg  [10:2] r_addr_col;
+    reg  [12:0] r_addr_sdr;
+    reg   [1:0] r_ba_sdr;
+
+    always@(posedge rst or posedge clk) begin : ADDRESS_GEN
+    
+        if (rst) begin
+            r_addr_mux <= 21'd0;
+            r_addr_col <= 9'd0;
+            r_addr_sdr <= 13'd0;
+            r_ba_sdr   <= 2'b00;
+        end
+        else begin
+            // Port address multiplexer
+            if (r_ram_cyc[0]) begin
+                r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
+                            | addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
+                            | addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
+                            | addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
+            end
+
+            // Column address (for read/write op.)
+            if (r_ram_cyc[3]) begin
+                r_addr_col <= r_addr_mux[10:2];
+            end
+            
+            // Memories layouts :
+            // ------------------
+            // SDRAM  4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
+            // SDRAM  8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
+            // SDRAM  8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
+            // SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
+    
+            // Row / col address
+            if (SDRAM_WIDTH == 32) begin
+                // 32-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000,  r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,     r_addr_mux[22:11]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010,  r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010,  r_addr_col[10: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  256 cols
+                                | { 1'b0,     r_addr_mux[21:10]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  256 cols
+                                | { 5'b00100, r_addr_col[ 9: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  256 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+            end
+            else begin
+                // 16-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                |            r_addr_mux[22:10]        & {13{r_act_ph & r_ram_cyc[1]}}  // 8192 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,    r_addr_mux[21:10]      } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b0_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+            end
+            
+            // Bank address
+            r_ba_sdr   <= r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[0]}}  // 32-bit read
+                        | r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}}  // Activate
+                        | r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[2]}}  // 32-bit read with auto-precharge
+                        | r_ba1_ctr & {2{r_wr_ph  & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
+        end
+    end
+    
+    // ======================================================
+    // SDRAM command generation
+    // ======================================================
+    
+    reg  [2:0] r_cmd_sdr;
+        
+    always@(posedge rst or posedge clk) begin : COMMAND_GEN
+        reg [2:0] v_cmd_0;
+        reg [2:0] v_cmd_1;
+        reg [2:0] v_cmd_2;
+        reg [2:0] v_cmd_3;
+        reg [2:0] v_cmd_4;
+        reg [2:0] v_cmd_5;
+        reg [2:0] v_cmd_6;
+    
+        if (rst) begin
+            r_cmd_sdr <= CMD_NOP;
+        end
+        else begin
+            v_cmd_0 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
+            v_cmd_2 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_3 = CMD_WR  | {3{~r_wr_ph }};
+            v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
+            v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
+            v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
+            
+            r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
+                       & (v_cmd_1 | {3{~r_ram_cyc[1]}})
+                       & (v_cmd_2 | {3{~r_ram_cyc[2]}})
+                       & (v_cmd_3 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_4 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_5 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_6 | {3{~r_ram_cyc[3]}});
+        end
+    end
+    
+    assign sdram_cs_n  = 1'b0;
+    
+    // Command and address
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
+    always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
+    always@(*) sdram_we_n  = #Tco_dly r_cmd_sdr[0];
+    always@(*) sdram_ba    = #Tco_dly r_ba_sdr;
+    always@(*) sdram_addr  = #Tco_dly r_addr_sdr;
+    /* verilator lint_on STMTDLY */
+    
+    // ======================================================
+    // Data being read
+    // ======================================================
+    
+    reg   [3:0] r_data_vld;
+    reg         r_data_sel;
+    
+    reg  [15:0] r_lrdata_p0;
+    reg  [15:0] r_hrdata_p0;
+    reg  [15:0] r_hrdata_p1;
+    wire [15:0] w_rdata_p0;
+    
+    always@(posedge rst or posedge clk) begin : DATA_READ
+        if (rst) begin
+            r_data_vld  <= 4'b0000;
+            r_data_sel  <= 1'b0;
+            r_lrdata_p0 <= 16'h0000;
+            r_hrdata_p0 <= 16'h0000;
+            r_hrdata_p1 <= 16'h0000;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
+                r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
+                r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
+                r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
+            end
+            r_data_sel  <= r_ram_cyc[1] | r_ram_cyc[3];
+            r_lrdata_p0 <= sdram_dq_i[15:0];
+            r_hrdata_p0 <= sdram_dq_i[31:16];
+            r_hrdata_p1 <= r_hrdata_p0;
+        end
+    end
+    
+    // 32-bit to 16-bit multiplexer
+    assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
+    
+    // Access Port #0
+    assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b0 = r_data_vld[0];
+    
+    // Access Port #1
+    assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b1 = r_data_vld[1];
+    
+    // Access Port #2
+    assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b2 = r_data_vld[2];
+    
+    // Access Port #3
+    assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b3 = r_data_vld[3];
+    
+    // ======================================================
+    // Data being written
+    // ======================================================
+    
+    reg   [3:0] r_data_fe_p0;
+    reg   [3:0] r_data_fe_p1;
+    reg         r_data_oe;
+    
+    reg  [15:0] r_wdata_p2a;
+    reg  [15:0] r_wdata_p2b;
+    reg  [31:0] r_wdata_p3;
+    
+    reg   [1:0] r_bena_p2a;
+    reg   [1:0] r_bena_p2b;
+    reg   [3:0] r_bena_p3;
+    
+    always@(posedge rst or posedge clk) begin : DATA_WRITE
+        if (rst) begin
+            r_data_fe_p0 <= 4'b0000;
+            r_data_fe_p1 <= 4'b0000;
+            r_data_oe    <= 1'b0;
+            r_wdata_p2a  <= 16'h0000;
+            r_wdata_p2b  <= 16'h0000;
+            r_wdata_p3   <= 32'h0000_0000;
+            r_bena_p2a   <= 2'b00;
+            r_bena_p2b   <= 2'b00;
+            r_bena_p3    <= 4'b00_00;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_fe_p0 <= r_wr_act & r_ram_ph;
+                r_data_oe    <= r_wr_ph;
+            end
+            else if (r_ram_cyc[1]) begin
+                r_data_fe_p0 <= 4'b0000;
+                r_data_oe    <= 1'b0;
+            end
+            r_data_fe_p1 <= r_data_fe_p0;
+            
+            if (SDRAM_WIDTH == 32) begin
+                // 16-bit -> 32-bit bus
+                if (r_data_sel) begin
+                    r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2b  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                else begin
+                    r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                r_wdata_p3  <= { r_wdata_p2b, r_wdata_p2a };
+                r_bena_p3   <= { r_bena_p2b, r_bena_p2a };
+            end
+            else begin
+                // 16-bit bus
+                r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                             | wdata_b1 & {16{r_data_fe_p1[1]}}
+                             | wdata_b2 & {16{r_data_fe_p1[2]}}
+                             | wdata_b3 & {16{r_data_fe_p1[3]}};
+                r_wdata_p2b <= r_wdata_p2a;
+                r_wdata_p3  <= { 16'h0000, r_wdata_p2b };
+                
+                r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                             | bena_b1 & {2{r_data_fe_p1[1]}}
+                             | bena_b2 & {2{r_data_fe_p1[2]}}
+                             | bena_b3 & {2{r_data_fe_p1[3]}}
+                             | {2{~|r_data_fe_p1}};
+                r_bena_p2b  <= r_bena_p2a;
+                r_bena_p3   <= { 2'b00, r_bena_p2b };
+            end
+        end
+    end
+    
+    // Output mask, data & enable
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
+    always@(*) sdram_dq_o  = #Tco_dly r_wdata_p3;
+    always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
+    /* verilator lint_on STMTDLY */
+    
+    // Access Port #0
+    assign fetch_b0 = r_data_fe_p0[0];
+    
+    // Access Port #1
+    assign fetch_b1 = r_data_fe_p0[1];
+    
+    // Access Port #2
+    assign fetch_b2 = r_data_fe_p0[2];
+    
+    // Access Port #3
+    assign fetch_b3 = r_data_fe_p0[3];
+    
+endmodule /* verilator tracing_on */
Index: mcctv/svideo/sin_cos.vhd
===================================================================
--- mcctv/svideo/sin_cos.vhd	(nonexistent)
+++ mcctv/svideo/sin_cos.vhd	(revision 181)
@@ -0,0 +1,102 @@
+-- ===================================================================================
+-- Package / Component definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE sin_cos_pkg IS
+  COMPONENT sin_cos
+  PORT(
+    -- Clock
+    clk      : IN  STD_LOGIC;
+    clk_ena  : IN  STD_LOGIC;
+    -- Sine computation
+    sin_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sin_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sin_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    -- Cosine computation
+    cos_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    cos_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    cos_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+  );
+  END COMPONENT;
+END PACKAGE;
+
+-- ===================================================================================
+-- Entity / Architecture definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+ENTITY sin_cos IS
+  PORT(
+    -- Clock
+    clk      : IN  STD_LOGIC;
+    clk_ena  : IN  STD_LOGIC;
+    -- Sine computation
+    sin_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sin_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sin_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    -- Cosine computation
+    cos_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    cos_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    cos_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+  );
+END sin_cos;
+
+ARCHITECTURE rtl OF sin_cos IS
+
+  COMPONENT sin_rom IS
+  PORT
+  (
+    clock     : IN STD_LOGIC;
+    enable    : IN STD_LOGIC := '1';
+    address_a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+    q_a       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+  END COMPONENT sin_rom;
+
+  SIGNAL sin_val    : STD_LOGIC_VECTOR(8 DOWNTO 0);
+  SIGNAL cos_val    : STD_LOGIC_VECTOR(8 DOWNTO 0);
+  SIGNAL sin_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL cos_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
+
+BEGIN
+
+  sin_inst : sin_rom
+  PORT MAP
+  (
+    clock                  => clk,
+    enable                 => clk_ena,
+    address_a(10 DOWNTO 3) => sin_amp,
+    address_a(2)           => sin_ph(2) XOR sin_ph(3),
+    address_a(1)           => sin_ph(1) XOR sin_ph(3),
+    address_a(0)           => sin_ph(0) XOR sin_ph(3),
+    q_a                    => sin_val(7 DOWNTO 0),
+    address_b(10 DOWNTO 3) => cos_amp,
+    address_b(2)           => cos_ph(2) XOR (NOT cos_ph(3)),
+    address_b(1)           => cos_ph(1) XOR (NOT cos_ph(3)),
+    address_b(0)           => cos_ph(0) XOR (NOT cos_ph(3)),
+    q_b                    => cos_val(7 DOWNTO 0)
+  );
+  sin_val(8) <= '0';
+  cos_val(8) <= '0';
+  
+  -- Delayed phase for output generation
+  sin_ph_dly <= sin_ph WHEN rising_edge(clk);
+  cos_ph_dly <= cos_ph WHEN rising_edge(clk);
+
+  -- Output generation using sine and cosine symetries
+  sin_cos_gen:
+  FOR i IN 0 TO 8 GENERATE
+    sin_out(i) <= sin_val(i) XOR sin_ph_dly(4);
+    cos_out(i) <= cos_val(i) XOR cos_ph_dly(3) XOR cos_ph_dly(4);
+  END GENERATE;
+
+END rtl;
\ No newline at end of file
Index: mcctv/svideo/sin_rom.vhd
===================================================================
--- mcctv/svideo/sin_rom.vhd	(nonexistent)
+++ mcctv/svideo/sin_rom.vhd	(revision 181)
@@ -0,0 +1,266 @@
+-- megafunction wizard: %ROM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: sin_rom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.0 Build 132 02/25/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sin_rom IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		enable		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END sin_rom;
+
+
+ARCHITECTURE SYN OF sin_rom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3_bv	: BIT_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			clocken0	: IN STD_LOGIC ;
+			wren_a	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire2    <= '0';
+	sub_wire3_bv(7 DOWNTO 0) <= "00000000";
+	sub_wire3    <= To_stdlogicvector(sub_wire3_bv);
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK0",
+		clock_enable_input_a => "NORMAL",
+		clock_enable_input_b => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK0",
+		init_file => "sin_rom.mif",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		numwords_b => 2048,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 11,
+		widthad_b => 11,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK0"
+	)
+	PORT MAP (
+		clocken0 => enable,
+		wren_a => sub_wire2,
+		wren_b => sub_wire2,
+		clock0 => clock,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => sub_wire3,
+		data_b => sub_wire3,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "sin_rom.mif"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "sin_rom.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0]
+-- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0]
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC enable
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
+-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 GND 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
+-- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
+-- Retrieval info: CONNECT: @data_b 0 0 8 0 GND 0 0 8 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: mcctv/MCCTV_Atari800XL_v0.6_release.txt
===================================================================
--- mcctv/MCCTV_Atari800XL_v0.6_release.txt	(nonexistent)
+++ mcctv/MCCTV_Atari800XL_v0.6_release.txt	(revision 181)
@@ -0,0 +1,93 @@
+===========================================
+ MCCTV Atari 800XL core v0.60 release note
+===========================================
+Mark Watson
+scrameta@gmail.com
+-------------------------------------------
+
+All control is via the MCC controller.
+
+Currently games are limited to those that can be played with start/select/option/reset and joystick.
+
+Special/console keys (joystick 1):
+Start button or button 4  - Start
+Select button or button 3  - Select
+button 2  - Option
+left shoulder 1  - Reset
+left shoulder 2 - Cold start (clear base 64KB RAM and reset) 
+right shoulder 1 - Select drive 1 and cold start
+	Use joystick to make selection in menu
+		Left - up several lines
+		Right - down several lines
+		Up - up 1 line
+		Down - down 1 line
+		Fire - select
+	Remember many titles require holding 'option'
+	Select "DIR .." to go up a directory
+	Select "DIR xxx" to go down a directory
+right shoulder 2 - System settings menu
+	Use joystick to make selection
+	Turbo - system speed
+		Left/right to select
+		1x (default): is very compatible - speed closely matches original hardware ~1.7MHz
+		2x: ~3.4MHz - less compatible
+		4x: ~6.8MHz - less compatible
+		8x/16x: 13MHz, 27MHZ - limited by SDRAM latency, not quicker than 4x yet.
+	RAM
+		Left/right to select
+		64KB:  like 65XE
+		128KB: like 130XE, 64KB ext ram, switchable by antic/cpu
+		320KB(Compy shop)(default): 256KB ext ram, switchable by antic/cpu 
+		320KB(Rambo): 256KB ext ram, both antic/cpu switch together
+		576KB(Compy shop): 512KB ext ram, switchable by antic/cpu 
+		576KB(Rambo): 512KB ext ram, both antic/cpu switch together
+		1088KB: 1024KB ext ram, both antic/cpu switch together
+		4160KB: - very imcompatible!
+	ROM
+		Right/fire: File selector
+		Select a different system OS ROM - can by 16KB or 10KB
+	Drive
+		Left: Remove disk
+		Right: File selector
+		Fire: Put this disk in F1
+	Cartridge 8K simple
+		Fire: select file
+		This allows a ROM to be loaded in the place of BASIC
+		Some simple ROM cartridges can be used
+		This is temporary until proper cartridge support is implemented
+
+System ROM:
+	Loaded from /System/rom/atari800/atarixl.rom
+
+Basic:
+	Loaded from /System/rom/atari800/ataribas.rom
+
+Disk images:
+	Default dir: /atari800/user
+	Supported types: 
+		.ATR - Atari disk image with header. single/medium/double density.
+		.XFD - Atari disk image without header. 
+		.XEX - Atari executable. A simple bootloader is loaded, not 100% compatible. 
+
+Important notes:
+	When running Atari software a lot of programs need to have basic disable. Hold option when pressing reset.
+
+Features
+
+* Acid 800 test pass
+* 99% of software runs
+* Version for PAL/NTSC VGA/SVIDEO
+* Write support
+* Drive emulation
+
+Known issues
+
+* No keyboard support yet
+* ~1% of programs fail
+* Copymate write verify fails
+* Entering menu during disk access may hang ZPU (used for drive emulation/menus)
+* Hardware matches Atari very closely - including overscan corruption - this often shows up on VGA monitors.
+* Cartridge support may be broken
+
+Enjoy !
+
Index: mcctv/TODO
===================================================================
--- mcctv/TODO	(nonexistent)
+++ mcctv/TODO	(revision 181)
@@ -0,0 +1,3 @@
+Merge with mcc216 core - with generic to select composite, sdram size, keyboard/usb etc.
+USB keyboard support?
+On screen keyboard support?
Index: mcctv/atari800core.jdi
===================================================================
--- mcctv/atari800core.jdi	(nonexistent)
+++ mcctv/atari800core.jdi	(revision 181)
@@ -0,0 +1,6 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="00000000000000000000"/>
+  </project>
+  <file_info/>
+</sld_project_info>
Index: mcctv/atari800core.qpf
===================================================================
--- mcctv/atari800core.qpf	(nonexistent)
+++ mcctv/atari800core.qpf	(revision 181)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: mcctv/atari800core.qsf
===================================================================
--- mcctv/atari800core.qsf	(nonexistent)
+++ mcctv/atari800core.qsf	(revision 181)
@@ -0,0 +1,211 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors.  Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 20:12:08  December 25, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_mcc_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name DEVICE EP4CE15E22C7
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core_mcc
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:12:08  DECEMBER 25, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS128
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name SIMULATION_MODE TIMING
+
+set_location_assignment PIN_46 -to AUDIO_L
+set_location_assignment PIN_49 -to AUDIO_R
+set_location_assignment PIN_55 -to FPGA_CLK
+set_location_assignment PIN_42 -to SD_CLK
+set_location_assignment PIN_43 -to SD_CMD
+set_location_assignment PIN_44 -to SD_DAT3
+set_location_assignment PIN_52 -to SD_DAT0
+set_location_assignment PIN_59 -to SDRAM_A[0]
+set_location_assignment PIN_58 -to SDRAM_A[1]
+set_location_assignment PIN_51 -to SDRAM_A[2]
+set_location_assignment PIN_50 -to SDRAM_A[3]
+set_location_assignment PIN_132 -to SDRAM_A[4]
+set_location_assignment PIN_125 -to SDRAM_A[5]
+set_location_assignment PIN_121 -to SDRAM_A[6]
+set_location_assignment PIN_120 -to SDRAM_A[7]
+set_location_assignment PIN_119 -to SDRAM_A[8]
+set_location_assignment PIN_115 -to SDRAM_A[9]
+set_location_assignment PIN_60 -to SDRAM_A[10]
+set_location_assignment PIN_114 -to SDRAM_A[11]
+set_location_assignment PIN_113 -to SDRAM_A[12]
+set_location_assignment PIN_111 -to SDRAM_CLK
+set_location_assignment PIN_110 -to SDRAM_DQMH_n
+set_location_assignment PIN_71 -to SDRAM_DQML_n
+set_location_assignment PIN_106 -to SDRAM_DQ[8]
+set_location_assignment PIN_105 -to SDRAM_DQ[9]
+set_location_assignment PIN_104 -to SDRAM_DQ[10]
+set_location_assignment PIN_103 -to SDRAM_DQ[11]
+set_location_assignment PIN_101 -to SDRAM_DQ[12]
+set_location_assignment PIN_100 -to SDRAM_DQ[13]
+set_location_assignment PIN_99 -to SDRAM_DQ[14]
+set_location_assignment PIN_98 -to SDRAM_DQ[15]
+set_location_assignment PIN_72 -to SDRAM_DQ[7]
+set_location_assignment PIN_76 -to SDRAM_DQ[6]
+set_location_assignment PIN_77 -to SDRAM_DQ[5]
+set_location_assignment PIN_80 -to SDRAM_DQ[4]
+set_location_assignment PIN_83 -to SDRAM_DQ[3]
+set_location_assignment PIN_85 -to SDRAM_DQ[2]
+set_location_assignment PIN_86 -to SDRAM_DQ[1]
+set_location_assignment PIN_87 -to SDRAM_DQ[0]
+set_location_assignment PIN_68 -to SDRAM_CAS_n
+set_location_assignment PIN_66 -to SDRAM_CS_n
+set_location_assignment PIN_64 -to SDRAM_BA[1]
+set_location_assignment PIN_65 -to SDRAM_BA[0]
+set_location_assignment PIN_67 -to SDRAM_RAS_n
+set_location_assignment PIN_69 -to SDRAM_WE_n
+set_location_assignment PIN_112 -to SDRAM_CKE
+set_location_assignment PIN_144 -to VGA_G[0]
+set_location_assignment PIN_143 -to VGA_G[1]
+set_location_assignment PIN_142 -to VGA_G[2]
+set_location_assignment PIN_141 -to VGA_G[3]
+set_location_assignment PIN_137 -to VGA_B[0]
+set_location_assignment PIN_136 -to VGA_B[1]
+set_location_assignment PIN_135 -to VGA_B[2]
+set_location_assignment PIN_133 -to VGA_B[3]
+set_location_assignment PIN_12 -to CFG_CLK
+set_location_assignment PIN_8 -to CFG_CS_n
+set_location_assignment PIN_13 -to CFG_DIN
+set_location_assignment PIN_6 -to CFG_DOUT
+set_location_assignment PIN_31 -to dplus1
+set_location_assignment PIN_30 -to dminus1
+set_location_assignment PIN_33 -to dplus2
+set_location_assignment PIN_32 -to dminus2
+
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]
+
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_SIGNALTAP_FILE atari.stp
+set_location_assignment PLL_2 -to "clk_reset:clk_rst_inst|pll_main:main_inst"
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQMH_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQML_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name IGNORE_LCELL_BUFFERS ON
+set_global_assignment -name IGNORE_CASCADE_BUFFERS ON
+set_location_assignment PLL_4 -to "clk_reset:clk_rst_inst|pll_5M_pal_ntsc:pll_5m_inst" -disable
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+set_global_assignment -name QIP_FILE pll_usb.qip
+set_global_assignment -name QIP_FILE pal_pll.qip
+set_global_assignment -name QIP_FILE pll_downstream_pal.qip
+set_global_assignment -name QIP_FILE ntsc_pll.qip
+set_global_assignment -name QIP_FILE pll_downstream_ntsc.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VERILOG_FILE sdram_ctrl_3_ports.v
+set_global_assignment -name VHDL_FILE zpu_rom.vhdl
+set_global_assignment -name VHDL_FILE atari800core_mcc.vhd
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Index: mcctv/atari800core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mcctv/atari800core.qws
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mcctv/atari800core.sdc
===================================================================
--- mcctv/atari800core.sdc	(nonexistent)
+++ mcctv/atari800core.sdc	(revision 181)
@@ -0,0 +1,3 @@
+create_clock -period 5MHz [get_ports FPGA_CLK]
+derive_pll_clocks
+derive_clock_uncertainty
\ No newline at end of file
Index: mcctv/atari800core_mcc.cmd
===================================================================
--- mcctv/atari800core_mcc.cmd	(nonexistent)
+++ mcctv/atari800core_mcc.cmd	(revision 181)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: mcctv/atari800core_mcc.vhd
===================================================================
--- mcctv/atari800core_mcc.vhd	(nonexistent)
+++ mcctv/atari800core_mcc.vhd	(revision 181)
@@ -0,0 +1,1007 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+use WORK.USBF_Declares.all;
+
+LIBRARY work;
+
+ENTITY atari800core_mcc IS 
+	GENERIC
+	(
+		TV : integer;  -- 1 = PAL, 0=NTSC
+		internal_rom : integer;
+		internal_ram : integer;
+		ext_clock : integer
+	);
+	PORT
+	(
+		FPGA_CLK :  IN  STD_LOGIC; -- crystal appears to be still 5MHz despite comment in file I was sent...
+
+		-- For test bench
+		EXT_CLK_SDRAM : in std_logic_vector(ext_clock downto 1);
+		EXT_CLK : in std_logic_vector(ext_clock downto 1);
+		EXT_SDRAM_CLK : in std_logic_vector(ext_clock downto 1);
+                EXT_SVIDEO_DAC_CLK : in std_logic_vector(ext_clock downto 1);
+                EXT_PLL_LOCKED : in std_logic_vector(ext_clock downto 1);
+
+		--PS2K_CLK :  IN  STD_LOGIC;
+		--PS2K_DAT :  IN  STD_LOGIC;
+		--PS2M_CLK :  IN  STD_LOGIC;
+		--PS2M_DAT :  IN  STD_LOGIC;		
+
+		-- VGA/cough cough... (composite...)
+		--VGA_VS :  OUT  STD_LOGIC;
+		--VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0); -- high bits composite
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0); -- low bits composite
+		--VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		
+		--JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		--JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+		----USB CONNECTIONS (with one 1.5K pull up to 3.3v)  ---------------
+		dplus1  			: inout std_logic;           --D+ data line , pin D16   
+		dminus1 			: inout std_logic;           --D- data line, pin E14
+		----USB CONNECTIONS (with one 1.5K pull up to 3.3v)  ---------------
+		dplus2  			: inout std_logic;           --D+ data line , pin D16   
+		dminus2 			: inout std_logic;           --D- data line, pin E14
+		
+		AUDIO_L : OUT std_logic;
+		AUDIO_R : OUT std_logic;
+
+		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+		SDRAM_CS_N :  OUT  STD_LOGIC;
+		SDRAM_RAS_N :  OUT  STD_LOGIC;
+		SDRAM_CAS_N :  OUT  STD_LOGIC;
+		SDRAM_WE_N :  OUT  STD_LOGIC;
+		SDRAM_DQMH_n :  OUT  STD_LOGIC;
+		SDRAM_DQML_n :  OUT  STD_LOGIC;
+		SDRAM_CLK :  OUT  STD_LOGIC;
+		SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		SD_DAT0 :  IN  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_DAT3 :  OUT  STD_LOGIC;
+
+		-- SPI flash clock
+		CFG_CLK       : OUT   STD_LOGIC;
+		CFG_CS_n      : OUT   STD_LOGIC;
+		CFG_DOUT      : OUT   STD_LOGIC;
+		CFG_DIN       : IN    STD_LOGIC
+	);
+END atari800core_mcc;
+
+ARCHITECTURE vhdl OF atari800core_mcc IS 
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+COMPONENT sdram_ctrl
+port
+(
+  --//--------------------
+  --// Clocks and reset --
+  --//--------------------
+  --// Global reset
+  rst : in std_logic;
+  --// Controller clock
+  clk : in std_logic;
+  --// Sequencer cycles
+  seq_cyc : in std_logic_vector(11 downto 0);
+  --// Sequencer phase
+  seq_ph : in std_logic;
+  --// Refresh cycle
+  refr_cyc : in std_logic;
+  --//------------------------
+  --// Access port #1 (CPU) --
+  --//------------------------
+  --// RAM select
+  ap1_ram_sel : in std_logic;
+  --// Address bus
+  ap1_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap1_rden : in std_logic;
+  --// Write enable
+  ap1_wren : in std_logic;
+  --// Byte enable
+  ap1_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap1_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap1_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap1_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap1_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap1_wr_bst_act : out std_logic;
+  --//------------------------
+  --// Access port #2 (GPU) --
+  --//------------------------
+  --// RAM select
+  ap2_ram_sel : in std_logic;
+  --// Address bus
+  ap2_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap2_rden : in std_logic;
+  --// Write enable
+  ap2_wren : in std_logic;
+  --// Byte enable
+  ap2_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap2_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap2_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap2_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap2_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap2_wr_bst_act : out std_logic;
+  --//------------------------
+  --// Access port #3 (CTL) --
+  --//------------------------
+  --// RAM select
+  ap3_ram_sel : in std_logic;
+  --// Address bus
+  ap3_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap3_rden : in std_logic;
+  --// Write enable
+  ap3_wren : in std_logic;
+  --// Byte enable
+  ap3_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap3_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap3_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap3_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap3_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap3_wr_bst_act : out std_logic;
+  --//------------------------
+  --// SDRAM memory signals --
+  --//------------------------
+  --// SDRAM controller ready
+  sdram_rdy : out std_logic;
+  --// SDRAM chip select
+  sdram_cs_n : out std_logic;
+  --// SDRAM row address strobe
+  sdram_ras_n : out std_logic;
+  --// SDRAM column address strobe
+  sdram_cas_n : out std_logic;
+  --// SDRAM write enable
+  sdram_we_n : out std_logic;
+  --// SDRAM DQ masks
+  sdram_dqm_n : out std_logic_vector(1 downto 0);
+  --// SDRAM bank address
+  sdram_ba : out std_logic_vector(1 downto 0);
+  --// SDRAM address
+  sdram_addr : out std_logic_vector(11 downto 0);
+  --// SDRAM data
+  sdram_dq_oe : out std_logic;
+  sdram_dq_o : out std_logic_vector(15 downto 0);
+  sdram_dq_i : in std_logic_vector(15 downto 0)
+);
+END COMPONENT;
+
+	signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
+	signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
+	
+	signal VIDEO_VS : std_logic;
+	signal VIDEO_HS : std_logic;
+	signal VIDEO_R : std_logic_vector(7 downto 0);
+	signal VIDEO_G : std_logic_vector(7 downto 0);
+	signal VIDEO_B : std_logic_vector(7 downto 0);
+
+	signal VIDEO_BLANK : std_logic;
+	signal VIDEO_BURST : std_logic;
+	signal VIDEO_START_OF_FIELD : std_logic;
+	signal VIDEO_ODD_LINE : std_logic;
+
+	signal PAL : std_logic;
+	
+	signal JOY1_IN_n : std_logic_vector(4 downto 0);
+	signal JOY2_IN_n : std_logic_vector(4 downto 0);
+
+	signal PLL1_LOCKED : std_logic;
+	signal CLK_PLL1 : std_logic;
+	
+	signal RESET_n : std_logic;
+	signal PLL_LOCKED : std_logic;
+	signal CLK : std_logic;
+	signal CLK_SDRAM : std_logic;
+
+	-- SDRAM
+	signal SDRAM_REQUEST : std_logic;
+	signal SDRAM_REQUEST_COMPLETE : std_logic;
+	signal SDRAM_READ_ENABLE :  STD_LOGIC;
+	signal SDRAM_WRITE_ENABLE : std_logic;
+	signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+	SIGNAL SDRAM_DI : std_logic_vector(31 downto 0);
+	SIGNAL SDRAM_WIDTH_32BIT_ACCESS : std_logic;
+	SIGNAL SDRAM_WIDTH_16BIT_ACCESS : std_logic;
+	SIGNAL SDRAM_WIDTH_8BIT_ACCESS : std_logic;
+	
+	signal SDRAM_REFRESH : std_logic;
+
+	signal SYSTEM_RESET_REQUEST: std_logic;
+
+	signal seq_reg : std_logic_vector(11 downto 0);
+	signal seq_next : std_logic_vector(11 downto 0);
+	
+	signal seq_ph_reg : std_logic;
+	signal seq_ph_next : std_logic;
+	
+	signal ref_reg : std_logic;
+	signal ref_next : std_logic;
+
+	signal sdram_request_complete_next : std_logic;
+	signal sdram_request_complete_reg : std_logic;
+
+	signal sdram_request_next : std_logic;
+	signal sdram_request_reg : std_logic;
+
+	signal ram_di_next : std_logic_vector(15 downto 0);
+	signal ram_di_reg : std_logic_vector(15 downto 0);
+
+	signal ram_do_next : std_logic_vector(31 downto 0);
+	signal ram_do_reg : std_logic_vector(31 downto 0);
+
+	signal ram_do : std_logic_vector(15 downto 0);
+
+	signal ram_bena_next : std_logic_vector(1 downto 0);
+	signal ram_bena_reg : std_logic_vector(1 downto 0);
+
+	signal ram_rd_active : std_logic;
+	signal ram_wr_active : std_logic;
+
+	signal sdram_dq_oe : std_logic;
+	signal sdram_dq_o : std_logic_vector(15 downto 0);
+	signal sdram_dq_i : std_logic_vector(15 downto 0);
+	signal sdram_dqm_n_temp : std_logic_vector(1 downto 0);
+	
+	signal sdram_rdy : std_logic;
+	signal sdram_reset_ctrl_n_next : std_logic;
+	signal sdram_reset_ctrl_n_reg : std_logic;
+	signal sdram_reset_n_next : std_logic;
+	signal sdram_reset_n_reg : std_logic;
+
+	-- pokey keyboard
+	SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
+	SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
+	
+	-- gtia consol keys
+	SIGNAL CONSOL_START : std_logic;
+	SIGNAL CONSOL_SELECT : std_logic;
+	SIGNAL CONSOL_OPTION : std_logic;
+	SIGNAL FKEYS : std_logic_vector(11 downto 0);
+
+	-- svideo
+	signal svideo_dac_clk : std_logic;
+
+	signal svideo_y : std_logic_vector(7 downto 0);
+	signal svideo_c : std_logic_vector(5 downto 0);
+
+	-- composite
+	SIGNAL svideo_yout : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL svideo_yout_dly1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL svideo_yout_dly2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL svideo_yout_dly3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	--SIGNAL svideo_cout : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL cvbs1_out : STD_LOGIC_VECTOR(9 DOWNTO 0);
+	SIGNAL cvbs2_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL luma : STD_LOGIC_VECTOR(9 DOWNTO 0);
+	SIGNAL chroma : STD_LOGIC_VECTOR(8 DOWNTO 0);
+	SIGNAL luma_saturated : STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+	-- dma/virtual drive
+	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_FETCH : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
+
+	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT4 : std_logic_vector(31 downto 0);
+
+	signal zpu_pokey_enable : std_logic;
+	signal zpu_sio_txd : std_logic;
+	signal zpu_sio_rxd : std_logic;
+	signal zpu_sio_command : std_logic;
+
+	-- system control from zpu
+	signal ram_select : std_logic_vector(2 downto 0);
+	signal rom_select : std_logic_vector(5 downto 0);
+	signal reset_atari : std_logic;
+	signal pause_atari : std_logic;
+	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
+
+	-- USB joystick
+	SIGNAL joyright1_2  			: STD_LOGIC := '1';
+	SIGNAL joyright1_4  			: STD_LOGIC := '1';
+	SIGNAL joyright1_3  			: STD_LOGIC := '1';
+	SIGNAL joyright1_1			: STD_LOGIC := '1';
+	SIGNAL joy1_start_fire  	: STD_LOGIC := '1';
+	SIGNAL joyright1_r2  		: STD_LOGIC := '1';
+	SIGNAL joyright1_r1  		: STD_LOGIC := '1';
+	-- joystick 1 left side
+	SIGNAL joyleft1_arrow_right  	: STD_LOGIC := '1';
+	SIGNAL joyleft1_arrow_left  	: STD_LOGIC := '1';
+	SIGNAL joyleft1_arrow_down  	: STD_LOGIC := '1';
+	SIGNAL joyleft1_arrow_up  	: STD_LOGIC := '1';
+	SIGNAL joy1_select_fire  	: STD_LOGIC := '1';
+	SIGNAL joyleft1_l2  		: STD_LOGIC := '1';
+	SIGNAL joyleft1_l1  		: STD_LOGIC := '1';
+	
+	SIGNAL joyright2_2  			: STD_LOGIC := '1';
+	SIGNAL joyright2_4  			: STD_LOGIC := '1';
+	SIGNAL joyright2_3  			: STD_LOGIC := '1';
+	SIGNAL joyright2_1			: STD_LOGIC := '1';
+	SIGNAL joy2_start_fire  	: STD_LOGIC := '1';
+	SIGNAL joyright2_r2  		: STD_LOGIC := '1';
+	SIGNAL joyright2_r1  		: STD_LOGIC := '1';
+	-- joystick 1 left side
+	SIGNAL joyleft2_arrow_right  	: STD_LOGIC := '1';
+	SIGNAL joyleft2_arrow_left  	: STD_LOGIC := '1';
+	SIGNAL joyleft2_arrow_down  	: STD_LOGIC := '1';
+	SIGNAL joyleft2_arrow_up  	: STD_LOGIC := '1';
+	SIGNAL joy2_select_fire  	: STD_LOGIC := '1';
+	SIGNAL joyleft2_l2  		: STD_LOGIC := '1';
+	SIGNAL joyleft2_l1  		: STD_LOGIC := '1';
+	
+	signal joyleft1_dummy : std_logic;
+	signal joyright1_dummy : std_logic;
+	signal joyleft2_dummy : std_logic;
+	signal joyright2_dummy : std_logic;
+	
+  SIGNAL reset_usbdrv  	: STD_LOGIC := '0';  
+  SIGNAL cntr_reset  : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111";
+
+  signal usb_clk : std_logic;
+  signal usb_reset_n : std_logic;
+
+BEGIN 
+
+-- disable flash (not used)
+CFG_CLK <= 'Z';
+CFG_CS_n <= '1';
+CFG_DOUT <= 'Z';
+
+-- disable usb
+--dplus1 <= 'Z';
+--dminus1 <= 'Z';
+--dplus2 <= 'Z';
+--dminus2 <= 'Z';
+
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_L_PCM&"0000",
+  dac_out => audio_l
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_R_PCM&"0000",
+  dac_out => audio_r
+);
+
+gen_fake_pll : if ext_clock=1 generate
+	CLK_SDRAM <= EXT_CLK_SDRAM(1);
+	CLK <= EXT_CLK(1);
+	SDRAM_CLK <= EXT_CLK_SDRAM(1);
+	SVIDEO_DAC_CLK <= EXT_SVIDEO_DAC_CLK(1);
+	--SCANDOUBLE_CLK <= EXT_SCANDOUBLE_CLK(1);
+	PLL_LOCKED <= EXT_PLL_LOCKED(1);
+end generate;
+
+gen_real_pll : if ext_clock=0 generate
+	gen_tv_pal : if tv=1 generate
+		mcc_pll : entity work.pal_pll
+		PORT MAP(inclk0 => FPGA_CLK,
+				 c0 => CLK_PLL1,
+				 locked => PLL1_LOCKED);
+		mcc_pll2 : entity work.pll_downstream_pal
+		PORT MAP(inclk0 => CLK_PLL1,
+				 c0 => CLK_SDRAM,
+				 c1 => CLK,
+				 c2 => SDRAM_CLK,
+				 c3 => SVIDEO_DAC_CLK,
+				 c4 => open, --SCANDOUBLE_CLK,      
+				 areset => not(PLL1_LOCKED),
+				 locked => PLL_LOCKED);
+	end generate;
+
+	gen_tv_ntsc : if tv=0 generate
+		mcc_pll : entity work.ntsc_pll
+		PORT MAP(inclk0 => FPGA_CLK,
+				 c0 => CLK_PLL1,
+				 locked => PLL1_LOCKED);
+		mcc_pll2 : entity work.pll_downstream_ntsc
+		PORT MAP(inclk0 => CLK_PLL1,
+				 c0 => CLK_SDRAM,
+				 c1 => CLK,
+				 c2 => SDRAM_CLK,
+				 c3 => SVIDEO_DAC_CLK,
+				 c4 => open, --SCANDOUBLE_CLK,      
+				 areset => not(PLL1_LOCKED),
+				 locked => PLL_LOCKED);
+	end generate;
+end generate;
+
+reset_n <= PLL_LOCKED;
+
+-- Keyboard (will be USB I hope, though component does not appear to support it...)
+--CONSOL_START <= '0';
+--CONSOL_SELECT <= '0';
+--CONSOL_OPTION <= '0';
+--FKEYS <= (others=>'0');
+KEYBOARD_RESPONSE <= (others=>'1');
+
+PAL <= '1' when TV=1 else '0';
+
+atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
+	GENERIC MAP
+	(
+		cycle_length => 16,
+		internal_rom => 0, --internal_rom,
+		internal_ram => 0, --internal_ram,
+		video_bits => 8,
+		palette => 1
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		--RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
+		RESET_N => RESET_N and SDRAM_RESET_N_REG,
+
+		VIDEO_VS => VIDEO_VS,
+		VIDEO_HS => VIDEO_HS,
+		VIDEO_B => VIDEO_B,
+		VIDEO_G => VIDEO_G,
+		VIDEO_R => VIDEO_R,
+		VIDEO_BLANK =>VIDEO_BLANK,
+		VIDEO_BURST =>VIDEO_BURST,
+		VIDEO_START_OF_FIELD =>VIDEO_START_OF_FIELD,
+		VIDEO_ODD_LINE =>VIDEO_ODD_LINE,
+
+		AUDIO_L => AUDIO_L_PCM,
+		AUDIO_R => AUDIO_R_PCM,
+
+		JOY1_n => JOY1_IN_n,
+		JOY2_n => JOY2_IN_n,
+
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+
+		SIO_COMMAND => zpu_sio_command,
+		SIO_RXD => zpu_sio_txd,
+		SIO_TXD => zpu_sio_rxd,
+
+		CONSOL_OPTION => CONSOL_OPTION,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_START => CONSOL_START,
+
+		SDRAM_REQUEST => SDRAM_REQUEST,
+		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
+		SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
+		SDRAM_ADDR => SDRAM_ADDR,
+		SDRAM_DO => ram_do_reg,
+		SDRAM_DI => SDRAM_DI,
+		SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
+		SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
+		SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
+		SDRAM_REFRESH => SDRAM_REFRESH,
+
+		DMA_FETCH => dma_fetch,
+		DMA_READ_ENABLE => dma_read_enable,
+		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		DMA_ADDR => dma_addr_fetch,
+		DMA_WRITE_DATA => dma_write_data,
+		MEMORY_READY_DMA => dma_memory_ready,
+		DMA_MEMORY_DATA => dma_memory_data, 
+
+   		RAM_SELECT => ram_select,
+    		ROM_SELECT => rom_select,
+		PAL => PAL,
+		HALT => pause_atari,
+		THROTTLE_COUNT_6502 => speed_6502
+	);
+
+	process(clk_sdram,sdram_reset_ctrl_n_reg)
+	begin
+		if (sdram_reset_ctrl_n_reg='0') then
+			seq_reg <= "100000000000";
+			seq_ph_reg <= '1';
+			ref_reg <= '0';
+
+			ram_do_reg <= (others=>'0');
+			ram_di_reg <= (others=>'0');
+			ram_bena_reg <= (others=>'0');
+			sdram_request_complete_reg <= '0';
+			sdram_request_reg <= '0';
+		elsif (clk_sdram'event and clk_sdram = '1') then
+			seq_reg <= seq_next;
+			seq_ph_reg <= seq_ph_next;
+			ref_reg <= ref_next;
+
+			ram_do_reg <= ram_do_next;
+			ram_di_reg <= ram_di_next;
+			ram_bena_reg <= ram_bena_next;
+			sdram_request_complete_reg <= sdram_request_complete_next;
+			sdram_request_reg <= sdram_request_next;
+		end if;
+	end process;
+
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			sdram_reset_n_reg <= '0';
+			sdram_reset_ctrl_n_reg <= '0';
+		elsif (clk'event and clk = '1') then
+			sdram_reset_n_reg <= sdram_reset_n_next;
+			sdram_reset_ctrl_n_reg <= reset_n;
+		end if;
+	end process;
+
+	-- Generate sdram sequence
+	process(seq_reg, seq_ph_reg, ref_reg)
+	begin
+		seq_next <= seq_reg(10 downto 0)&seq_reg(11);
+		seq_ph_next <= seq_ph_reg;
+		ref_next <= ref_reg;
+		if (seq_reg(11) = '1') then
+			seq_ph_next <= not(seq_ph_reg);
+			ref_next <= not(ref_reg);
+		end if;
+	end process;
+
+	process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)
+	begin
+		sdram_reset_n_next <= sdram_reset_n_reg;
+		if (sdram_rdy = '1' and seq_next(8)='1' and seq_reg(8)='0') then
+			sdram_reset_n_next <= '1';
+		end if;
+		if (reset_atari = '1') then
+			sdram_reset_n_next <= '0';
+		end if;
+	end process;
+
+	-- Adapt SDRAM
+	process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)
+	begin
+		sdram_request_next <= sdram_request_reg or sdram_request;
+		sdram_request_complete_next <= sdram_request_complete_reg;
+		ram_bena_next <= "00";
+		ram_di_next <= (others=>'0');
+		ram_do_next <= ram_do_reg;
+
+		case seq_reg is
+		when "000000000001" =>
+			-- nop
+		when "000000000010" => -- write data from next...
+			if (SDRAM_WRITE_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					ram_di_next <= SDRAM_DI(7 downto 0)&SDRAM_DI(7 downto 0);
+					ram_bena_next <= SDRAM_ADDR(0)&not(SDRAM_ADDR(0));
+				else
+					ram_di_next <= SDRAM_DI(15 downto 0);
+					ram_bena_next <= "11";
+				end if;
+			end if;
+		when "000000000100" =>
+			if (SDRAM_WRITE_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					ram_di_next <= (others=>'0');
+				else
+					ram_di_next <= SDRAM_DI(31 downto 16);
+					ram_bena_next <= "11";
+				end if;
+			end if;
+			if ((ram_wr_active)='1') then
+				sdram_request_complete_next <= '1';
+				sdram_request_next <= '0';
+			end if;
+		when "000000001000" =>
+			-- nop
+		when "000000010000" =>
+			sdram_request_complete_next <= '0';
+			-- nop
+		when "000000100000" =>
+			-- nop
+		when "000001000000" =>
+			if (SDRAM_READ_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					if (SDRAM_ADDR(0) = '0') then
+						ram_do_next(15 downto 0) <= ram_do(7 downto 0)&ram_do(7 downto 0);
+					else
+						ram_do_next(15 downto 0) <= ram_do(15 downto 8)&ram_do(15 downto 8);
+					end if;
+				else
+					ram_do_next(15 downto 0) <= ram_do;
+				end if;
+			end if;
+		when "000010000000" =>
+			if (SDRAM_READ_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					ram_do_next(31 downto 16) <= (others=>'0');
+				else
+					ram_do_next(31 downto 16) <= ram_do;
+				end if;
+			end if;
+			if ((ram_rd_active)='1') then
+				sdram_request_complete_next <= '1';
+				sdram_request_next <= '0';
+			end if;
+		when "000100000000" =>
+			-- nop
+		when "001000000000" =>
+			-- nop
+		when "010000000000" =>
+			sdram_request_complete_next <= '0';
+			-- nop
+		when "100000000000" =>
+			-- nop
+		when others =>
+			-- never
+		end case;
+	end process;
+
+	SDRAM_REQUEST_COMPLETE <= SDRAM_REQUEST_COMPLETE_REG;
+sdram_controller : sdram_ctrl
+	PORT MAP
+	(
+		CLK => CLK_SDRAM,
+		rst => not(sdram_reset_ctrl_n_reg),
+		seq_cyc => seq_reg(11 downto 0),
+		seq_ph => seq_ph_reg,
+		--refr_cyc => ref_reg,
+		refr_cyc => SDRAM_REFRESH,
+
+		ap1_ram_sel => SDRAM_REQUEST_NEXT,
+		ap1_address => '0'&SDRAM_ADDR(22 downto 1),
+		ap1_rden => SDRAM_READ_ENABLE,
+		ap1_wren => SDRAM_WRITE_ENABLE,
+		ap1_bena => ram_bena_reg,
+		ap1_rddata => ram_do,
+		ap1_wrdata => ram_di_reg,
+		ap1_bst_siz => "001",
+		ap1_rd_bst_act => ram_rd_active,
+		ap1_wr_bst_act => ram_wr_active,
+
+		ap2_ram_sel => '0',
+		ap2_address => "00000000000000000000000",
+		ap2_rden => '0',
+		ap2_wren => '0',
+		ap2_bena => "11",
+		ap2_rddata => open,
+		ap2_wrdata => X"0000",
+		ap2_bst_siz => "111",
+		ap2_rd_bst_act => open,
+		ap2_wr_bst_act => open,
+
+		ap3_ram_sel => '0',
+		ap3_address => "00000000000000000000000",
+		ap3_rden => '0',
+		ap3_wren => '0',
+		ap3_bena => "11",
+		ap3_rddata => open,
+		ap3_wrdata => X"0000",
+		ap3_bst_siz => "111",
+		ap3_rd_bst_act => open,
+		ap3_wr_bst_act => open,
+
+		sdram_rdy => sdram_rdy,
+		sdram_cs_n => sdram_cs_n,
+		sdram_ras_n => sdram_ras_n,
+		sdram_cas_n => sdram_cas_n,
+		sdram_we_n => sdram_we_n,
+		sdram_dqm_n => sdram_dqm_n_temp,
+		sdram_ba => sdram_ba,
+		sdram_addr => sdram_a(11 downto 0),
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+	);
+
+sdram_dqmh_n <= sdram_dqm_n_temp(1);
+sdram_dqml_n <= sdram_dqm_n_temp(0);
+
+sdram_dq <= sdram_dq_o when sdram_dq_oe='1' else (others=>'Z');
+sdram_dq_i <= sdram_dq;
+sdram_a(12) <= '1';
+sdram_cke <= '1';
+
+-- Video options
+	-- SVIDEO COMPONENT
+	svideo : entity work.svideo
+	PORT MAP
+	(
+		areset_n => RESET_N,
+		ecs_clk => CLK,
+		dac_clk => SVIDEO_DAC_CLK,
+		r_in => VIDEO_R,
+		g_in => VIDEO_G,
+		b_in => VIDEO_B,
+		sof => VIDEO_VS, -- base on vsync?
+		vpos_lsb => VIDEO_ODD_LINE,
+		blank => VIDEO_BLANK,
+		burst => VIDEO_BURST,
+		csync_n => not(VIDEO_HS xor VIDEO_VS),
+		
+		y_out => svideo_yout,
+		c_out => open,
+
+ 		luma_out => luma,
+		chroma_out => chroma,
+		
+		pal_ntsc => not(pal)
+	);
+
+zpu: entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 1,
+		spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
+	)
+	PORT MAP
+	(
+		-- standard...
+		CLK => CLK,
+		RESET_N => RESET_N and sdram_rdy,
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH => dma_addr_fetch,
+		ZPU_DATA_OUT => dma_write_data,
+		ZPU_FETCH => dma_fetch,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		ZPU_READ_ENABLE => dma_read_enable,
+		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_MEMORY_DATA => dma_memory_data, 
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM => zpu_addr_rom,
+		ZPU_ROM_DATA => zpu_rom_data,
+
+		-- spi master
+		-- Too painful to bit bang spi from zpu, so we have a hardware master in here
+		ZPU_SD_DAT0 => sd_dat0,
+		ZPU_SD_CLK => sd_clk,
+		ZPU_SD_CMD => sd_cmd,
+		ZPU_SD_DAT3 => sd_dat3,
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE => zpu_pokey_enable,
+		ZPU_SIO_TXD => zpu_sio_txd,
+		ZPU_SIO_RXD => zpu_sio_rxd,
+		ZPU_SIO_COMMAND => zpu_sio_command,
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 => X"00000"&FKEYS,
+		ZPU_IN2 => X"00000000",
+		ZPU_IN3 => X"00000000",
+		ZPU_IN4 => X"00000000",
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => zpu_out1,
+		ZPU_OUT2 => zpu_out2,
+		ZPU_OUT3 => zpu_out3,
+		ZPU_OUT4 => zpu_out4
+	);
+
+	pause_atari <= zpu_out1(0);
+	reset_atari <= zpu_out1(1);
+	speed_6502 <= zpu_out1(7 downto 2);
+	ram_select <= zpu_out1(10 downto 8);
+	rom_select <= zpu_out1(16 downto 11);
+
+zpu_rom1: entity work.zpu_rom
+	port map(
+	        clock => clk,
+	        address => zpu_addr_rom(13 downto 2),
+	        q => zpu_rom_data
+	);
+
+enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	generic map (COUNT=>16) -- cycle_length
+	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
+
+mcc_pll3 : entity work.pll_usb
+	PORT MAP(inclk0 => FPGA_CLK,
+		 c0 => USB_CLK,
+		 locked => USB_RESET_N);
+
+  -----------------------------------------------------------------------------------------------
+  --------------------------------  reset process for USB component -----------------------------
+  -----------------------------------------------------------------------------------------------
+  PROCESS(usb_reset_n,usb_clk)
+  BEGIN
+    -- 
+   IF (usb_reset_n = '0') THEN
+		cntr_reset 			<= "01100111";
+		reset_usbdrv 		<= '0';
+   ELSIF (rising_edge(usb_clk)) THEN
+		IF (cntr_reset = "00000000") THEN
+			reset_usbdrv 		<= '1';				-- reset released
+		ELSE
+			cntr_reset 			<= cntr_reset - 1; -- 
+      END IF;
+   END IF;			
+  END PROCESS;
+
+  -----------------------------------------------------------------------------------------------
+  ------------------------------- Main USB interface Component ----------------------------------
+  -----------------------------------------------------------------------------------------------
+		
+-- USB 1 interface Component.
+  UUSB_1 : USBF_IFC1 -- 
+    port map(
+      clk_usb     			=> usb_clk,        	-- 12MHz master clock input
+		pll_lock					=> usb_reset_n,
+      reset       			=> reset_usbdrv,            		-- XST reset push button
+      ----USB CONNECTIONS               	---------
+      dplus       			=> dplus1,             	--differential data
+      dminus      			=> dminus1,
+      ----------------------------
+		joyright_out(0) 		=> joyright1_2,
+		joyright_out(1) 		=> joyright1_4,
+		joyright_out(2) 		=> joyright1_3,
+		joyright_out(3) 		=> joyright1_1,
+		joyright_out(4) 		=> joy1_start_fire,
+		joyright_out(5)       => joyright1_dummy,
+		joyright_out(6) 		=> joyright1_r2,
+		joyright_out(7) 		=> joyright1_r1,
+		-- joystick 1 left side
+		joyleft_out(0) 		=> joyleft1_arrow_right,
+		joyleft_out(1) 		=> joyleft1_arrow_left,
+		joyleft_out(2) 		=> joyleft1_arrow_down,
+		joyleft_out(3) 		=> joyleft1_arrow_up,
+		joyleft_out(4) 		=> joy1_select_fire,
+		joyleft_out(5)       => joyleft1_dummy,
+		joyleft_out(6) 		=> joyleft1_l2,
+		joyleft_out(7) 		=> joyleft1_l1,
+		mousex_out				=> open,
+		mousey_out				=> open
+      );
+		
+-- USB 2 interface Component.
+  UUSB_2 : USBF_IFC2 -- 
+    port map(
+      clk_usb     			=> usb_clk,        	-- 12MHz master clock input
+		pll_lock					=> usb_reset_n,
+      reset       			=> reset_usbdrv,            		-- XST reset push button
+      --USB CONNECTIONS               	---------
+      dplus       			=> dplus2,             	--differential data
+      dminus      			=> dminus2,
+      -- joystick 2 right side
+		joyright_out(0) 		=> joyright2_2,
+		joyright_out(1) 		=> joyright2_4,
+		joyright_out(2) 		=> joyright2_3,
+		joyright_out(3) 		=> joyright2_1,
+		joyright_out(4) 		=> joy2_start_fire,
+		joyright_out(5)       => joyright2_dummy,
+		joyright_out(6) 		=> joyright2_r2,
+		joyright_out(7) 		=> joyright2_r1,
+		-- joystick 2 left side
+		joyleft_out(0) 		=> joyleft2_arrow_right,
+		joyleft_out(1) 		=> joyleft2_arrow_left,
+		joyleft_out(2) 		=> joyleft2_arrow_down,
+		joyleft_out(3) 		=> joyleft2_arrow_up,
+		joyleft_out(4) 		=> joy2_select_fire,
+		joyleft_out(5)       => joyleft2_dummy,
+		joyleft_out(6) 		=> joyleft2_l2,
+		joyleft_out(7) 		=> joyleft2_l1,
+		mousex_out				=> open,
+		mousey_out				=> open
+      );
+		
+-- Joystick (will be USB)
+--JOY1_IN_N <= (others=>'1');
+--JOY2_IN_N <= (others=>'1');
+
+	-- joystick player 1
+	joy1_in_n 				<= --(joy1_start_fire AND joyright1_r2 AND joyleft1_l2) &
+										--(joy1_start_fire AND joyright1_r1 AND joyleft1_l1) &
+										joyright1_1 &
+										joyleft1_arrow_right 	&
+										joyleft1_arrow_left 	&
+										joyleft1_arrow_down 	&
+										joyleft1_arrow_up;
+										
+	-- joystick player 2
+	joy2_in_n 				<= --(joy2_start_fire AND joyright2_r2 AND joyleft2_l2) &
+										--(joy2_start_fire AND joyright2_r1 AND joyleft2_l1) &
+										joyright2_1 &
+										joyleft2_arrow_right 	&
+										joyleft2_arrow_left 	&
+										joyleft2_arrow_down 	&
+										joyleft2_arrow_up;
+
+CONSOL_START <= not(joy1_start_fire and joyright1_4);
+CONSOL_SELECT <= not(joy1_select_fire and joyright1_3);
+CONSOL_OPTION <= not(joyright1_2);
+FKEYS(7 downto 0) <= (others=>'0');
+FKEYS(8) <= not(joyleft1_l1);
+FKEYS(9) <= not(joyleft1_l2);
+FKEYS(10) <= not(joyright1_r1);
+FKEYS(11) <= not(joyright1_r2);
+
+  ---------------------------------
+  -- process for CVBS output (TODO - merge this into the svideo.vhd component, as an option...)
+  ---------------------------------
+ -- cvbs_block:
+ -- IF (SVIDEO_OUT = 2) GENERATE
+  PROCESS
+  (
+    svideo_dac_clk,
+    svideo_yout_dly1,
+    svideo_yout_dly2,
+	 svideo_yout_dly3
+  )
+  BEGIN
+	IF (rising_edge(svideo_dac_clk)) THEN
+		svideo_yout_dly1			<= 	svideo_yout;
+		svideo_yout_dly2			<= 	svideo_yout_dly1;
+		svideo_yout_dly3			<= 	svideo_yout_dly2;
+		luma_saturated		    	<= 	luma - "0000011111";
+		cvbs1_out  					<= 	luma_saturated + (chroma(8) & chroma(8 DOWNTO 0)) ;
+		IF (svideo_yout_dly2 = "00000000") THEN
+			cvbs2_out  				<=  "00000000";
+		ELSE 
+			cvbs2_out  				<=  cvbs1_out(9 DOWNTO 2);
+		END IF;
+     END IF;
+  END PROCESS;
+
+  VGA_B				<= cvbs2_out(7 DOWNTO 4); -- WHEN JOY1_n(2) = '1' ELSE svideo_yout(7 DOWNTO 4) ;
+  VGA_G				<= cvbs2_out(3 DOWNTO 0); -- WHEN JOY1_n(2) = '1' ELSE svideo_yout(3 DOWNTO 0) ; 
+ -- END GENERATE;
+
+END vhdl;
Index: mcctv/atari800core_mcc.wcfg
===================================================================
--- mcctv/atari800core_mcc.wcfg	(nonexistent)
+++ mcctv/atari800core_mcc.wcfg	(revision 181)
@@ -0,0 +1,234 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+            <top_module name="zpupkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="50" />
+   <wvobject fp_name="/atari800core_mcc_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_ba" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_cs_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cs_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cs_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_ras_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ras_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_ras_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_cas_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cas_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cas_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_we_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_we_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_we_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_dqm_n" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_clk</obj_property>
+      <obj_property name="ObjectShortName">sdram_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_a[12:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_a[12:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_dq" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/di" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">di[7:0]</obj_property>
+      <obj_property name="ObjectShortName">di[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/do" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">do[7:0]</obj_property>
+      <obj_property name="ObjectShortName">do[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">a[15:0]</obj_property>
+      <obj_property name="ObjectShortName">a[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/throttle" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">throttle</obj_property>
+      <obj_property name="ObjectShortName">throttle</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/memory_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">memory_ready</obj_property>
+      <obj_property name="ObjectShortName">memory_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request</obj_property>
+      <obj_property name="ObjectShortName">sdram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_complete_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_complete_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_complete" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_rdy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_rdy</obj_property>
+      <obj_property name="ObjectShortName">sdram_rdy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_addr[22:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_addr[22:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/cpu_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_fetch</obj_property>
+      <obj_property name="ObjectShortName">cpu_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/antic_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">antic_fetch</obj_property>
+      <obj_property name="ObjectShortName">antic_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_rden" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_rden</obj_property>
+      <obj_property name="ObjectShortName">ap1_rden</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wren" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wren</obj_property>
+      <obj_property name="ObjectShortName">ap1_wren</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/ram_rd_active" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_rd_active</obj_property>
+      <obj_property name="ObjectShortName">ram_rd_active</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/ram_wr_active" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_wr_active</obj_property>
+      <obj_property name="ObjectShortName">ram_wr_active</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/seq_ph_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_ph_reg</obj_property>
+      <obj_property name="ObjectShortName">seq_ph_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/seq_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_dat0" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat0</obj_property>
+      <obj_property name="ObjectShortName">sd_dat0</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_clk</obj_property>
+      <obj_property name="ObjectShortName">sd_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_cmd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_cmd</obj_property>
+      <obj_property name="ObjectShortName">sd_cmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_dat3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat3</obj_property>
+      <obj_property name="ObjectShortName">sd_dat3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/clock" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clock</obj_property>
+      <obj_property name="ObjectShortName">clock</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enable</obj_property>
+      <obj_property name="ObjectShortName">enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/cpol" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpol</obj_property>
+      <obj_property name="ObjectShortName">cpol</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/cpha" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpha</obj_property>
+      <obj_property name="ObjectShortName">cpha</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/cont" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cont</obj_property>
+      <obj_property name="ObjectShortName">cont</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/clk_div" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_div</obj_property>
+      <obj_property name="ObjectShortName">clk_div</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/addr" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">addr</obj_property>
+      <obj_property name="ObjectShortName">addr</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/tx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">tx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">tx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/miso" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">miso</obj_property>
+      <obj_property name="ObjectShortName">miso</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/mosi" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mosi</obj_property>
+      <obj_property name="ObjectShortName">mosi</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/busy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">busy</obj_property>
+      <obj_property name="ObjectShortName">busy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/rx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv/atari_mcc_auto_stripped.stp
===================================================================
--- mcctv/atari_mcc_auto_stripped.stp	(nonexistent)
+++ mcctv/atari_mcc_auto_stripped.stp	(revision 181)
@@ -0,0 +1,1585 @@
+<session jtag_chain="USB-Blaster [1-2]" jtag_device="@1: EP3C16/EP4CE15 (0x020F20DD)" sof_file="">
+  <display_tree gui_logging_enabled="1">
+    <display_branch instance="auto_signaltap_0" log="log: 2014/04/26 08:28:05  #1" signal_set="signal_set: 2014/04/25 22:38:45  #0" trigger="trigger: 2014/04/26 08:28:05  #0"/>
+  </display_tree>
+  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
+    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
+    <signal_set is_expanded="true" name="signal_set: 2014/04/25 22:38:45  #0">
+      <clock name="sdram_ctrl:sdram_controller|clk" polarity="posedge" tap_mode="classic"/>
+      <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="no" trigger_out_enable="no"/>
+      <top_entity/>
+      <signal_vec>
+        <trigger_input_vec>
+          <wire name="SDRAM_CAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[0]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[10]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[11]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[12]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[13]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[14]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[15]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[1]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[2]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[3]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[4]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[5]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[6]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[7]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[8]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[9]" tap_mode="classic"/>
+          <wire name="SDRAM_RAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_WE_N" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[16]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[17]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[18]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[19]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[20]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[21]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[22]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[23]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_rden" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wren" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_oe" tap_mode="classic"/>
+          <wire name="sdram_request_complete_reg" tap_mode="classic"/>
+          <wire name="sdram_request_reg" tap_mode="classic"/>
+        </trigger_input_vec>
+        <data_input_vec>
+          <wire name="SDRAM_CAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[0]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[10]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[11]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[12]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[13]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[14]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[15]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[1]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[2]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[3]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[4]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[5]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[6]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[7]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[8]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[9]" tap_mode="classic"/>
+          <wire name="SDRAM_RAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_WE_N" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[16]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[17]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[18]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[19]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[20]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[21]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[22]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[23]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_rden" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wren" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_oe" tap_mode="classic"/>
+          <wire name="sdram_request_complete_reg" tap_mode="classic"/>
+          <wire name="sdram_request_reg" tap_mode="classic"/>
+        </data_input_vec>
+        <storage_qualifier_input_vec>
+          <wire name="SDRAM_CAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[0]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[10]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[11]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[12]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[13]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[14]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[15]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[1]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[2]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[3]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[4]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[5]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[6]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[7]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[8]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[9]" tap_mode="classic"/>
+          <wire name="SDRAM_RAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_WE_N" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[16]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[17]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[18]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[19]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[20]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[21]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[22]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[23]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_rden" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wren" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_oe" tap_mode="classic"/>
+          <wire name="sdram_request_complete_reg" tap_mode="classic"/>
+          <wire name="sdram_request_reg" tap_mode="classic"/>
+        </storage_qualifier_input_vec>
+      </signal_vec>
+      <presentation>
+        <unified_setup_data_view>
+          <node name="sdram_ctrl:sdram_controller|ap1_address" order="msb_to_lsb" type="combinatorial">
+            <node data_index="233" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_oe" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="combinatorial"/>
+            <node data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="bidir pin"/>
+            <node data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="bidir pin"/>
+            <node data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="bidir pin"/>
+            <node data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="bidir pin"/>
+            <node data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="bidir pin"/>
+            <node data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="bidir pin"/>
+            <node data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="bidir pin"/>
+            <node data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="bidir pin"/>
+            <node data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="bidir pin"/>
+            <node data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="bidir pin"/>
+            <node data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="bidir pin"/>
+            <node data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="bidir pin"/>
+            <node data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="bidir pin"/>
+            <node data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="bidir pin"/>
+            <node data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="bidir pin"/>
+            <node data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="bidir pin"/>
+            <node data_index="157" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="combinatorial"/>
+            <node data_index="156" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="combinatorial"/>
+            <node data_index="155" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="combinatorial"/>
+            <node data_index="154" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="combinatorial"/>
+            <node data_index="152" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="combinatorial"/>
+            <node data_index="151" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="combinatorial"/>
+            <node data_index="150" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="combinatorial"/>
+            <node data_index="149" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="combinatorial"/>
+            <node data_index="148" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="combinatorial"/>
+            <node data_index="147" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="combinatorial"/>
+            <node data_index="146" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="combinatorial"/>
+            <node data_index="145" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="combinatorial"/>
+            <node data_index="144" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="combinatorial"/>
+            <node data_index="143" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="combinatorial"/>
+            <node data_index="165" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="combinatorial"/>
+            <node data_index="164" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="combinatorial"/>
+            <node data_index="163" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="combinatorial"/>
+            <node data_index="162" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="combinatorial"/>
+            <node data_index="161" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="combinatorial"/>
+            <node data_index="160" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="combinatorial"/>
+            <node data_index="159" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="combinatorial"/>
+            <node data_index="158" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="combinatorial"/>
+            <node data_index="153" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="combinatorial"/>
+          </node>
+          <node data_index="166" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_rden" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="combinatorial"/>
+          <node data_index="167" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="combinatorial"/>
+          <node name="sdram_ctrl:sdram_controller|ap1_wrdata" order="msb_to_lsb" type="combinatorial">
+            <node data_index="174" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="combinatorial"/>
+            <node data_index="173" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="combinatorial"/>
+            <node data_index="172" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="combinatorial"/>
+            <node data_index="171" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="combinatorial"/>
+            <node data_index="170" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="combinatorial"/>
+            <node data_index="169" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="combinatorial"/>
+            <node data_index="183" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="combinatorial"/>
+            <node data_index="182" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="combinatorial"/>
+            <node data_index="181" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="combinatorial"/>
+            <node data_index="180" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="combinatorial"/>
+            <node data_index="179" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="combinatorial"/>
+            <node data_index="178" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="combinatorial"/>
+            <node data_index="177" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="combinatorial"/>
+            <node data_index="176" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="combinatorial"/>
+            <node data_index="175" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="combinatorial"/>
+            <node data_index="168" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="combinatorial"/>
+          </node>
+          <node data_index="184" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wren" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="combinatorial"/>
+          <node data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_CAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="output pin"/>
+          <node data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_RAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="output pin"/>
+          <node data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="falling edge" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_WE_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="output pin"/>
+          <node name="sdram_ctrl:sdram_controller|r_sdram_dq_o" order="msb_to_lsb" type="register">
+            <node data_index="191" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="register"/>
+            <node data_index="190" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="register"/>
+            <node data_index="189" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="register"/>
+            <node data_index="188" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="register"/>
+            <node data_index="187" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="register"/>
+            <node data_index="186" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="register"/>
+            <node data_index="200" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="register"/>
+            <node data_index="199" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="register"/>
+            <node data_index="198" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="register"/>
+            <node data_index="197" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="register"/>
+            <node data_index="196" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="register"/>
+            <node data_index="195" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="register"/>
+            <node data_index="194" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="register"/>
+            <node data_index="193" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="register"/>
+            <node data_index="192" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="register"/>
+            <node data_index="185" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="register"/>
+          </node>
+          <node name="sdram_ctrl:sdram_controller|sdram_dq_i" order="msb_to_lsb" type="combinatorial">
+            <node data_index="207" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="combinatorial"/>
+            <node data_index="206" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="combinatorial"/>
+            <node data_index="205" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="combinatorial"/>
+            <node data_index="204" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="combinatorial"/>
+            <node data_index="203" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="combinatorial"/>
+            <node data_index="202" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="combinatorial"/>
+            <node data_index="216" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="combinatorial"/>
+            <node data_index="215" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="combinatorial"/>
+            <node data_index="214" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="combinatorial"/>
+            <node data_index="213" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="combinatorial"/>
+            <node data_index="212" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="combinatorial"/>
+            <node data_index="211" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="combinatorial"/>
+            <node data_index="210" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="combinatorial"/>
+            <node data_index="209" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="combinatorial"/>
+            <node data_index="208" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="combinatorial"/>
+            <node data_index="201" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="combinatorial"/>
+          </node>
+          <node name="sdram_ctrl:sdram_controller|sdram_dq_o" order="msb_to_lsb" type="combinatorial">
+            <node data_index="223" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="combinatorial"/>
+            <node data_index="222" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="combinatorial"/>
+            <node data_index="221" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="combinatorial"/>
+            <node data_index="220" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="combinatorial"/>
+            <node data_index="219" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="combinatorial"/>
+            <node data_index="218" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="combinatorial"/>
+            <node data_index="232" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="combinatorial"/>
+            <node data_index="231" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="combinatorial"/>
+            <node data_index="230" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="combinatorial"/>
+            <node data_index="229" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="combinatorial"/>
+            <node data_index="228" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="combinatorial"/>
+            <node data_index="227" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="combinatorial"/>
+            <node data_index="226" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="combinatorial"/>
+            <node data_index="225" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="combinatorial"/>
+            <node data_index="224" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="combinatorial"/>
+            <node data_index="217" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="combinatorial"/>
+          </node>
+          <node data_index="234" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_complete_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="register"/>
+          <node data_index="235" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="register"/>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR" order="msb_to_lsb" type="combinatorial">
+            <node data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>
+            <node data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>
+            <node data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>
+            <node data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>
+            <node data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>
+            <node data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>
+            <node data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>
+            <node data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>
+            <node data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>
+            <node data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>
+            <node data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>
+            <node data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>
+            <node data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>
+            <node data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>
+            <node data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>
+            <node data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>
+            <node data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>
+            <node data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>
+            <node data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>
+            <node data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>
+            <node data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>
+            <node data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>
+            <node data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>
+          </node>
+          <node data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI" order="msb_to_lsb" type="combinatorial">
+            <node data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="combinatorial"/>
+            <node data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="combinatorial"/>
+            <node data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="combinatorial"/>
+            <node data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="combinatorial"/>
+            <node data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="combinatorial"/>
+            <node data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="combinatorial"/>
+            <node data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="combinatorial"/>
+            <node data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="combinatorial"/>
+            <node data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="combinatorial"/>
+            <node data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="combinatorial"/>
+            <node data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="combinatorial"/>
+            <node data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="combinatorial"/>
+            <node data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="combinatorial"/>
+            <node data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="combinatorial"/>
+            <node data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="combinatorial"/>
+            <node data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="combinatorial"/>
+            <node data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="combinatorial"/>
+            <node data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>
+            <node data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>
+            <node data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>
+            <node data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>
+            <node data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>
+            <node data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="combinatorial"/>
+            <node data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="combinatorial"/>
+            <node data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="combinatorial"/>
+            <node data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="combinatorial"/>
+            <node data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="combinatorial"/>
+            <node data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="combinatorial"/>
+            <node data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="combinatorial"/>
+            <node data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="combinatorial"/>
+            <node data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="combinatorial"/>
+            <node data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>
+          </node>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO" order="msb_to_lsb" type="combinatorial">
+            <node data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="combinatorial"/>
+            <node data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="combinatorial"/>
+            <node data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="combinatorial"/>
+            <node data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="combinatorial"/>
+            <node data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="combinatorial"/>
+            <node data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="combinatorial"/>
+            <node data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="combinatorial"/>
+            <node data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="combinatorial"/>
+            <node data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="combinatorial"/>
+            <node data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="combinatorial"/>
+            <node data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="combinatorial"/>
+            <node data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="combinatorial"/>
+            <node data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="combinatorial"/>
+            <node data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="combinatorial"/>
+            <node data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="combinatorial"/>
+            <node data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="combinatorial"/>
+            <node data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="combinatorial"/>
+            <node data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="combinatorial"/>
+            <node data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="combinatorial"/>
+            <node data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="combinatorial"/>
+            <node data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="combinatorial"/>
+            <node data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="combinatorial"/>
+            <node data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="combinatorial"/>
+            <node data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="combinatorial"/>
+            <node data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="combinatorial"/>
+            <node data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="combinatorial"/>
+            <node data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="combinatorial"/>
+            <node data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="combinatorial"/>
+            <node data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="combinatorial"/>
+            <node data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="combinatorial"/>
+            <node data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="combinatorial"/>
+            <node data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="combinatorial"/>
+          </node>
+          <node data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="combinatorial"/>
+          <node data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="combinatorial"/>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A" order="msb_to_lsb" type="combinatorial">
+            <node data_index="115" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="combinatorial"/>
+            <node data_index="114" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="combinatorial"/>
+            <node data_index="113" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="combinatorial"/>
+            <node data_index="112" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="combinatorial"/>
+            <node data_index="111" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="combinatorial"/>
+            <node data_index="110" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="combinatorial"/>
+            <node data_index="124" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="combinatorial"/>
+            <node data_index="123" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="combinatorial"/>
+            <node data_index="122" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="combinatorial"/>
+            <node data_index="121" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="combinatorial"/>
+            <node data_index="120" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="combinatorial"/>
+            <node data_index="119" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="combinatorial"/>
+            <node data_index="118" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="combinatorial"/>
+            <node data_index="117" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="combinatorial"/>
+            <node data_index="116" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="combinatorial"/>
+            <node data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="combinatorial"/>
+          </node>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI" order="msb_to_lsb" type="combinatorial">
+            <node data_index="132" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="combinatorial"/>
+            <node data_index="131" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="combinatorial"/>
+            <node data_index="130" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="combinatorial"/>
+            <node data_index="129" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="combinatorial"/>
+            <node data_index="128" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="combinatorial"/>
+            <node data_index="127" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="combinatorial"/>
+            <node data_index="126" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="combinatorial"/>
+            <node data_index="125" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="combinatorial"/>
+          </node>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO" order="msb_to_lsb" type="combinatorial">
+            <node data_index="140" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="combinatorial"/>
+            <node data_index="139" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="combinatorial"/>
+            <node data_index="138" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="combinatorial"/>
+            <node data_index="137" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="combinatorial"/>
+            <node data_index="136" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="combinatorial"/>
+            <node data_index="135" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="combinatorial"/>
+            <node data_index="134" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="combinatorial"/>
+            <node data_index="133" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="combinatorial"/>
+          </node>
+          <node data_index="142" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="combinatorial"/>
+          <node data_index="141" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="combinatorial"/>
+        </unified_setup_data_view>
+        <data_view>
+          <bus name="sdram_ctrl:sdram_controller|ap1_address" order="msb_to_lsb" type="combinatorial">
+            <net data_index="233" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_oe" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="combinatorial"/>
+            <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="bidir pin"/>
+            <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="bidir pin"/>
+            <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="bidir pin"/>
+            <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="bidir pin"/>
+            <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="bidir pin"/>
+            <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="bidir pin"/>
+            <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="bidir pin"/>
+            <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="bidir pin"/>
+            <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="bidir pin"/>
+            <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="bidir pin"/>
+            <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="bidir pin"/>
+            <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="bidir pin"/>
+            <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="bidir pin"/>
+            <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="bidir pin"/>
+            <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="bidir pin"/>
+            <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="bidir pin"/>
+            <net data_index="157" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="combinatorial"/>
+            <net data_index="156" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="combinatorial"/>
+            <net data_index="155" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="combinatorial"/>
+            <net data_index="154" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="combinatorial"/>
+            <net data_index="152" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="combinatorial"/>
+            <net data_index="151" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="combinatorial"/>
+            <net data_index="150" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="combinatorial"/>
+            <net data_index="149" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="combinatorial"/>
+            <net data_index="148" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="combinatorial"/>
+            <net data_index="147" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="combinatorial"/>
+            <net data_index="146" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="combinatorial"/>
+            <net data_index="145" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="combinatorial"/>
+            <net data_index="144" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="combinatorial"/>
+            <net data_index="143" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="combinatorial"/>
+            <net data_index="165" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="combinatorial"/>
+            <net data_index="164" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="combinatorial"/>
+            <net data_index="163" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="combinatorial"/>
+            <net data_index="162" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="combinatorial"/>
+            <net data_index="161" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="combinatorial"/>
+            <net data_index="160" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="combinatorial"/>
+            <net data_index="159" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="combinatorial"/>
+            <net data_index="158" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="combinatorial"/>
+            <net data_index="153" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="combinatorial"/>
+          </bus>
+          <net data_index="166" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_rden" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="combinatorial"/>
+          <net data_index="167" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="combinatorial"/>
+          <bus name="sdram_ctrl:sdram_controller|ap1_wrdata" order="msb_to_lsb" type="combinatorial">
+            <net data_index="174" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="combinatorial"/>
+            <net data_index="173" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="combinatorial"/>
+            <net data_index="172" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="combinatorial"/>
+            <net data_index="171" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="combinatorial"/>
+            <net data_index="170" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="combinatorial"/>
+            <net data_index="169" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="combinatorial"/>
+            <net data_index="183" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="combinatorial"/>
+            <net data_index="182" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="combinatorial"/>
+            <net data_index="181" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="combinatorial"/>
+            <net data_index="180" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="combinatorial"/>
+            <net data_index="179" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="combinatorial"/>
+            <net data_index="178" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="combinatorial"/>
+            <net data_index="177" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="combinatorial"/>
+            <net data_index="176" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="combinatorial"/>
+            <net data_index="175" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="combinatorial"/>
+            <net data_index="168" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="combinatorial"/>
+          </bus>
+          <net data_index="184" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wren" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="combinatorial"/>
+          <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_CAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="output pin"/>
+          <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_RAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="output pin"/>
+          <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="falling edge" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_WE_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="output pin"/>
+          <bus name="sdram_ctrl:sdram_controller|r_sdram_dq_o" order="msb_to_lsb" type="register">
+            <net data_index="191" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="register"/>
+            <net data_index="190" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="register"/>
+            <net data_index="189" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="register"/>
+            <net data_index="188" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="register"/>
+            <net data_index="187" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="register"/>
+            <net data_index="186" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="register"/>
+            <net data_index="200" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="register"/>
+            <net data_index="199" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="register"/>
+            <net data_index="198" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="register"/>
+            <net data_index="197" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="register"/>
+            <net data_index="196" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="register"/>
+            <net data_index="195" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="register"/>
+            <net data_index="194" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="register"/>
+            <net data_index="193" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="register"/>
+            <net data_index="192" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="register"/>
+            <net data_index="185" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="register"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_i" order="msb_to_lsb" type="combinatorial">
+            <net data_index="207" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="combinatorial"/>
+            <net data_index="206" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="combinatorial"/>
+            <net data_index="205" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="combinatorial"/>
+            <net data_index="204" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="combinatorial"/>
+            <net data_index="203" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="combinatorial"/>
+            <net data_index="202" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="combinatorial"/>
+            <net data_index="216" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="combinatorial"/>
+            <net data_index="215" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="combinatorial"/>
+            <net data_index="214" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="combinatorial"/>
+            <net data_index="213" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="combinatorial"/>
+            <net data_index="212" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="combinatorial"/>
+            <net data_index="211" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="combinatorial"/>
+            <net data_index="210" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="combinatorial"/>
+            <net data_index="209" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="combinatorial"/>
+            <net data_index="208" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="combinatorial"/>
+            <net data_index="201" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="combinatorial"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_o" order="msb_to_lsb" type="combinatorial">
+            <net data_index="223" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="combinatorial"/>
+            <net data_index="222" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="combinatorial"/>
+            <net data_index="221" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="combinatorial"/>
+            <net data_index="220" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="combinatorial"/>
+            <net data_index="219" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="combinatorial"/>
+            <net data_index="218" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="combinatorial"/>
+            <net data_index="232" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="combinatorial"/>
+            <net data_index="231" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="combinatorial"/>
+            <net data_index="230" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="combinatorial"/>
+            <net data_index="229" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="combinatorial"/>
+            <net data_index="228" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="combinatorial"/>
+            <net data_index="227" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="combinatorial"/>
+            <net data_index="226" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="combinatorial"/>
+            <net data_index="225" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="combinatorial"/>
+            <net data_index="224" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="combinatorial"/>
+            <net data_index="217" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="combinatorial"/>
+          </bus>
+          <net data_index="234" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_complete_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="register"/>
+          <net data_index="235" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="register"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR" order="msb_to_lsb" type="combinatorial">
+            <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>
+            <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>
+            <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>
+            <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>
+            <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>
+            <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>
+            <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>
+            <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>
+            <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>
+            <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>
+            <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>
+            <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>
+            <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>
+            <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>
+            <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>
+            <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>
+            <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>
+            <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>
+            <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>
+            <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>
+            <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>
+            <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>
+            <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>
+          </bus>
+          <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="combinatorial"/>
+            <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="combinatorial"/>
+            <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="combinatorial"/>
+            <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="combinatorial"/>
+            <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="combinatorial"/>
+            <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="combinatorial"/>
+            <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="combinatorial"/>
+            <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="combinatorial"/>
+            <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="combinatorial"/>
+            <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="combinatorial"/>
+            <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="combinatorial"/>
+            <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="combinatorial"/>
+            <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="combinatorial"/>
+            <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="combinatorial"/>
+            <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="combinatorial"/>
+            <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="combinatorial"/>
+            <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="combinatorial"/>
+            <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>
+            <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>
+            <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>
+            <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>
+            <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>
+            <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="combinatorial"/>
+            <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="combinatorial"/>
+            <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="combinatorial"/>
+            <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="combinatorial"/>
+            <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="combinatorial"/>
+            <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="combinatorial"/>
+            <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="combinatorial"/>
+            <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="combinatorial"/>
+            <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="combinatorial"/>
+            <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="combinatorial"/>
+            <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="combinatorial"/>
+            <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="combinatorial"/>
+            <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="combinatorial"/>
+            <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="combinatorial"/>
+            <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="combinatorial"/>
+            <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="combinatorial"/>
+            <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="combinatorial"/>
+            <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="combinatorial"/>
+            <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="combinatorial"/>
+            <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="combinatorial"/>
+            <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="combinatorial"/>
+            <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="combinatorial"/>
+            <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="combinatorial"/>
+            <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="combinatorial"/>
+            <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="combinatorial"/>
+            <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="combinatorial"/>
+            <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="combinatorial"/>
+            <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="combinatorial"/>
+            <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="combinatorial"/>
+            <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="combinatorial"/>
+            <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="combinatorial"/>
+            <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="combinatorial"/>
+            <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="combinatorial"/>
+            <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="combinatorial"/>
+            <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="combinatorial"/>
+            <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="combinatorial"/>
+            <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="combinatorial"/>
+            <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="combinatorial"/>
+            <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="combinatorial"/>
+            <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="combinatorial"/>
+            <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="combinatorial"/>
+          </bus>
+          <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="combinatorial"/>
+          <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A" order="msb_to_lsb" type="combinatorial">
+            <net data_index="115" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="combinatorial"/>
+            <net data_index="114" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="combinatorial"/>
+            <net data_index="113" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="combinatorial"/>
+            <net data_index="112" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="combinatorial"/>
+            <net data_index="111" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="combinatorial"/>
+            <net data_index="110" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="combinatorial"/>
+            <net data_index="124" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="combinatorial"/>
+            <net data_index="123" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="combinatorial"/>
+            <net data_index="122" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="combinatorial"/>
+            <net data_index="121" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="combinatorial"/>
+            <net data_index="120" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="combinatorial"/>
+            <net data_index="119" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="combinatorial"/>
+            <net data_index="118" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="combinatorial"/>
+            <net data_index="117" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="combinatorial"/>
+            <net data_index="116" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="combinatorial"/>
+            <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="132" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="combinatorial"/>
+            <net data_index="131" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="combinatorial"/>
+            <net data_index="130" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="combinatorial"/>
+            <net data_index="129" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="combinatorial"/>
+            <net data_index="128" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="combinatorial"/>
+            <net data_index="127" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="combinatorial"/>
+            <net data_index="126" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="combinatorial"/>
+            <net data_index="125" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="140" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="combinatorial"/>
+            <net data_index="139" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="combinatorial"/>
+            <net data_index="138" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="combinatorial"/>
+            <net data_index="137" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="combinatorial"/>
+            <net data_index="136" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="combinatorial"/>
+            <net data_index="135" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="combinatorial"/>
+            <net data_index="134" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="combinatorial"/>
+            <net data_index="133" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="combinatorial"/>
+          </bus>
+          <net data_index="142" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="combinatorial"/>
+          <net data_index="141" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="combinatorial"/>
+        </data_view>
+        <setup_view>
+          <bus name="sdram_ctrl:sdram_controller|ap1_address" order="msb_to_lsb" type="combinatorial">
+            <net data_index="233" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_oe" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="combinatorial"/>
+            <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="bidir pin"/>
+            <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="bidir pin"/>
+            <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="bidir pin"/>
+            <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="bidir pin"/>
+            <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="bidir pin"/>
+            <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="bidir pin"/>
+            <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="bidir pin"/>
+            <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="bidir pin"/>
+            <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="bidir pin"/>
+            <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="bidir pin"/>
+            <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="bidir pin"/>
+            <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="bidir pin"/>
+            <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="bidir pin"/>
+            <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="bidir pin"/>
+            <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="bidir pin"/>
+            <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="bidir pin"/>
+            <net data_index="157" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="combinatorial"/>
+            <net data_index="156" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="combinatorial"/>
+            <net data_index="155" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="combinatorial"/>
+            <net data_index="154" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="combinatorial"/>
+            <net data_index="152" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="combinatorial"/>
+            <net data_index="151" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="combinatorial"/>
+            <net data_index="150" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="combinatorial"/>
+            <net data_index="149" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="combinatorial"/>
+            <net data_index="148" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="combinatorial"/>
+            <net data_index="147" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="combinatorial"/>
+            <net data_index="146" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="combinatorial"/>
+            <net data_index="145" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="combinatorial"/>
+            <net data_index="144" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="combinatorial"/>
+            <net data_index="143" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="combinatorial"/>
+            <net data_index="165" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="combinatorial"/>
+            <net data_index="164" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="combinatorial"/>
+            <net data_index="163" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="combinatorial"/>
+            <net data_index="162" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="combinatorial"/>
+            <net data_index="161" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="combinatorial"/>
+            <net data_index="160" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="combinatorial"/>
+            <net data_index="159" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="combinatorial"/>
+            <net data_index="158" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="combinatorial"/>
+            <net data_index="153" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="combinatorial"/>
+          </bus>
+          <net data_index="166" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_rden" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="combinatorial"/>
+          <net data_index="167" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="combinatorial"/>
+          <bus name="sdram_ctrl:sdram_controller|ap1_wrdata" order="msb_to_lsb" type="combinatorial">
+            <net data_index="174" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="combinatorial"/>
+            <net data_index="173" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="combinatorial"/>
+            <net data_index="172" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="combinatorial"/>
+            <net data_index="171" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="combinatorial"/>
+            <net data_index="170" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="combinatorial"/>
+            <net data_index="169" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="combinatorial"/>
+            <net data_index="183" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="combinatorial"/>
+            <net data_index="182" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="combinatorial"/>
+            <net data_index="181" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="combinatorial"/>
+            <net data_index="180" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="combinatorial"/>
+            <net data_index="179" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="combinatorial"/>
+            <net data_index="178" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="combinatorial"/>
+            <net data_index="177" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="combinatorial"/>
+            <net data_index="176" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="combinatorial"/>
+            <net data_index="175" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="combinatorial"/>
+            <net data_index="168" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="combinatorial"/>
+          </bus>
+          <net data_index="184" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wren" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="combinatorial"/>
+          <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_CAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="output pin"/>
+          <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_RAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="output pin"/>
+          <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="falling edge" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_WE_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="output pin"/>
+          <bus name="sdram_ctrl:sdram_controller|r_sdram_dq_o" order="msb_to_lsb" type="register">
+            <net data_index="191" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="register"/>
+            <net data_index="190" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="register"/>
+            <net data_index="189" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="register"/>
+            <net data_index="188" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="register"/>
+            <net data_index="187" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="register"/>
+            <net data_index="186" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="register"/>
+            <net data_index="200" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="register"/>
+            <net data_index="199" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="register"/>
+            <net data_index="198" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="register"/>
+            <net data_index="197" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="register"/>
+            <net data_index="196" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="register"/>
+            <net data_index="195" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="register"/>
+            <net data_index="194" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="register"/>
+            <net data_index="193" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="register"/>
+            <net data_index="192" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="register"/>
+            <net data_index="185" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="register"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_i" order="msb_to_lsb" type="combinatorial">
+            <net data_index="207" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="combinatorial"/>
+            <net data_index="206" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="combinatorial"/>
+            <net data_index="205" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="combinatorial"/>
+            <net data_index="204" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="combinatorial"/>
+            <net data_index="203" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="combinatorial"/>
+            <net data_index="202" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="combinatorial"/>
+            <net data_index="216" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="combinatorial"/>
+            <net data_index="215" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="combinatorial"/>
+            <net data_index="214" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="combinatorial"/>
+            <net data_index="213" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="combinatorial"/>
+            <net data_index="212" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="combinatorial"/>
+            <net data_index="211" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="combinatorial"/>
+            <net data_index="210" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="combinatorial"/>
+            <net data_index="209" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="combinatorial"/>
+            <net data_index="208" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="combinatorial"/>
+            <net data_index="201" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="combinatorial"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_o" order="msb_to_lsb" type="combinatorial">
+            <net data_index="223" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="combinatorial"/>
+            <net data_index="222" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="combinatorial"/>
+            <net data_index="221" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="combinatorial"/>
+            <net data_index="220" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="combinatorial"/>
+            <net data_index="219" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="combinatorial"/>
+            <net data_index="218" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="combinatorial"/>
+            <net data_index="232" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="combinatorial"/>
+            <net data_index="231" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="combinatorial"/>
+            <net data_index="230" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="combinatorial"/>
+            <net data_index="229" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="combinatorial"/>
+            <net data_index="228" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="combinatorial"/>
+            <net data_index="227" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="combinatorial"/>
+            <net data_index="226" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="combinatorial"/>
+            <net data_index="225" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="combinatorial"/>
+            <net data_index="224" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="combinatorial"/>
+            <net data_index="217" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="combinatorial"/>
+          </bus>
+          <net data_index="234" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_complete_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="register"/>
+          <net data_index="235" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="register"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR" order="msb_to_lsb" type="combinatorial">
+            <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>
+            <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>
+            <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>
+            <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>
+            <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>
+            <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>
+            <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>
+            <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>
+            <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>
+            <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>
+            <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>
+            <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>
+            <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>
+            <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>
+            <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>
+            <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>
+            <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>
+            <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>
+            <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>
+            <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>
+            <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>
+            <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>
+            <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>
+          </bus>
+          <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="combinatorial"/>
+            <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="combinatorial"/>
+            <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="combinatorial"/>
+            <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="combinatorial"/>
+            <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="combinatorial"/>
+            <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="combinatorial"/>
+            <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="combinatorial"/>
+            <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="combinatorial"/>
+            <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="combinatorial"/>
+            <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="combinatorial"/>
+            <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="combinatorial"/>
+            <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="combinatorial"/>
+            <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="combinatorial"/>
+            <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="combinatorial"/>
+            <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="combinatorial"/>
+            <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="combinatorial"/>
+            <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="combinatorial"/>
+            <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>
+            <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>
+            <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>
+            <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>
+            <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>
+            <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="combinatorial"/>
+            <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="combinatorial"/>
+            <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="combinatorial"/>
+            <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="combinatorial"/>
+            <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="combinatorial"/>
+            <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="combinatorial"/>
+            <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="combinatorial"/>
+            <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="combinatorial"/>
+            <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="combinatorial"/>
+            <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="combinatorial"/>
+            <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="combinatorial"/>
+            <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="combinatorial"/>
+            <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="combinatorial"/>
+            <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="combinatorial"/>
+            <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="combinatorial"/>
+            <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="combinatorial"/>
+            <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="combinatorial"/>
+            <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="combinatorial"/>
+            <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="combinatorial"/>
+            <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="combinatorial"/>
+            <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="combinatorial"/>
+            <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="combinatorial"/>
+            <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="combinatorial"/>
+            <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="combinatorial"/>
+            <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="combinatorial"/>
+            <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="combinatorial"/>
+            <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="combinatorial"/>
+            <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="combinatorial"/>
+            <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="combinatorial"/>
+            <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="combinatorial"/>
+            <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="combinatorial"/>
+            <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="combinatorial"/>
+            <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="combinatorial"/>
+            <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="combinatorial"/>
+            <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="combinatorial"/>
+            <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="combinatorial"/>
+            <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="combinatorial"/>
+            <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="combinatorial"/>
+            <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="combinatorial"/>
+            <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="combinatorial"/>
+            <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="combinatorial"/>
+          </bus>
+          <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="combinatorial"/>
+          <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A" order="msb_to_lsb" type="combinatorial">
+            <net data_index="115" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="combinatorial"/>
+            <net data_index="114" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="combinatorial"/>
+            <net data_index="113" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="combinatorial"/>
+            <net data_index="112" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="combinatorial"/>
+            <net data_index="111" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="combinatorial"/>
+            <net data_index="110" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="combinatorial"/>
+            <net data_index="124" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="combinatorial"/>
+            <net data_index="123" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="combinatorial"/>
+            <net data_index="122" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="combinatorial"/>
+            <net data_index="121" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="combinatorial"/>
+            <net data_index="120" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="combinatorial"/>
+            <net data_index="119" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="combinatorial"/>
+            <net data_index="118" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="combinatorial"/>
+            <net data_index="117" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="combinatorial"/>
+            <net data_index="116" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="combinatorial"/>
+            <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="132" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="combinatorial"/>
+            <net data_index="131" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="combinatorial"/>
+            <net data_index="130" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="combinatorial"/>
+            <net data_index="129" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="combinatorial"/>
+            <net data_index="128" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="combinatorial"/>
+            <net data_index="127" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="combinatorial"/>
+            <net data_index="126" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="combinatorial"/>
+            <net data_index="125" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="140" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="combinatorial"/>
+            <net data_index="139" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="combinatorial"/>
+            <net data_index="138" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="combinatorial"/>
+            <net data_index="137" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="combinatorial"/>
+            <net data_index="136" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="combinatorial"/>
+            <net data_index="135" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="combinatorial"/>
+            <net data_index="134" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="combinatorial"/>
+            <net data_index="133" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="combinatorial"/>
+          </bus>
+          <net data_index="142" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="combinatorial"/>
+          <net data_index="141" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="combinatorial"/>
+        </setup_view>
+        <trigger_in_editor/>
+        <trigger_out_editor/>
+      </presentation>
+      <trigger CRC="FA424211" attribute_mem_mode="false" gap_record="true" is_expanded="true" name="trigger: 2014/04/26 08:28:05  #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1024" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
+        <power_up_trigger position="pre" storage_qualifier_disabled="no"/>
+        <events use_custom_flow_control="no">
+          <level enabled="no" name="condition1" type="basic">'SDRAM_WE_N' == falling edge
+            <power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="no" name="condition2" type="basic">'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]' == low
+            <power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="yes" name="condition3" type="basic"><power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="yes" name="condition4" type="basic"><power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="yes" name="condition5" type="basic"><power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <custom_flow_control>
+            <runtime_configurable comparison_operator="yes" counter_action="no" flag_action="no" logical_operator="yes" numerical_value="yes" state_transition="yes"/>
+            <flow_expression><![CDATA[state ST1:
+trigger;]]>
+            </flow_expression>
+            <power_up_flow_expression><![CDATA[state ST1:
+trigger;]]>
+            </power_up_flow_expression>
+          </custom_flow_control>
+        </events>
+        <storage_qualifier_events>
+          <transitional>11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
+            <pwr_up_transitional>11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional>
+          </transitional>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+        </storage_qualifier_events>
+      </trigger>
+    </signal_set>
+    <position_info>
+      <single attribute="active tab" value="0"/>
+      <single attribute="data horizontal scroll position" value="360"/>
+      <single attribute="data vertical scroll position" value="0"/>
+      <single attribute="zoom level denominator" value="1"/>
+      <single attribute="zoom level numerator" value="64"/>
+      <single attribute="zoom offset denominator" value="1"/>
+      <single attribute="zoom offset numerator" value="2032"/>
+    </position_info>
+  </instance>
+  <mnemonics/>
+  <static_plugin_mnemonics/>
+  <global_info>
+    <single attribute="active instance" value="0"/>
+    <single attribute="config widget visible" value="1"/>
+    <single attribute="data log widget visible" value="1"/>
+    <single attribute="hierarchy widget visible" value="1"/>
+    <single attribute="instance widget visible" value="1"/>
+    <single attribute="jtag widget visible" value="1"/>
+    <multi attribute="frame size" size="2" value="1625,976"/>
+    <multi attribute="jtag widget size" size="2" value="398,120"/>
+  </global_info>
+</session>
Index: mcctv/build.sh
===================================================================
--- mcctv/build.sh	(nonexistent)
+++ mcctv/build.sh	(revision 181)
@@ -0,0 +1,108 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $wanted_variant = shift @ARGV;
+
+#variants...
+my $PAL = 1;
+my $NTSC = 0;
+
+my $SVIDEO = 1;
+my $VGA = 2;
+
+#Added like this to the generated qsf
+#set_parameter -name TV 1
+
+my %variants = 
+(
+	"PAL_SVIDEO" => 
+	{
+		"TV" => $PAL,
+		"SCANDOUBLE" => 0,
+		"VIDEO" => $SVIDEO,
+		"internal_ram" => 0,
+		"internal_rom" => 0,
+		"ext_clock" => 0
+	},
+	"NTSC_SVIDEO" =>
+	{
+		"TV" => $NTSC,
+		"SCANDOUBLE" => 0,
+		"VIDEO" => $SVIDEO,
+		"internal_ram" => 0,
+		"internal_rom" => 0,
+		"ext_clock" => 0
+	}
+);
+
+if (not defined $wanted_variant or (not exists $variants{$wanted_variant} and $wanted_variant ne "ALL"))
+{
+	die "Provide variant of ALL or ".join ",",sort keys %variants;
+}
+
+foreach my $variant (sort keys %variants)
+{
+	next if ($wanted_variant ne $variant and $wanted_variant ne "ALL");
+	print "Building $variant\n";
+
+	my $dir = "build_$variant";
+	`rm -rf $dir`;
+	mkdir $dir;
+	`cp atari800core_mcc.vhd $dir`;
+	`cp *pll*.* $dir`;
+	`cp sdram_ctrl_3_ports.v $dir`;
+	`cp zpu_rom.vhdl $dir`;
+	`cp atari800core.sdc $dir`;
+	`mkdir $dir/common`;
+	`mkdir $dir/common/a8core`;
+	`mkdir $dir/common/components`;
+	`mkdir $dir/common/zpu`;
+	`mkdir $dir/svideo`;
+	`mkdir $dir/usb`;
+	`cp ../common/a8core/* ./$dir/common/a8core`;
+	`cp ../common/components/* ./$dir/common/components`;
+	`cp ../common/zpu/* ./$dir/common/zpu`;
+	`cp ./svideo/* ./$dir/svideo`;
+	`cp ./usb/* ./$dir/usb`;
+
+	chdir $dir;
+	`../makeqsf ../atari800core.qsf ./svideo ./usb ./common/a8core ./common/components ./common/zpu`;
+
+	foreach my $key (sort keys %{$variants{$variant}})
+	{
+		my $val = $variants{$variant}->{$key};
+		`echo set_parameter -name $key $val >> atari800core.qsf`;
+	}
+
+	`quartus_sh --flow compile atari800core > build.log 2> build.err`;
+
+	`quartus_cpf --convert ../output_file.cof`;
+	my $vga = 1;
+	if ($variant =~ /SVIDEO/)
+	{
+		$vga = 0;
+	}
+	
+	#TODO - generate automated version number
+	my $version = `svn info  | grep Revision: | cut -d' ' -f 2`;
+	chomp $version;
+	$version = `date +%y%m`;
+	my $version2 = `date +%d`;
+	chomp $version;
+	chomp $version2;
+	$version = 0
+	$version2 = 6
+	my $cmd = "wine ../rbf2arg/rbf2arg.exe $vga A $version.$version2 \"Atari 800XL $variant\" output_files/atari800core.rbf output_files/atari800core_$variant.arg";
+	print "Running $cmd\n";
+	`$cmd`;
+	
+	chdir "..";
+}
+
+
+#--for the MCC216 S-Video
+#--rbf2arg 0 A <version.revison> "description" <filename.rbf> <filename.arg>
+#--for the MCC216 VGA
+#--rbf2arg 1 A <version.revison> "description" <filename.rbf> <filename.arg>
+
+

Property changes on: mcctv/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcctv/cparg
===================================================================
--- mcctv/cparg	(nonexistent)
+++ mcctv/cparg	(revision 181)
@@ -0,0 +1,5 @@
+ln -s build_NTSC_SVIDEO/output_files/atari800core.arg atari800core.arg_NTSC_SVIDEO
+ln -s build_PAL_SVIDEO/output_files/atari800core.arg atari800core.arg_PAL_SVIDEO
+ln -s build_NTSC_VGA/output_files/atari800core.arg atari800core.arg_NTSC_VGA
+ln -s build_PAL_VGA/output_files/atari800core.arg atari800core.arg_PAL_VGA
+ln -s build_SIMPLE/output_files/atari800core.arg atari800core.arg_SIMPLE

Property changes on: mcctv/cparg
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcctv/makeqsf
===================================================================
--- mcctv/makeqsf	(nonexistent)
+++ mcctv/makeqsf	(revision 181)
@@ -0,0 +1,39 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $qsf_in = shift @ARGV;
+my $qsf_out = $qsf_in;
+$qsf_out =~ s/.*\///;
+
+open (QSF_IN,$qsf_in) or die "Failed to open $qsf_in";
+my @qsf_base = <QSF_IN>;
+close (QSF_IN);
+
+open (QSF_OUT,">$qsf_out") or die "Failed to open $qsf_out";
+print QSF_OUT @qsf_base;
+
+foreach (@ARGV)
+{
+	my @vhdl = glob ("$_/*.vhd");
+	push @vhdl, glob ("$_/*.vhdl");
+	my @verilog = glob ("$_/*.v");
+	my @qip = glob ("$_/*.qip");
+
+	foreach (@verilog)
+	{
+		print QSF_OUT "set_global_assignment -name VERILOG_FILE $_\n";
+	}
+
+	foreach (@vhdl)
+	{
+		print QSF_OUT "set_global_assignment -name VHDL_FILE $_\n";
+	}
+
+	foreach (@qip)
+	{
+		print QSF_OUT "set_global_assignment -name QIP_FILE $_\n";
+	}
+}
+
+close (QSF_OUT);
+

Property changes on: mcctv/makeqsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcctv/ntsc_pll.cmp
===================================================================
--- mcctv/ntsc_pll.cmp	(nonexistent)
+++ mcctv/ntsc_pll.cmp	(revision 181)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component ntsc_pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcctv/ntsc_pll.ppf
===================================================================
--- mcctv/ntsc_pll.ppf	(nonexistent)
+++ mcctv/ntsc_pll.ppf	(revision 181)
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="ntsc_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcctv/ntsc_pll.qip
===================================================================
--- mcctv/ntsc_pll.qip	(nonexistent)
+++ mcctv/ntsc_pll.qip	(revision 181)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ntsc_pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ntsc_pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ntsc_pll.ppf"]
Index: mcctv/ntsc_pll.vhd
===================================================================
--- mcctv/ntsc_pll.vhd	(nonexistent)
+++ mcctv/ntsc_pll.vhd	(revision 181)
@@ -0,0 +1,360 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: ntsc_pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ntsc_pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END ntsc_pll;
+
+
+ARCHITECTURE SYN OF ntsc_pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	locked    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "LOW",
+		clk0_divide_by => 11,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 63,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=ntsc_pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "11"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636364"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "63"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcctv/output_file.cof
===================================================================
--- mcctv/output_file.cof	(nonexistent)
+++ mcctv/output_file.cof	(revision 181)
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
+<cof>
+	<eprom_name>CFI_128Mb</eprom_name>
+	<output_filename>output_files/atari800core.rbf</output_filename>
+	<n_pages>1</n_pages>
+	<width>1</width>
+	<mode>0</mode>
+	<sof_data>
+		<user_name>Page_0</user_name>
+		<page_flags>1</page_flags>
+		<bit0>
+			<sof_filename>output_files/atari800core.sof<compress_bitstream>1</compress_bitstream></sof_filename>
+		</bit0>
+	</sof_data>
+	<version>5</version>
+	<create_cvp_file>0</create_cvp_file>
+	<options>
+	</options>
+</cof>
Index: mcctv/pal_pll.cmp
===================================================================
--- mcctv/pal_pll.cmp	(nonexistent)
+++ mcctv/pal_pll.cmp	(revision 181)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pal_pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcctv/pal_pll.ppf
===================================================================
--- mcctv/pal_pll.ppf	(nonexistent)
+++ mcctv/pal_pll.ppf	(revision 181)
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pal_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcctv/pal_pll.qip
===================================================================
--- mcctv/pal_pll.qip	(nonexistent)
+++ mcctv/pal_pll.qip	(revision 181)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pal_pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pal_pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pal_pll.ppf"]
Index: mcctv/pal_pll.vhd
===================================================================
--- mcctv/pal_pll.vhd	(nonexistent)
+++ mcctv/pal_pll.vhd	(revision 181)
@@ -0,0 +1,360 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pal_pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pal_pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pal_pll;
+
+
+ARCHITECTURE SYN OF pal_pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	locked    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "LOW",
+		clk0_divide_by => 40,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 227,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pal_pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "40"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.375000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "227"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcctv/pll_downstream_ntsc.cmp
===================================================================
--- mcctv/pll_downstream_ntsc.cmp	(nonexistent)
+++ mcctv/pll_downstream_ntsc.cmp	(revision 181)
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_downstream_ntsc
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcctv/pll_downstream_ntsc.ppf
===================================================================
--- mcctv/pll_downstream_ntsc.ppf	(nonexistent)
+++ mcctv/pll_downstream_ntsc.ppf	(revision 181)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_downstream_ntsc" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcctv/pll_downstream_ntsc.vhd
===================================================================
--- mcctv/pll_downstream_ntsc.vhd	(nonexistent)
+++ mcctv/pll_downstream_ntsc.vhd	(revision 181)
@@ -0,0 +1,493 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_downstream_ntsc.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_downstream_ntsc IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_downstream_ntsc;
+
+
+ARCHITECTURE SYN OF pll_downstream_ntsc IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire9_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire9_bv(0 DOWNTO 0) <= "0";
+	sub_wire9    <= To_stdlogicvector(sub_wire9_bv);
+	sub_wire5    <= sub_wire0(3);
+	sub_wire4    <= sub_wire0(4);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	c2    <= sub_wire3;
+	c4    <= sub_wire4;
+	c3    <= sub_wire5;
+	locked    <= sub_wire6;
+	sub_wire7    <= inclk0;
+	sub_wire8    <= sub_wire9(0 DOWNTO 0) & sub_wire7;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "HIGH",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 3,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 1,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 1,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 3,
+		clk2_phase_shift => "7500",
+		clk3_divide_by => 1,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 4,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 1,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 2,
+		clk4_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 34921,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_downstream_ntsc",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire8,
+		clk => sub_wire0,
+		locked => sub_wire6
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.907997"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "28.636000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "85.907997"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "114.543999"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "57.271999"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "28.636"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "7.50000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_downstream.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "7500"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "34921"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcctv/pll_downstream_pal.ppf
===================================================================
--- mcctv/pll_downstream_pal.ppf	(nonexistent)
+++ mcctv/pll_downstream_pal.ppf	(revision 181)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_downstream_pal" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcctv/pll_downstream_pal.vhd
===================================================================
--- mcctv/pll_downstream_pal.vhd	(nonexistent)
+++ mcctv/pll_downstream_pal.vhd	(revision 181)
@@ -0,0 +1,493 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_downstream_pal.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_downstream_pal IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_downstream_pal;
+
+
+ARCHITECTURE SYN OF pll_downstream_pal IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire9_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire9_bv(0 DOWNTO 0) <= "0";
+	sub_wire9    <= To_stdlogicvector(sub_wire9_bv);
+	sub_wire5    <= sub_wire0(3);
+	sub_wire4    <= sub_wire0(4);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	c2    <= sub_wire3;
+	c4    <= sub_wire4;
+	c3    <= sub_wire5;
+	locked    <= sub_wire6;
+	sub_wire7    <= inclk0;
+	sub_wire8    <= sub_wire9(0 DOWNTO 0) & sub_wire7;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "HIGH",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 3,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 1,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 1,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 3,
+		clk2_phase_shift => "7500",
+		clk3_divide_by => 1,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 4,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 1,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 2,
+		clk4_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 35242,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_downstream_pal",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire8,
+		clk => sub_wire0,
+		locked => sub_wire6
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.125000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "28.375000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "85.125000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "113.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "56.750000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "28.375"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "7.50000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_downstream.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "7500"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "35242"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_pal.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_pal.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_pal.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_pal.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_pal.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_pal_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcctv/pll_usb.ppf
===================================================================
--- mcctv/pll_usb.ppf	(nonexistent)
+++ mcctv/pll_usb.ppf	(revision 181)
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone IV E" variation_name="pll_usb" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcctv/rbf2arg/rbf2arg.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mcctv/rbf2arg/rbf2arg.exe
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mcctv/sdram_ctrl_3_ports.v
===================================================================
--- mcctv/sdram_ctrl_3_ports.v	(nonexistent)
+++ mcctv/sdram_ctrl_3_ports.v	(revision 181)
@@ -0,0 +1,629 @@
+//`include "arg_defs.vh"
+
+module sdram_ctrl /* verilator tracing_off */
+(
+  //--------------------
+  // Clocks and reset --
+  //--------------------
+  // Global reset
+  input             rst,
+  // Controller clock
+  input             clk,
+  // Sequencer cycles
+  input      [11:0] seq_cyc,
+  // Sequencer phase
+  input             seq_ph,
+  // Refresh cycle
+  input             refr_cyc,
+  //------------------------
+  // Access port #1 (CPU) --
+  //------------------------
+  // RAM select
+  input             ap1_ram_sel,
+  // Address bus
+  input      [23:1] ap1_address,
+  // Read enable
+  input             ap1_rden,
+  // Write enable
+  input             ap1_wren,
+  // Byte enable
+  input       [1:0] ap1_bena,
+  // Data bus (read)
+  output     [15:0] ap1_rddata,
+  // Data bus (write)
+  input      [15:0] ap1_wrdata,
+  // Burst size
+  input       [2:0] ap1_bst_siz,
+  // Read burst active
+  output reg        ap1_rd_bst_act,
+  // Write burst active
+  output            ap1_wr_bst_act,
+  //------------------------
+  // Access port #2 (GPU) --
+  //------------------------
+  // RAM select
+  input             ap2_ram_sel,
+  // Address bus
+  input      [23:1] ap2_address,
+  // Read enable
+  input             ap2_rden,
+  // Write enable
+  input             ap2_wren,
+  // Byte enable
+  input       [1:0] ap2_bena,
+  // Data bus (read)
+  output     [15:0] ap2_rddata,
+  // Data bus (write)
+  input      [15:0] ap2_wrdata,
+  // Burst size
+  input       [2:0] ap2_bst_siz,
+  // Read burst active
+  output reg        ap2_rd_bst_act,
+  // Write burst active
+  output            ap2_wr_bst_act,
+  //------------------------
+  // Access port #3 (CTL) --
+  //------------------------
+  // RAM select
+  input             ap3_ram_sel,
+  // Address bus
+  input      [23:1] ap3_address,
+  // Read enable
+  input             ap3_rden,
+  // Write enable
+  input             ap3_wren,
+  // Byte enable
+  input       [1:0] ap3_bena,
+  // Data bus (read)
+  output     [15:0] ap3_rddata,
+  // Data bus (write)
+  input      [15:0] ap3_wrdata,
+  // Burst size
+  input       [2:0] ap3_bst_siz,
+  // Read burst active
+  output reg        ap3_rd_bst_act,
+  // Write burst active
+  output            ap3_wr_bst_act,
+  //------------------------
+  // SDRAM memory signals --
+  //------------------------
+  // SDRAM controller ready
+  output reg        sdram_rdy,
+  // SDRAM chip select
+  output reg        sdram_cs_n,
+  // SDRAM row address strobe
+  output reg        sdram_ras_n,
+  // SDRAM column address strobe
+  output reg        sdram_cas_n,
+  // SDRAM write enable
+  output reg        sdram_we_n,
+  // SDRAM DQ masks
+  output reg  [1:0] sdram_dqm_n,
+  // SDRAM bank address
+  output reg  [1:0] sdram_ba,
+  // SDRAM address
+  output reg [11:0] sdram_addr,
+  // SDRAM data
+  output reg        sdram_dq_oe,
+  output reg [15:0] sdram_dq_o,
+  input      [15:0] sdram_dq_i
+);
+
+// SDRAM memory size
+parameter SDRAM_SIZE     = 8;
+// SDRAM operational frequency
+parameter SDRAM_FREQ     = 85909090;
+// Hidden refresh mode
+parameter HIDDEN_REFRESH = 0;
+// MODE REGISTER SET value (RS = 00, WB = 0, OP = 00, CL = 010, BT = 0, BL = 011)
+parameter MRS_VALUE = 12'b000000100011;
+// Refresh period
+parameter REF_COUNT = ((SDRAM_FREQ / ((12 * 64000)))) - 1;
+// Clock-to-output delay
+parameter Tco_dly = 4.5;
+
+// Port select signals
+reg   [2:0] r_psel;       // Port select (one hot)
+reg   [2:0] r_psel_dly;   // Port select delayed
+
+// Refresh signals
+reg         r_refr_req;   // Refresh requested
+reg         r_refr_act;   // Refresh active
+reg         r_refr_ack;   // Refresh acknowledged
+reg  [31:0] r_refr_ctr;   // Refresh counter
+
+// Port multiplexer signals
+wire        w_rden;       // Read enable
+reg         r_rd_reg;     // Registered read enable
+reg         r_rd_act;     // Read active
+wire        w_wren;       // Write enable
+reg         r_wr_reg;     // Registered write enable
+reg         r_wr_act;     // Write active
+wire        w_ram_sel;    // RAM select
+reg   [2:0] r_rd_bctr;    // Read burst counter
+reg   [2:0] r_wr_bctr;    // Write burst counter
+wire  [2:0] w_bst_siz;    // Burst size (load value of burst counters)
+reg   [2:0] r_bst_stp;    // Burst stop
+wire  [1:0] w_dqm;        // Bytes masks
+wire [23:1] w_addr;       // Address
+reg  [15:0] r_rddata;     // Data read
+wire [15:0] w_wrdata;     // Data written
+
+// SDRAM speed adjustment
+wire        w_rd_start;   // Read start condition
+wire        w_wr_start;   // Write start condition
+wire  [3:0] w_rd_cycle;   // First read cycle number
+
+// Initialization signals
+reg   [2:0] r_init_fsm;   // SDRAM initialization state machine
+reg  [10:0] r_init_tmr;   // SDRAM initialization timer
+
+// Output registers
+reg         r_sdram_cs_n;  // SDRAM chip select
+reg         r_sdram_ras_n; // SDRAM row address strobe
+reg         r_sdram_cas_n; // SDRAM column address strobe
+reg         r_sdram_we_n;  // SDRAM write enable
+reg   [1:0] r_sdram_dqm_n; // SDRAM DQ masks
+reg   [1:0] r_sdram_ba;    // SDRAM bank address
+reg  [11:0] r_sdram_addr;  // SDRAM address
+reg  [15:0] r_sdram_dq_o;  // SDRAM DQ output
+reg         r_sdram_dq_oe; // SDRAM DQ output enable
+
+  // Signal multiplexing based on the port select
+  assign w_wren         = (ap1_wren & r_psel[0])
+                        | (ap2_wren & r_psel[1])
+                        | (ap3_wren & r_psel[2]);
+  assign w_rden         = (ap1_rden & r_psel[0])
+                        | (ap2_rden & r_psel[1])
+                        | (ap3_rden & r_psel[2]);
+  assign w_ram_sel      = (HIDDEN_REFRESH == 1)
+                        ? (r_psel[0] | r_psel[1] | r_psel[2])
+                        : (r_psel[0] | r_psel[1] | r_psel[2]) & ~r_refr_req;
+  assign w_dqm[0]       = (ap1_bena[0] & r_psel[0])
+                        | (ap2_bena[0] & r_psel[1])
+                        | (ap3_bena[0] & r_psel[2]);
+  assign w_dqm[1]       = (ap1_bena[1] & r_psel[0])
+                        | (ap2_bena[1] & r_psel[1])
+                        | (ap3_bena[1] & r_psel[2]);
+  assign w_bst_siz[2]   = (ap1_bst_siz[2] & r_psel[0])
+                        | (ap2_bst_siz[2] & r_psel[1])
+                        | (ap3_bst_siz[2] & r_psel[2]);
+  assign w_bst_siz[1]   = (ap1_bst_siz[1] & r_psel[0])
+                        | (ap2_bst_siz[1] & r_psel[1])
+                        | (ap3_bst_siz[1] & r_psel[2]);
+  assign w_bst_siz[0]   = (ap1_bst_siz[0] & r_psel[0])
+                        | (ap2_bst_siz[0] & r_psel[1])
+                        | (ap3_bst_siz[0] & r_psel[2]);
+  assign w_addr[23:1]   = (ap1_address[23:1] & {23{r_psel[0]}})
+                        | (ap2_address[23:1] & {23{r_psel[1]}})
+                        | (ap3_address[23:1] & {23{r_psel[2]}});
+  assign w_wrdata[15:0] = (ap1_wrdata[15:0] & {16{r_psel[0]}})
+                        | (ap2_wrdata[15:0] & {16{r_psel[1]}})
+                        | (ap3_wrdata[15:0] & {16{r_psel[2]}});
+
+  // SDRAM speed adjustment
+  assign w_rd_cycle = (SDRAM_FREQ < 50000000) ? 4'd2 : 4'd3;
+  assign w_rd_start = (SDRAM_FREQ < 50000000) ? (seq_cyc[2] & r_rd_reg) : (seq_cyc[4] & r_rd_reg);
+  assign w_wr_start = (SDRAM_FREQ < 50000000) ? (seq_cyc[0] & w_wren & w_ram_sel) : (seq_cyc[1] & r_wr_reg);
+  
+  // Write burst active flags, one cycle before "r_wr_act"
+  assign ap1_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[0];
+  assign ap2_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[1];
+  assign ap3_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[2];
+  
+  // SDRAM data read
+  assign ap1_rddata = r_rddata;
+  assign ap2_rddata = r_rddata;
+  assign ap3_rddata = r_rddata;
+  
+  // Hidden refresh / port select :
+  //-------------------------------
+  // rst         : Global reset
+  // clk         : SDRAM controller clock
+  // seq_cyc     : Sequencer cycle (0 to 11)
+  // seq_ph      : Sequencer phase (0 or 1)
+  // r_refr_req  : Internal refresh cycle request
+  // r_refr_ack  : Internal refresh cycle acknowledge
+  // r_refr_ctr  : Internal refresh counter
+  // r_psel      : Port select (one hot)
+  // r_psel_dly  : Delayed port select
+  // ap1_ram_sel : Port #1 access
+  // ap2_ram_sel : Port #2 access
+  // ap3_ram_sel : Port #3 access
+  always @(posedge rst or posedge clk) begin
+    if (rst) begin
+      // Refresh counter
+      r_refr_ctr <= REF_COUNT;
+      // Refresh cycle request
+      r_refr_req <= 1'b0;
+    end else begin
+      // Hidden refresh case
+      if (HIDDEN_REFRESH == 1) begin
+        // Sequencer cycle #11
+        if (seq_cyc[11]) begin
+          // Internal refresh counter
+          if (r_refr_ctr == 0) begin
+            r_refr_req <= 1'b1;
+            r_refr_ctr <= REF_COUNT;
+          end
+          else begin
+            r_refr_ctr <= r_refr_ctr - 1;
+          end
+        end
+        // When refresh cycle is acknowledged
+        if (r_refr_ack == 1'b1) begin
+          // Clear the refresh cycle request
+          r_refr_req <= 1'b0;
+        end
+      end else begin
+        // External refresh
+        r_refr_req <= refr_cyc;
+      end
+    end
+    
+    if (rst) begin
+      // Port select
+      r_psel     <= 3'b000;
+      r_psel_dly <= 3'b000;
+    end else begin
+      // Access port select
+      if (seq_cyc[11]) begin
+        if (!seq_ph) begin
+          // Phase #0 : select port #1 (CPU) -> #3 (CTL) -> none
+          r_psel[0] <= ap1_ram_sel;
+          r_psel[1] <= 1'b0;
+          r_psel[2] <= ap3_ram_sel & ~ap1_ram_sel;
+        end
+        else begin
+          // Phase #1 : select port #2 (GPU) -> #1 (CPU) -> #3 (CTL) -> none
+          r_psel[0] <= ap1_ram_sel & ~ap2_ram_sel;
+          r_psel[1] <= ap2_ram_sel;
+          r_psel[2] <= ap3_ram_sel & ~(ap1_ram_sel | ap2_ram_sel);
+        end
+      end
+      // Delayed port select for data read multiplexer
+      if (seq_cyc[1]) begin
+        r_psel_dly <= r_psel;
+      end
+    end
+  end
+
+  // Burst activities :
+  //-------------------
+  // rst        : Global reset
+  // clk        : SDRAM controller clock
+  // w_rd_start : Read start conditions
+  // w_wr_start : Write start conditions
+  // r_rd_reg   : Read mode (registered)
+  // r_rd_act   : Read active
+  // r_wr_act   : Write active
+  // r_rd_bctr  : Burst read counter
+  // r_wr_bctr  : Burst write counter
+  // r_psel_dly : Port select delayed
+  always @(posedge rst or posedge clk) begin
+    if (rst) begin
+      // Burst signals
+      r_rd_act       <= 1'b0;
+      r_wr_act       <= 1'b0;
+      r_rd_bctr      <= 3'b000;
+      r_wr_bctr      <= 3'b000;
+      ap1_rd_bst_act <= 1'b0;
+      ap2_rd_bst_act <= 1'b0;
+      ap3_rd_bst_act <= 1'b0;
+      // Data bus
+      r_rddata       <= 16'h0000;
+      r_sdram_dqm_n  <= 2'b11;
+      r_sdram_dq_oe  <= 1'b0;
+      r_sdram_dq_o   <= 16'h0000;
+    end else begin
+      // Prepare write burst cycles
+      if (w_wr_start) begin
+        // Set the active bits
+        r_wr_act  <= 1'b1;
+        // Start the burst counter
+        r_wr_bctr <= w_bst_siz;
+      end
+      // Prepare read burst cycles
+      if (w_rd_start) begin
+        // Set the active bits
+        r_rd_act  <= 1'b1;
+        // Start the burst counter
+        r_rd_bctr <= r_bst_stp;
+      end
+      // Read burst counter management
+      if (r_rd_act) begin
+        if (r_rd_bctr == 0) begin
+          // Burst finished : clear the active bit
+          r_rd_act <= 1'b0;
+        end
+        else begin
+          r_rd_bctr <= r_rd_bctr - 3'b1;
+        end
+      end
+      // Write burst counter management
+      if (r_wr_act) begin
+        if (r_wr_bctr == 0) begin
+          // Burst finished : clear the active bit
+          r_wr_act <= 1'b0;
+        end
+        else begin
+          r_wr_bctr <= r_wr_bctr - 3'b1;
+        end
+      end
+      // Read burst active flags, one cycle after "r_rd_act"
+      ap1_rd_bst_act <= r_rd_act & r_psel_dly[0];
+      ap2_rd_bst_act <= r_rd_act & r_psel_dly[1];
+      ap3_rd_bst_act <= r_rd_act & r_psel_dly[2];
+      // Read SDRAM data
+      r_rddata <= sdram_dq_i;
+      // Write SDRAM data / DQM management
+      if (r_wr_act) begin
+        r_sdram_dqm_n[0] <= ~w_dqm[0];
+        r_sdram_dqm_n[1] <= ~w_dqm[1];
+        r_sdram_dq_oe    <= 1'b1;
+        r_sdram_dq_o     <= w_wrdata;
+      end
+      else begin
+        r_sdram_dqm_n[0] <= ~r_rd_reg;
+        r_sdram_dqm_n[1] <= ~r_rd_reg;
+        r_sdram_dq_oe    <= 1'b0;
+        r_sdram_dq_o     <= 16'h0000;
+      end
+    end
+  end
+
+  // SDRAM controller state machine :
+  //---------------------------------
+  //  rst        : Global reset
+  //  clk        : SDRAM controller clock
+  //  seq_cyc    : Sequencer cycle
+  //  r_refr_req : Refresh cycle requested
+  //  r_refr_act : Refresh cycle active
+  //  r_refr_ack : Refresh cycle acknowledge
+  //  w_ram_sel  : SDRAM selected
+  //  w_rden     : Read enable flag
+  //  w_wren     : Write enable flag
+  //  r_rd_reg   : Read mode (registered)
+  //  r_wr_reg   : Write mode (registered)
+  //  w_bst_siz  : Burst size (1 to 8 words)
+  //  r_bst_stp  : Burst stop cycle
+  //  r_init_fsm : SDRAM initialization state
+  //  r_init_tmr : SDRAM initialization timer (>100 us)
+  always @(posedge rst or posedge clk) begin
+    if (rst) begin
+      // SDRAM outputs
+      r_sdram_cs_n  <= 1'b1;
+      r_sdram_ras_n <= 1'b1;
+      r_sdram_cas_n <= 1'b1;
+      r_sdram_we_n  <= 1'b1;
+      r_sdram_ba    <= 2'b00;
+      r_sdram_addr  <= 12'b000000000000;
+      // Controller state
+      r_rd_reg      <= 1'b0;
+      r_wr_reg      <= 1'b0;
+      r_bst_stp     <= 3'b000;
+      sdram_rdy     <= 1'b0;
+      r_refr_ack    <= 1'b0;
+      r_refr_act    <= 1'b0;
+      // 1024 * 12 cycles > 100 us
+      r_init_tmr    <= 11'd0;    // 143 us
+      r_init_fsm    <= 3'b000;
+    end else begin
+      // Default : NOPs
+      r_sdram_ras_n <= 1'b1;
+      r_sdram_cas_n <= 1'b1;
+      r_sdram_we_n  <= 1'b1;
+      if (r_init_fsm[2]) begin
+        // Chip select management
+        if (seq_cyc[0]) begin
+          // RAM selected or refresh request
+          r_sdram_cs_n <= ~(w_ram_sel | r_refr_req);
+        end
+        // If there is an active refresh
+        if (r_refr_act) begin
+          //------------------
+          // Refresh cycles --
+          //------------------
+          // Cycle #0 : clear read/write enable signals
+          r_rd_reg <= 1'b0;
+          r_wr_reg <= 1'b0;
+          // Cycle #2 : prepare AUTO REFRESH cmd for cycle #3
+          if (seq_cyc[2]) begin
+            r_sdram_ras_n <= 1'b0;
+            r_sdram_cas_n <= 1'b0;
+          end
+          // Cycle #9 : acknowledge the refresh request
+          if (seq_cyc[9]) begin
+            // Hidden refresh case
+            if (HIDDEN_REFRESH == 1) begin
+              r_refr_ack <= 1'b1;
+            end
+            r_refr_act <= 1'b0;
+          end
+        end
+        else begin
+          //-----------------
+          // Normal cycles --
+          //-----------------
+          // Hidden refresh case
+          if (HIDDEN_REFRESH == 1) begin
+            // Clear any refresh acknowledge
+            r_refr_ack <= 1'b0;
+          end
+          if (seq_cyc[0]) begin
+            // If no access, activate refresh
+            r_refr_act <= ~((w_rden | w_wren) & w_ram_sel) & r_refr_req;
+            // Register read/write enable signals
+            r_rd_reg   <= w_rden & w_ram_sel;
+            r_wr_reg   <= w_wren & w_ram_sel;
+            // Register the burst stop
+            r_bst_stp  <= w_bst_siz;
+          end
+          // Cycle #0 : prepare ACTIVATE cmd for cycle #1
+          //            set the row address and the bank number
+          if ((seq_cyc[0]) && (w_ram_sel) && ((w_rden) || (w_wren))) begin
+            r_sdram_ras_n <= 1'b0;
+            if (SDRAM_SIZE == 16) begin
+              // 4096 rows : 12 address lines
+              r_sdram_addr  <= w_addr[23:12];
+              // 4 banks : 2 address lines
+              r_sdram_ba    <= w_addr[11:10];
+            end else begin
+              // 4096 rows : 12 address lines
+              r_sdram_addr  <= w_addr[22:11];
+              // 4 banks : 2 address lines
+              r_sdram_ba    <= w_addr[10:9];
+            end
+          end
+          // Cycle #1/2 : prepare READ/WRITE cmd for next cycle
+          //              set the column address and the bank number
+          if ((seq_cyc[w_rd_cycle - 1]) && ((r_rd_reg) || (r_wr_reg))) begin
+            r_sdram_cas_n <= 1'b0;
+            r_sdram_we_n  <= ~r_wr_reg;
+            if (SDRAM_SIZE == 16)
+              // 512 columns : 9 address lines
+              r_sdram_addr  <= {3'b010, w_addr[9:1]};
+            else
+              // 256 columns : 8 address lines
+              r_sdram_addr  <= {4'b0100, w_addr[8:1]};
+          end
+          // Cycles #2/3+ : prepare the PRECHARGE cmd (burst stop)
+          //if ((seq_cyc[w_rd_cycle + r_bst_stp]) && ((r_rd_reg) || (r_wr_reg))) begin
+          //  r_sdram_ras_n <= 1'b0;
+          //  r_sdram_we_n  <= 1'b0;
+          //end
+        end
+      end
+      else begin
+        //---------------
+        // Init cycles --
+        //---------------
+        if (r_init_tmr[10]) begin
+          // Select SDRAM
+          r_sdram_cs_n <= 1'b0;
+          case (r_init_fsm[1:0])
+            2'd0 : begin
+              // Prepare PRECHARGE ALL cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n    <= 1'b0;
+                r_sdram_we_n     <= 1'b0;
+                r_sdram_addr[10] <= 1'b1;
+              end
+            end
+            2'd1 : begin
+              // Prepare AUTO REFRESH cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n <= 1'b0;
+                r_sdram_cas_n <= 1'b0;
+              end
+            end
+            2'd2 : begin
+              // Prepare AUTO REFRESH cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n <= 1'b0;
+                r_sdram_cas_n <= 1'b0;
+              end
+            end
+            2'd3 : begin
+              // Prepare MODE REGISTER SET value
+              if (seq_cyc[1]) begin
+                r_sdram_addr <= MRS_VALUE;
+              end
+              // Prepare MODE REGISTER SET cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n <= 1'b0;
+                r_sdram_cas_n <= 1'b0;
+                r_sdram_we_n  <= 1'b0;
+              end
+              // SDRAM is initialized
+              if (seq_cyc[10]) begin
+                sdram_rdy <= 1'b1;
+              end
+            end
+            default : begin
+            end
+          endcase
+          // Cycle #11 : next state
+          if (seq_cyc[11]) begin
+            r_init_fsm <= r_init_fsm + 3'd1;
+          end
+        end
+        else begin
+          // Deselect SDRAM
+          r_sdram_cs_n <= 1'b1;
+          // Cycle #11 : timer management
+          if (seq_cyc[11]) begin
+            r_init_tmr <= r_init_tmr + 11'd1;
+          end
+        end
+      end
+    end
+  end
+  
+  // TCO delay on all outputs
+  always@(r_sdram_cs_n or r_sdram_ras_n or r_sdram_cas_n or r_sdram_we_n or
+          r_sdram_dqm_n or r_sdram_ba or r_sdram_addr or r_sdram_dq_oe or r_sdram_dq_o) begin
+  `ifdef SIMULATION
+  
+    `ifdef verilator3
+      // Cycle based simulation
+      sdram_cs_n   = r_sdram_cs_n;
+      sdram_ras_n  = r_sdram_ras_n;
+      sdram_cas_n  = r_sdram_cas_n;
+      sdram_we_n   = r_sdram_we_n;
+      sdram_dqm_n  = r_sdram_dqm_n;
+      sdram_ba     = r_sdram_ba;
+      sdram_addr   = r_sdram_addr;
+      sdram_dq_oe  = r_sdram_dq_oe;
+      sdram_dq_o   = r_sdram_dq_o;
+    `else
+      // Timing based simulation
+      sdram_cs_n   = #Tco_dly r_sdram_cs_n;
+      sdram_ras_n  = #Tco_dly r_sdram_ras_n;
+      sdram_cas_n  = #Tco_dly r_sdram_cas_n;
+      sdram_we_n   = #Tco_dly r_sdram_we_n;
+      sdram_dqm_n  = #Tco_dly r_sdram_dqm_n;
+      sdram_ba     = #Tco_dly r_sdram_ba;
+      sdram_addr   = #Tco_dly r_sdram_addr;
+      sdram_dq_oe  = #Tco_dly r_sdram_dq_oe;
+      sdram_dq_o   = #Tco_dly r_sdram_dq_o;
+    `endif
+    
+  `else
+    // Synthesis
+    sdram_cs_n   = r_sdram_cs_n;
+    sdram_ras_n  = r_sdram_ras_n;
+    sdram_cas_n  = r_sdram_cas_n;
+    sdram_we_n   = r_sdram_we_n;
+    sdram_dqm_n  = r_sdram_dqm_n;
+    sdram_ba     = r_sdram_ba;
+    sdram_addr   = r_sdram_addr;
+    sdram_dq_oe  = r_sdram_dq_oe;
+    sdram_dq_o   = r_sdram_dq_o;
+  `endif
+  end
+
+`ifdef SIMULATION
+
+`ifndef verilator3
+  // Setup and hold times check for DQ
+  reg r_dq_noti;
+
+  specify
+    specparam
+      Tsu_dly =  0.7, // Input setup time
+      Th_dly  = -0.5; // Input hold time
+    $setuphold(posedge clk, sdram_dq_i, Tsu_dly, Th_dly, r_dq_noti);
+  endspecify
+
+  always @(r_dq_noti)
+  begin
+    $display($realtime, " ns : Setup/Hold time violation on DQ inputs");
+  end
+`endif
+  
+`endif
+
+endmodule
+
+/* verilator tracing_off */
Index: mcctv/sdram_statemachine_mcc.vhdl
===================================================================
--- mcctv/sdram_statemachine_mcc.vhdl	(nonexistent)
+++ mcctv/sdram_statemachine_mcc.vhdl	(revision 181)
@@ -0,0 +1,480 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine_mcc;
+
+ARCHITECTURE vhdl OF sdram_statemachine_mcc IS
+component sdram_ctrl
+port
+(
+--    //-----------------------------
+--    // Clock and reset
+--    //-----------------------------
+--    input         rst,             // Global reset
+--    input         clk,             // Master clock (72 MHz)
+--    
+--    output        ram_rdy_n,       // SDRAM ready
+--    output        ram_ref,         // SDRAM refresh
+--    output  [3:0] ram_cyc,         // SDRAM cycles
+--    output  [3:0] ram_ph,          // SDRAM phases
+--    output  [8:0] ram_ph_ctr,      // Phase counter
+    rst : in std_logic;
+	 clk : in std_logic;
+	 
+	 ram_rdy_n : out std_logic;
+	 ram_ref : out std_logic;
+	 ram_cyc : out std_logic_vector(3 downto 0);
+	 ram_ph : out std_logic_vector(3 downto 0);
+	 ram_ph_ctr : out std_logic_vector(8 downto 0);
+	
+	rden_b0 : in std_logic;
+	wren_b0 : in std_logic;
+	addr_b0 : in std_logic_vector(22 downto 2);
+	valid_b0 : out std_logic;
+	fetch_b0 : out std_logic;
+	rdata_b0 : out std_logic_vector(15 downto 0);
+	wdata_b0 : in std_logic_vector(15 downto 0);
+	bena_b0 : in std_logic_vector(1 downto 0);
+
+	rden_b1 : in std_logic;
+	wren_b1 : in std_logic;
+	addr_b1 : in std_logic_vector(22 downto 2);
+	valid_b1 : out std_logic;
+	fetch_b1 : out std_logic;
+	rdata_b1 : out std_logic_vector(15 downto 0);
+	wdata_b1 : in std_logic_vector(15 downto 0);
+	bena_b1 : in std_logic_vector(1 downto 0);
+
+	rden_b2 : in std_logic;
+	wren_b2 : in std_logic;
+	addr_b2 : in std_logic_vector(22 downto 2);
+	valid_b2 : out std_logic;
+	fetch_b2 : out std_logic;
+	rdata_b2 : out std_logic_vector(15 downto 0);
+	wdata_b2 : in std_logic_vector(15 downto 0);
+	bena_b2 : in std_logic_vector(1 downto 0);
+
+	rden_b3 : in std_logic;
+	wren_b3 : in std_logic;
+	addr_b3 : in std_logic_vector(22 downto 2);
+	valid_b3 : out std_logic;
+	fetch_b3 : out std_logic;
+	rdata_b3 : out std_logic_vector(15 downto 0);
+	wdata_b3 : in std_logic_vector(15 downto 0);
+	bena_b3 : in std_logic_vector(1 downto 0);
+	
+--    //-----------------------------
+--    // Access bank #0
+--    //-----------------------------
+--    input         rden_b0,         // Read enable
+--    input         wren_b0,         // Write enable
+--    input  [22:2] addr_b0,         // Address (up to 8 MB)
+--    output        valid_b0,        // Read data valid
+--    output        fetch_b0,        // Write data fetch
+--    output [15:0] rdata_b0,        // Read data
+--    input  [15:0] wdata_b0,        // Write data
+--    input   [1:0] bena_b0,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #1
+--    //-----------------------------
+--    input         rden_b1,         // Read enable
+--    input         wren_b1,         // Write enable
+--    input  [22:2] addr_b1,         // Address (up to 8 MB)
+--    output        valid_b1,        // Read data valid
+--    output        fetch_b1,        // Write data fetch
+--    output [15:0] rdata_b1,        // Read data
+--    input  [15:0] wdata_b1,        // Write data
+--    input   [1:0] bena_b1,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #2
+--    //-----------------------------
+--    input         rden_b2,         // Read enable
+--    input         wren_b2,         // Write enable
+--    input  [22:2] addr_b2,         // Address (up to 8 MB)
+--    output        valid_b2,        // Read data valid
+--    output        fetch_b2,        // Write data fetch
+--    output [15:0] rdata_b2,        // Read data
+--    input  [15:0] wdata_b2,        // Write data
+--    input   [1:0] bena_b2,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #3
+--    //-----------------------------
+--    input         rden_b3,         // Read enable
+--    input         wren_b3,         // Write enable
+--    input  [22:2] addr_b3,         // Address (up to 8 MB)
+--    output        valid_b3,        // Read data valid
+--    output        fetch_b3,        // Write data fetch
+--    output [15:0] rdata_b3,        // Read data
+--    input  [15:0] wdata_b3,        // Write data
+--    input   [1:0] bena_b3,         // Byte enable
+    
+--    //-----------------------------
+--    // SDRAM memory signals
+--    //-----------------------------
+--    output            sdram_cs_n,  // SDRAM chip select
+--    output reg        sdram_ras_n, // SDRAM row address strobe
+--    output reg        sdram_cas_n, // SDRAM column address strobe
+--    output reg        sdram_we_n,  // SDRAM write enable
+--    //
+--    output reg  [1:0] sdram_ba,    // SDRAM bank address
+--    output reg [12:0] sdram_addr,  // SDRAM address
+--    //
+--    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+--    output reg        sdram_dq_oe, // SDRAM data output enable
+--    output reg [31:0] sdram_dq_o,  // SDRAM data output
+--    input      [31:0] sdram_dq_i   // SDRAM data input
+
+	sdram_cs_n : out std_logic;
+	sdram_ras_n : out std_logic;
+	sdram_cas_n : out std_logic;
+	sdram_we_n : out std_logic;
+	sdram_ba : out std_logic_vector(1 downto 0);
+	sdram_addr : out std_logic_vector(12 downto 0);
+	sdram_dqm_n : out std_logic_vector(3 downto 0);
+	sdram_dq_oe : out std_logic;
+	sdram_dq_o : out std_logic_vector(31 downto 0);
+	sdram_dq_i : in std_logic_vector(31 downto 0)
+);
+end component;
+
+signal SDRAM_CKE_dummy : std_logic;
+
+signal sdram_valid_b0_dummy : std_logic;
+signal sdram_valid_b1_dummy : std_logic;
+signal sdram_valid_b2_dummy : std_logic;
+signal sdram_valid_b3_dummy : std_logic;
+
+signal sdram_fetch_b0_dummy : std_logic;
+signal sdram_fetch_b1_dummy : std_logic;
+signal sdram_fetch_b2_dummy : std_logic;
+signal sdram_fetch_b3_dummy : std_logic;
+
+signal sdram_read_b0_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b1_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b2_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b3_dummy : std_logic_vector(15 downto 0);
+
+signal reset : std_logic;
+
+signal sdram_ctl_rdy_dummy : std_logic;
+signal sdram_ctl_ref_dummy : std_logic;
+signal sdram_ctl_cyc_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_ctr_dummy : std_logic_vector(8 downto 0);
+
+signal SDRAM_VALID : std_logic;
+signal SDRAM_FETCH : std_logic;
+
+signal SDRAM_dq_oe : std_logic;
+signal sdram_dq_o : std_logic_vector(31 downto 0);
+signal sdram_dq_i : std_logic_vector(31 downto 0);
+signal sdram_dqm_N_temp : std_logic_vector(3 downto 0);
+
+signal sdram_ba : std_logic_vector(1 downto 0);
+
+signal sdram_enable_byte : std_logic_vector(1 downto 0);
+
+signal sdram_reply_reg : std_logic;
+signal state_reg : std_logic_vector(2 downto 0);
+signal store_data_in_reg : std_logic_vector(47 downto 0);
+signal data_out_reg : std_logic_vector(31 downto 0);
+signal sdram_reply_next : std_logic;
+signal state_next : std_logic_vector(2 downto 0);
+signal store_data_in_next : std_logic_vector(47 downto 0);
+signal data_out_next : std_logic_vector(31 downto 0);
+
+constant state_idle : std_logic_vector(2 downto 0) := "000";
+constant state_write_wait_1 : std_logic_vector(2 downto 0) := "001";
+constant state_write_wait_2 : std_logic_vector(2 downto 0) := "010";
+constant state_write_wait_3 : std_logic_vector(2 downto 0) := "111";
+constant state_read_wait_1 : std_logic_vector(2 downto 0) := "011";
+constant state_read_wait_2 : std_logic_vector(2 downto 0) := "100";
+constant state_read_wait_3 : std_logic_vector(2 downto 0) := "101";
+constant state_read_wait_4 : std_logic_vector(2 downto 0) := "110";
+
+
+signal internal_data_in : std_logic_vector(15 downto 0);
+signal internal_data_out : std_logic_vector(15 downto 0);
+
+signal write_en_next : std_logic;
+signal write_en_reg : std_logic;
+
+signal read_en_next : std_logic;
+signal read_en_reg : std_logic;
+
+signal SDRAM_ADDR_temp : std_logic_vector(12 downto 0);
+
+begin
+
+
+reset <= not(reset_n);
+
+process(clk_system, reset_n)
+begin
+	if (reset_n = '0') then
+		sdram_reply_reg <= '0';
+		state_reg <= state_idle;
+		store_data_in_reg <= (others=>'0');
+		data_out_reg <= (others=>'0');
+		write_en_reg <= '0';
+		read_en_reg <= '0';
+	elsif (clk_system'event and clk_system = '1') then
+		sdram_reply_reg <= sdram_reply_next;
+		state_reg <= state_next;
+		store_data_in_reg <= store_data_in_next;
+		data_out_reg <= data_out_next;
+		write_en_reg <= write_en_next;
+		read_en_reg <= read_en_next;		
+	end if;
+end process;	
+
+data_out <= data_out_reg;
+reply <= sdram_reply_reg;
+
+process(read_en_reg, write_en_reg, state_reg, request, write_en, store_data_in_reg, internal_data_in, data_in, sdram_reply_reg, byte_access, longword_access, address_in, sdram_valid, sdram_fetch)
+begin
+	sdram_reply_next <= sdram_reply_reg;
+	state_next <= state_reg;
+	store_data_in_next <= store_data_in_reg;
+	data_out_next <= (others=>'0');
+	
+	read_en_next <= read_en_reg;
+	write_en_next <= write_en_reg;
+	
+	internal_data_out <= (others=>'0');
+	sdram_enable_byte <= "11";
+
+	case state_reg is
+	when state_idle => 
+		sdram_reply_next <= '0';
+		if (request = '1') then
+			if (write_en = '1') then
+				-- 4 byte write
+				state_next <= state_write_wait_1;
+				write_en_next <= '1';
+			else
+				-- 8 byte read
+				state_next <= state_read_wait_1;
+				read_en_next <= '1';
+				-- TODO - read from cached?
+			end if;
+		end if;
+	when state_write_wait_1 =>
+		if (sdram_fetch = '1') then
+			state_next <= state_write_wait_2;
+		end if;
+		internal_data_out <= data_in(31 downto 16);
+	when state_write_wait_2 =>
+		state_next <= state_write_wait_3;
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "01";
+			when "01" =>	
+				sdram_enable_byte <= "10";				
+			when "10" =>
+				sdram_enable_byte <= "00";								
+			when "11" =>	
+				sdram_enable_byte <= "00";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(15 downto 0);
+		end if;
+		sdram_reply_next <= '1';	
+	when state_write_wait_3 =>
+		state_next <= state_idle;
+		write_en_next <= '0';		
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "00";
+			when "01" =>	
+				sdram_enable_byte <= "00";				
+			when "10" =>
+				sdram_enable_byte <= "01";								
+			when "11" =>	
+				sdram_enable_byte <= "10";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(31 downto 16);
+		end if;
+		sdram_reply_next <= '0';
+	when state_read_wait_1 =>
+		if (sdram_valid = '1') then
+			state_next <= state_read_wait_2;
+			store_data_in_next(15 downto 0) <= internal_data_in;
+		end if;
+	when state_read_wait_2 =>
+		state_next <= state_read_wait_3;
+		store_data_in_next(31 downto 16) <= internal_data_in;
+	when state_read_wait_3 =>
+		state_next <= state_read_wait_4;
+		store_data_in_next(47 downto 32) <= internal_data_in;
+	when state_read_wait_4 =>
+		read_en_next <= '0';
+		state_next <= state_idle;
+		--store_data_in_next(63 downto 48) <= internal_data_in;
+		sdram_reply_next <= '1';
+		if (byte_access = '1') then
+			case address_in(2 downto 0) is
+			when "000" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(7 downto 0);
+			when "001" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(15 downto 8);
+			when "010" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(23 downto 16);
+			when "011" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(31 downto 24);
+			when "100" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(39 downto 32);
+			when "101" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(47 downto 40);
+			when "110" =>
+				data_out_next(7 downto 0) <= internal_data_in(7 downto 0);
+			when "111" =>
+				data_out_next(7 downto 0) <= internal_data_in(15 downto 8);
+			end case;
+		elsif (longword_access = '1') then
+			case address_in(2 downto 0) is -- aligned only!
+			when "000" =>
+				data_out_next <= store_data_in_reg(31 downto 0);
+			when "100" =>
+				data_out_next <= internal_data_in&store_data_in_reg(47 downto 32);
+			when others =>
+				-- NOP
+			end case;		
+		end if;
+	end case;	
+end process;
+
+
+sdram_mcc : sdram_ctrl 
+	PORT map
+	(
+		rst => reset,
+		clk => clk_SYSTEM,
+		
+		ram_rdy_n => sdram_ctl_rdy_dummy,
+		ram_ref => sdram_ctl_ref_dummy,
+		ram_cyc => sdram_ctl_cyc_dummy,
+		ram_ph => sdram_ctl_ph_dummy,
+		ram_ph_ctr => sdram_ctl_ph_ctr_dummy,
+
+		 --BYTE_ACCESS : IN STD_LOGIC;
+		 --WORD_ACCESS : IN STD_LOGIC;
+		 --LONGWORD_ACCESS : IN STD_LOGIC;		
+		 
+		rden_b0 => READ_EN_reg,
+		wren_b0 => WRITE_EN_reg,
+		addr_b0 => ADDRESS_IN(22 downto 2),
+		valid_b0 => SDRAM_VALID,
+		fetch_b0 => SDRAM_FETCH,
+		rdata_b0 => INTERNAL_DATA_IN(15 downto 0),
+		wdata_b0 => INTERNAL_DATA_OUT(15 downto 0),
+		bena_b0 => sdram_enable_byte,
+
+		rden_b1 => '0',
+		wren_b1 => '0',
+		addr_b1 => (others=>'0'),
+		valid_b1 => sdram_valid_b1_dummy,
+		fetch_b1 => sdram_fetch_b1_dummy,
+		rdata_b1 => sdram_read_b1_dummy,
+		wdata_b1 => (others=>'0'),
+		bena_b1 => "00",
+
+		rden_b2 => '0',
+		wren_b2 => '0',
+		addr_b2 => (others=>'0'),
+		valid_b2 => sdram_valid_b2_dummy,
+		fetch_b2 => sdram_fetch_b2_dummy,
+		rdata_b2 => sdram_read_b2_dummy,
+		wdata_b2 => (others=>'0'),
+		bena_b2 => "00",
+
+		rden_b3 => '0',
+		wren_b3 => '0',
+		addr_b3 => (others=>'0'),
+		valid_b3 => sdram_valid_b3_dummy,
+		fetch_b3 => sdram_fetch_b3_dummy,		
+		rdata_b3 => sdram_read_b3_dummy,
+		wdata_b3 => (others=>'0'),
+		bena_b3 => "00",	
+		
+		sdram_cs_n => SDRAM_CS_N,
+		sdram_ras_n => SDRAM_RAS_N,
+		sdram_cas_n => SDRAM_CAS_N,
+		sdram_we_n => SDRAM_WE_N,
+		sdram_ba => SDRAM_BA,
+		sdram_addr => SDRAM_ADDR_temp,
+		sdram_dqm_n => sdram_dqm_N_temp,
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+);
+sdram_dq <= sdram_dq_o(15 downto 0) when sdram_dq_oe='1' else (others=>'Z');
+sdram_dq_i(15 downto 0) <= sdram_dq;
+sdram_dq_i(31 downto 16) <= (others=>'0');
+SDRAM_LDQM<= sdram_dqm_N_temp(0);
+SDRAM_UDQM<= sdram_dqm_N_temp(1);
+SDRAM_BA0 <= sdram_ba(0);
+SDRAM_BA1 <= sdram_ba(1);
+
+SDRAM_ADDR(12) <= '1';
+SDRAM_ADDR(11 downto 0) <= SDRAM_ADDR_temp(11 downto 0);
+
+end vhdl;
\ No newline at end of file
Index: mcctv/svideo/sin_rom.mif
===================================================================
--- mcctv/svideo/sin_rom.mif	(nonexistent)
+++ mcctv/svideo/sin_rom.mif	(revision 181)
@@ -0,0 +1,2054 @@
+WIDTH=8;
+DEPTH=2048;
+ADDRESS_RADIX=UNS;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+    0      : 00;
+    1      : 00;
+    2      : 00;
+    3      : 00;
+    4      : 00;
+    5      : 00;
+    6      : 00;
+    7      : 00;
+    8      : 00;
+    9      : 00;
+    10     : 00;
+    11     : 00;
+    12     : 00;
+    13     : 00;
+    14     : 00;
+    15     : 01;
+    16     : 00;
+    17     : 00;
+    18     : 00;
+    19     : 01;
+    20     : 01;
+    21     : 01;
+    22     : 01;
+    23     : 02;
+    24     : 00;
+    25     : 00;
+    26     : 01;
+    27     : 01;
+    28     : 02;
+    29     : 02;
+    30     : 02;
+    31     : 03;
+    32     : 00;
+    33     : 01;
+    34     : 01;
+    35     : 02;
+    36     : 03;
+    37     : 03;
+    38     : 03;
+    39     : 04;
+    40     : 00;
+    41     : 01;
+    42     : 02;
+    43     : 03;
+    44     : 03;
+    45     : 04;
+    46     : 04;
+    47     : 05;
+    48     : 00;
+    49     : 01;
+    50     : 02;
+    51     : 03;
+    52     : 04;
+    53     : 05;
+    54     : 05;
+    55     : 06;
+    56     : 00;
+    57     : 02;
+    58     : 03;
+    59     : 04;
+    60     : 05;
+    61     : 06;
+    62     : 06;
+    63     : 07;
+    64     : 00;
+    65     : 02;
+    66     : 03;
+    67     : 05;
+    68     : 06;
+    69     : 07;
+    70     : 07;
+    71     : 08;
+    72     : 00;
+    73     : 02;
+    74     : 04;
+    75     : 05;
+    76     : 06;
+    77     : 07;
+    78     : 08;
+    79     : 09;
+    80     : 00;
+    81     : 02;
+    82     : 04;
+    83     : 06;
+    84     : 07;
+    85     : 08;
+    86     : 09;
+    87     : 0A;
+    88     : 01;
+    89     : 03;
+    90     : 05;
+    91     : 07;
+    92     : 08;
+    93     : 09;
+    94     : 0A;
+    95     : 0B;
+    96     : 01;
+    97     : 03;
+    98     : 05;
+    99     : 07;
+    100    : 09;
+    101    : 0A;
+    102    : 0B;
+    103    : 0C;
+    104    : 01;
+    105    : 03;
+    106    : 06;
+    107    : 08;
+    108    : 0A;
+    109    : 0B;
+    110    : 0C;
+    111    : 0D;
+    112    : 01;
+    113    : 04;
+    114    : 06;
+    115    : 08;
+    116    : 0A;
+    117    : 0C;
+    118    : 0D;
+    119    : 0E;
+    120    : 01;
+    121    : 04;
+    122    : 07;
+    123    : 09;
+    124    : 0B;
+    125    : 0D;
+    126    : 0E;
+    127    : 0F;
+    128    : 01;
+    129    : 04;
+    130    : 07;
+    131    : 0A;
+    132    : 0C;
+    133    : 0E;
+    134    : 0F;
+    135    : 10;
+    136    : 01;
+    137    : 04;
+    138    : 08;
+    139    : 0A;
+    140    : 0D;
+    141    : 0F;
+    142    : 10;
+    143    : 11;
+    144    : 01;
+    145    : 05;
+    146    : 08;
+    147    : 0B;
+    148    : 0D;
+    149    : 0F;
+    150    : 11;
+    151    : 12;
+    152    : 01;
+    153    : 05;
+    154    : 08;
+    155    : 0C;
+    156    : 0E;
+    157    : 10;
+    158    : 12;
+    159    : 13;
+    160    : 01;
+    161    : 05;
+    162    : 09;
+    163    : 0C;
+    164    : 0F;
+    165    : 11;
+    166    : 13;
+    167    : 14;
+    168    : 02;
+    169    : 06;
+    170    : 09;
+    171    : 0D;
+    172    : 10;
+    173    : 12;
+    174    : 14;
+    175    : 15;
+    176    : 02;
+    177    : 06;
+    178    : 0A;
+    179    : 0E;
+    180    : 11;
+    181    : 13;
+    182    : 15;
+    183    : 16;
+    184    : 02;
+    185    : 06;
+    186    : 0A;
+    187    : 0E;
+    188    : 11;
+    189    : 14;
+    190    : 16;
+    191    : 17;
+    192    : 02;
+    193    : 07;
+    194    : 0B;
+    195    : 0F;
+    196    : 12;
+    197    : 15;
+    198    : 17;
+    199    : 18;
+    200    : 02;
+    201    : 07;
+    202    : 0B;
+    203    : 0F;
+    204    : 13;
+    205    : 16;
+    206    : 18;
+    207    : 19;
+    208    : 02;
+    209    : 07;
+    210    : 0C;
+    211    : 10;
+    212    : 14;
+    213    : 17;
+    214    : 19;
+    215    : 1A;
+    216    : 02;
+    217    : 07;
+    218    : 0C;
+    219    : 11;
+    220    : 14;
+    221    : 17;
+    222    : 19;
+    223    : 1B;
+    224    : 02;
+    225    : 08;
+    226    : 0D;
+    227    : 11;
+    228    : 15;
+    229    : 18;
+    230    : 1A;
+    231    : 1C;
+    232    : 02;
+    233    : 08;
+    234    : 0D;
+    235    : 12;
+    236    : 16;
+    237    : 19;
+    238    : 1B;
+    239    : 1D;
+    240    : 02;
+    241    : 08;
+    242    : 0E;
+    243    : 13;
+    244    : 17;
+    245    : 1A;
+    246    : 1C;
+    247    : 1E;
+    248    : 03;
+    249    : 09;
+    250    : 0E;
+    251    : 13;
+    252    : 18;
+    253    : 1B;
+    254    : 1D;
+    255    : 1F;
+    256    : 03;
+    257    : 09;
+    258    : 0F;
+    259    : 14;
+    260    : 18;
+    261    : 1C;
+    262    : 1E;
+    263    : 20;
+    264    : 03;
+    265    : 09;
+    266    : 0F;
+    267    : 15;
+    268    : 19;
+    269    : 1D;
+    270    : 1F;
+    271    : 21;
+    272    : 03;
+    273    : 09;
+    274    : 10;
+    275    : 15;
+    276    : 1A;
+    277    : 1E;
+    278    : 20;
+    279    : 22;
+    280    : 03;
+    281    : 0A;
+    282    : 10;
+    283    : 16;
+    284    : 1B;
+    285    : 1F;
+    286    : 21;
+    287    : 23;
+    288    : 03;
+    289    : 0A;
+    290    : 11;
+    291    : 16;
+    292    : 1B;
+    293    : 1F;
+    294    : 22;
+    295    : 24;
+    296    : 03;
+    297    : 0A;
+    298    : 11;
+    299    : 17;
+    300    : 1C;
+    301    : 20;
+    302    : 23;
+    303    : 25;
+    304    : 03;
+    305    : 0B;
+    306    : 11;
+    307    : 18;
+    308    : 1D;
+    309    : 21;
+    310    : 24;
+    311    : 26;
+    312    : 03;
+    313    : 0B;
+    314    : 12;
+    315    : 18;
+    316    : 1E;
+    317    : 22;
+    318    : 25;
+    319    : 27;
+    320    : 03;
+    321    : 0B;
+    322    : 12;
+    323    : 19;
+    324    : 1F;
+    325    : 23;
+    326    : 26;
+    327    : 28;
+    328    : 04;
+    329    : 0B;
+    330    : 13;
+    331    : 1A;
+    332    : 1F;
+    333    : 24;
+    334    : 27;
+    335    : 29;
+    336    : 04;
+    337    : 0C;
+    338    : 13;
+    339    : 1A;
+    340    : 20;
+    341    : 25;
+    342    : 28;
+    343    : 2A;
+    344    : 04;
+    345    : 0C;
+    346    : 14;
+    347    : 1B;
+    348    : 21;
+    349    : 26;
+    350    : 29;
+    351    : 2B;
+    352    : 04;
+    353    : 0C;
+    354    : 14;
+    355    : 1C;
+    356    : 22;
+    357    : 26;
+    358    : 2A;
+    359    : 2C;
+    360    : 04;
+    361    : 0D;
+    362    : 15;
+    363    : 1C;
+    364    : 22;
+    365    : 27;
+    366    : 2B;
+    367    : 2D;
+    368    : 04;
+    369    : 0D;
+    370    : 15;
+    371    : 1D;
+    372    : 23;
+    373    : 28;
+    374    : 2C;
+    375    : 2E;
+    376    : 04;
+    377    : 0D;
+    378    : 16;
+    379    : 1D;
+    380    : 24;
+    381    : 29;
+    382    : 2D;
+    383    : 2F;
+    384    : 04;
+    385    : 0E;
+    386    : 16;
+    387    : 1E;
+    388    : 25;
+    389    : 2A;
+    390    : 2E;
+    391    : 30;
+    392    : 04;
+    393    : 0E;
+    394    : 17;
+    395    : 1F;
+    396    : 26;
+    397    : 2B;
+    398    : 2F;
+    399    : 31;
+    400    : 04;
+    401    : 0E;
+    402    : 17;
+    403    : 1F;
+    404    : 26;
+    405    : 2C;
+    406    : 30;
+    407    : 32;
+    408    : 05;
+    409    : 0E;
+    410    : 18;
+    411    : 20;
+    412    : 27;
+    413    : 2D;
+    414    : 31;
+    415    : 33;
+    416    : 05;
+    417    : 0F;
+    418    : 18;
+    419    : 21;
+    420    : 28;
+    421    : 2E;
+    422    : 32;
+    423    : 34;
+    424    : 05;
+    425    : 0F;
+    426    : 19;
+    427    : 21;
+    428    : 29;
+    429    : 2E;
+    430    : 32;
+    431    : 35;
+    432    : 05;
+    433    : 0F;
+    434    : 19;
+    435    : 22;
+    436    : 29;
+    437    : 2F;
+    438    : 33;
+    439    : 36;
+    440    : 05;
+    441    : 10;
+    442    : 1A;
+    443    : 23;
+    444    : 2A;
+    445    : 30;
+    446    : 34;
+    447    : 37;
+    448    : 05;
+    449    : 10;
+    450    : 1A;
+    451    : 23;
+    452    : 2B;
+    453    : 31;
+    454    : 35;
+    455    : 38;
+    456    : 05;
+    457    : 10;
+    458    : 1A;
+    459    : 24;
+    460    : 2C;
+    461    : 32;
+    462    : 36;
+    463    : 39;
+    464    : 05;
+    465    : 10;
+    466    : 1B;
+    467    : 24;
+    468    : 2D;
+    469    : 33;
+    470    : 37;
+    471    : 3A;
+    472    : 05;
+    473    : 11;
+    474    : 1B;
+    475    : 25;
+    476    : 2D;
+    477    : 34;
+    478    : 38;
+    479    : 3B;
+    480    : 05;
+    481    : 11;
+    482    : 1C;
+    483    : 26;
+    484    : 2E;
+    485    : 35;
+    486    : 39;
+    487    : 3C;
+    488    : 06;
+    489    : 11;
+    490    : 1C;
+    491    : 26;
+    492    : 2F;
+    493    : 36;
+    494    : 3A;
+    495    : 3D;
+    496    : 06;
+    497    : 12;
+    498    : 1D;
+    499    : 27;
+    500    : 30;
+    501    : 36;
+    502    : 3B;
+    503    : 3E;
+    504    : 06;
+    505    : 12;
+    506    : 1D;
+    507    : 28;
+    508    : 30;
+    509    : 37;
+    510    : 3C;
+    511    : 3F;
+    512    : 06;
+    513    : 12;
+    514    : 1E;
+    515    : 28;
+    516    : 31;
+    517    : 38;
+    518    : 3D;
+    519    : 40;
+    520    : 06;
+    521    : 12;
+    522    : 1E;
+    523    : 29;
+    524    : 32;
+    525    : 39;
+    526    : 3E;
+    527    : 41;
+    528    : 06;
+    529    : 13;
+    530    : 1F;
+    531    : 2A;
+    532    : 33;
+    533    : 3A;
+    534    : 3F;
+    535    : 42;
+    536    : 06;
+    537    : 13;
+    538    : 1F;
+    539    : 2A;
+    540    : 34;
+    541    : 3B;
+    542    : 40;
+    543    : 43;
+    544    : 06;
+    545    : 13;
+    546    : 20;
+    547    : 2B;
+    548    : 34;
+    549    : 3C;
+    550    : 41;
+    551    : 44;
+    552    : 06;
+    553    : 14;
+    554    : 20;
+    555    : 2B;
+    556    : 35;
+    557    : 3D;
+    558    : 42;
+    559    : 45;
+    560    : 06;
+    561    : 14;
+    562    : 21;
+    563    : 2C;
+    564    : 36;
+    565    : 3E;
+    566    : 43;
+    567    : 46;
+    568    : 06;
+    569    : 14;
+    570    : 21;
+    571    : 2D;
+    572    : 37;
+    573    : 3E;
+    574    : 44;
+    575    : 47;
+    576    : 07;
+    577    : 15;
+    578    : 22;
+    579    : 2D;
+    580    : 37;
+    581    : 3F;
+    582    : 45;
+    583    : 48;
+    584    : 07;
+    585    : 15;
+    586    : 22;
+    587    : 2E;
+    588    : 38;
+    589    : 40;
+    590    : 46;
+    591    : 49;
+    592    : 07;
+    593    : 15;
+    594    : 23;
+    595    : 2F;
+    596    : 39;
+    597    : 41;
+    598    : 47;
+    599    : 4A;
+    600    : 07;
+    601    : 15;
+    602    : 23;
+    603    : 2F;
+    604    : 3A;
+    605    : 42;
+    606    : 48;
+    607    : 4B;
+    608    : 07;
+    609    : 16;
+    610    : 23;
+    611    : 30;
+    612    : 3B;
+    613    : 43;
+    614    : 49;
+    615    : 4C;
+    616    : 07;
+    617    : 16;
+    618    : 24;
+    619    : 31;
+    620    : 3B;
+    621    : 44;
+    622    : 4A;
+    623    : 4D;
+    624    : 07;
+    625    : 16;
+    626    : 24;
+    627    : 31;
+    628    : 3C;
+    629    : 45;
+    630    : 4B;
+    631    : 4E;
+    632    : 07;
+    633    : 17;
+    634    : 25;
+    635    : 32;
+    636    : 3D;
+    637    : 46;
+    638    : 4B;
+    639    : 4F;
+    640    : 07;
+    641    : 17;
+    642    : 25;
+    643    : 32;
+    644    : 3E;
+    645    : 46;
+    646    : 4C;
+    647    : 50;
+    648    : 07;
+    649    : 17;
+    650    : 26;
+    651    : 33;
+    652    : 3E;
+    653    : 47;
+    654    : 4D;
+    655    : 51;
+    656    : 08;
+    657    : 17;
+    658    : 26;
+    659    : 34;
+    660    : 3F;
+    661    : 48;
+    662    : 4E;
+    663    : 52;
+    664    : 08;
+    665    : 18;
+    666    : 27;
+    667    : 34;
+    668    : 40;
+    669    : 49;
+    670    : 4F;
+    671    : 53;
+    672    : 08;
+    673    : 18;
+    674    : 27;
+    675    : 35;
+    676    : 41;
+    677    : 4A;
+    678    : 50;
+    679    : 54;
+    680    : 08;
+    681    : 18;
+    682    : 28;
+    683    : 36;
+    684    : 42;
+    685    : 4B;
+    686    : 51;
+    687    : 55;
+    688    : 08;
+    689    : 19;
+    690    : 28;
+    691    : 36;
+    692    : 42;
+    693    : 4C;
+    694    : 52;
+    695    : 56;
+    696    : 08;
+    697    : 19;
+    698    : 29;
+    699    : 37;
+    700    : 43;
+    701    : 4D;
+    702    : 53;
+    703    : 57;
+    704    : 08;
+    705    : 19;
+    706    : 29;
+    707    : 38;
+    708    : 44;
+    709    : 4D;
+    710    : 54;
+    711    : 58;
+    712    : 08;
+    713    : 19;
+    714    : 2A;
+    715    : 38;
+    716    : 45;
+    717    : 4E;
+    718    : 55;
+    719    : 59;
+    720    : 08;
+    721    : 1A;
+    722    : 2A;
+    723    : 39;
+    724    : 45;
+    725    : 4F;
+    726    : 56;
+    727    : 5A;
+    728    : 08;
+    729    : 1A;
+    730    : 2B;
+    731    : 3A;
+    732    : 46;
+    733    : 50;
+    734    : 57;
+    735    : 5B;
+    736    : 09;
+    737    : 1A;
+    738    : 2B;
+    739    : 3A;
+    740    : 47;
+    741    : 51;
+    742    : 58;
+    743    : 5C;
+    744    : 09;
+    745    : 1B;
+    746    : 2C;
+    747    : 3B;
+    748    : 48;
+    749    : 52;
+    750    : 59;
+    751    : 5D;
+    752    : 09;
+    753    : 1B;
+    754    : 2C;
+    755    : 3B;
+    756    : 49;
+    757    : 53;
+    758    : 5A;
+    759    : 5E;
+    760    : 09;
+    761    : 1B;
+    762    : 2C;
+    763    : 3C;
+    764    : 49;
+    765    : 54;
+    766    : 5B;
+    767    : 5F;
+    768    : 09;
+    769    : 1C;
+    770    : 2D;
+    771    : 3D;
+    772    : 4A;
+    773    : 55;
+    774    : 5C;
+    775    : 60;
+    776    : 09;
+    777    : 1C;
+    778    : 2D;
+    779    : 3D;
+    780    : 4B;
+    781    : 55;
+    782    : 5D;
+    783    : 61;
+    784    : 09;
+    785    : 1C;
+    786    : 2E;
+    787    : 3E;
+    788    : 4C;
+    789    : 56;
+    790    : 5E;
+    791    : 62;
+    792    : 09;
+    793    : 1C;
+    794    : 2E;
+    795    : 3F;
+    796    : 4C;
+    797    : 57;
+    798    : 5F;
+    799    : 63;
+    800    : 09;
+    801    : 1D;
+    802    : 2F;
+    803    : 3F;
+    804    : 4D;
+    805    : 58;
+    806    : 60;
+    807    : 64;
+    808    : 09;
+    809    : 1D;
+    810    : 2F;
+    811    : 40;
+    812    : 4E;
+    813    : 59;
+    814    : 61;
+    815    : 65;
+    816    : 0A;
+    817    : 1D;
+    818    : 30;
+    819    : 41;
+    820    : 4F;
+    821    : 5A;
+    822    : 62;
+    823    : 66;
+    824    : 0A;
+    825    : 1E;
+    826    : 30;
+    827    : 41;
+    828    : 50;
+    829    : 5B;
+    830    : 63;
+    831    : 67;
+    832    : 0A;
+    833    : 1E;
+    834    : 31;
+    835    : 42;
+    836    : 50;
+    837    : 5C;
+    838    : 64;
+    839    : 68;
+    840    : 0A;
+    841    : 1E;
+    842    : 31;
+    843    : 42;
+    844    : 51;
+    845    : 5D;
+    846    : 64;
+    847    : 69;
+    848    : 0A;
+    849    : 1E;
+    850    : 32;
+    851    : 43;
+    852    : 52;
+    853    : 5D;
+    854    : 65;
+    855    : 6A;
+    856    : 0A;
+    857    : 1F;
+    858    : 32;
+    859    : 44;
+    860    : 53;
+    861    : 5E;
+    862    : 66;
+    863    : 6B;
+    864    : 0A;
+    865    : 1F;
+    866    : 33;
+    867    : 44;
+    868    : 53;
+    869    : 5F;
+    870    : 67;
+    871    : 6C;
+    872    : 0A;
+    873    : 1F;
+    874    : 33;
+    875    : 45;
+    876    : 54;
+    877    : 60;
+    878    : 68;
+    879    : 6D;
+    880    : 0A;
+    881    : 20;
+    882    : 34;
+    883    : 46;
+    884    : 55;
+    885    : 61;
+    886    : 69;
+    887    : 6E;
+    888    : 0A;
+    889    : 20;
+    890    : 34;
+    891    : 46;
+    892    : 56;
+    893    : 62;
+    894    : 6A;
+    895    : 6F;
+    896    : 0B;
+    897    : 20;
+    898    : 35;
+    899    : 47;
+    900    : 56;
+    901    : 63;
+    902    : 6B;
+    903    : 70;
+    904    : 0B;
+    905    : 20;
+    906    : 35;
+    907    : 48;
+    908    : 57;
+    909    : 64;
+    910    : 6C;
+    911    : 71;
+    912    : 0B;
+    913    : 21;
+    914    : 35;
+    915    : 48;
+    916    : 58;
+    917    : 65;
+    918    : 6D;
+    919    : 72;
+    920    : 0B;
+    921    : 21;
+    922    : 36;
+    923    : 49;
+    924    : 59;
+    925    : 65;
+    926    : 6E;
+    927    : 73;
+    928    : 0B;
+    929    : 21;
+    930    : 36;
+    931    : 49;
+    932    : 5A;
+    933    : 66;
+    934    : 6F;
+    935    : 74;
+    936    : 0B;
+    937    : 22;
+    938    : 37;
+    939    : 4A;
+    940    : 5A;
+    941    : 67;
+    942    : 70;
+    943    : 75;
+    944    : 0B;
+    945    : 22;
+    946    : 37;
+    947    : 4B;
+    948    : 5B;
+    949    : 68;
+    950    : 71;
+    951    : 76;
+    952    : 0B;
+    953    : 22;
+    954    : 38;
+    955    : 4B;
+    956    : 5C;
+    957    : 69;
+    958    : 72;
+    959    : 77;
+    960    : 0B;
+    961    : 23;
+    962    : 38;
+    963    : 4C;
+    964    : 5D;
+    965    : 6A;
+    966    : 73;
+    967    : 78;
+    968    : 0B;
+    969    : 23;
+    970    : 39;
+    971    : 4D;
+    972    : 5D;
+    973    : 6B;
+    974    : 74;
+    975    : 79;
+    976    : 0C;
+    977    : 23;
+    978    : 39;
+    979    : 4D;
+    980    : 5E;
+    981    : 6C;
+    982    : 75;
+    983    : 7A;
+    984    : 0C;
+    985    : 23;
+    986    : 3A;
+    987    : 4E;
+    988    : 5F;
+    989    : 6D;
+    990    : 76;
+    991    : 7B;
+    992    : 0C;
+    993    : 24;
+    994    : 3A;
+    995    : 4F;
+    996    : 60;
+    997    : 6D;
+    998    : 77;
+    999    : 7C;
+    1000   : 0C;
+    1001   : 24;
+    1002   : 3B;
+    1003   : 4F;
+    1004   : 61;
+    1005   : 6E;
+    1006   : 78;
+    1007   : 7D;
+    1008   : 0C;
+    1009   : 24;
+    1010   : 3B;
+    1011   : 50;
+    1012   : 61;
+    1013   : 6F;
+    1014   : 79;
+    1015   : 7E;
+    1016   : 0C;
+    1017   : 25;
+    1018   : 3C;
+    1019   : 50;
+    1020   : 62;
+    1021   : 70;
+    1022   : 7A;
+    1023   : 7F;
+    1024   : 0C;
+    1025   : 25;
+    1026   : 3C;
+    1027   : 51;
+    1028   : 63;
+    1029   : 71;
+    1030   : 7B;
+    1031   : 80;
+    1032   : 0C;
+    1033   : 25;
+    1034   : 3D;
+    1035   : 52;
+    1036   : 64;
+    1037   : 72;
+    1038   : 7C;
+    1039   : 81;
+    1040   : 0C;
+    1041   : 25;
+    1042   : 3D;
+    1043   : 52;
+    1044   : 64;
+    1045   : 73;
+    1046   : 7D;
+    1047   : 82;
+    1048   : 0C;
+    1049   : 26;
+    1050   : 3E;
+    1051   : 53;
+    1052   : 65;
+    1053   : 74;
+    1054   : 7D;
+    1055   : 83;
+    1056   : 0D;
+    1057   : 26;
+    1058   : 3E;
+    1059   : 54;
+    1060   : 66;
+    1061   : 74;
+    1062   : 7E;
+    1063   : 84;
+    1064   : 0D;
+    1065   : 26;
+    1066   : 3E;
+    1067   : 54;
+    1068   : 67;
+    1069   : 75;
+    1070   : 7F;
+    1071   : 85;
+    1072   : 0D;
+    1073   : 27;
+    1074   : 3F;
+    1075   : 55;
+    1076   : 68;
+    1077   : 76;
+    1078   : 80;
+    1079   : 86;
+    1080   : 0D;
+    1081   : 27;
+    1082   : 3F;
+    1083   : 56;
+    1084   : 68;
+    1085   : 77;
+    1086   : 81;
+    1087   : 87;
+    1088   : 0D;
+    1089   : 27;
+    1090   : 40;
+    1091   : 56;
+    1092   : 69;
+    1093   : 78;
+    1094   : 82;
+    1095   : 88;
+    1096   : 0D;
+    1097   : 27;
+    1098   : 40;
+    1099   : 57;
+    1100   : 6A;
+    1101   : 79;
+    1102   : 83;
+    1103   : 89;
+    1104   : 0D;
+    1105   : 28;
+    1106   : 41;
+    1107   : 57;
+    1108   : 6B;
+    1109   : 7A;
+    1110   : 84;
+    1111   : 8A;
+    1112   : 0D;
+    1113   : 28;
+    1114   : 41;
+    1115   : 58;
+    1116   : 6B;
+    1117   : 7B;
+    1118   : 85;
+    1119   : 8B;
+    1120   : 0D;
+    1121   : 28;
+    1122   : 42;
+    1123   : 59;
+    1124   : 6C;
+    1125   : 7C;
+    1126   : 86;
+    1127   : 8C;
+    1128   : 0D;
+    1129   : 29;
+    1130   : 42;
+    1131   : 59;
+    1132   : 6D;
+    1133   : 7C;
+    1134   : 87;
+    1135   : 8D;
+    1136   : 0D;
+    1137   : 29;
+    1138   : 43;
+    1139   : 5A;
+    1140   : 6E;
+    1141   : 7D;
+    1142   : 88;
+    1143   : 8E;
+    1144   : 0E;
+    1145   : 29;
+    1146   : 43;
+    1147   : 5B;
+    1148   : 6F;
+    1149   : 7E;
+    1150   : 89;
+    1151   : 8F;
+    1152   : 0E;
+    1153   : 2A;
+    1154   : 44;
+    1155   : 5B;
+    1156   : 6F;
+    1157   : 7F;
+    1158   : 8A;
+    1159   : 90;
+    1160   : 0E;
+    1161   : 2A;
+    1162   : 44;
+    1163   : 5C;
+    1164   : 70;
+    1165   : 80;
+    1166   : 8B;
+    1167   : 91;
+    1168   : 0E;
+    1169   : 2A;
+    1170   : 45;
+    1171   : 5D;
+    1172   : 71;
+    1173   : 81;
+    1174   : 8C;
+    1175   : 92;
+    1176   : 0E;
+    1177   : 2A;
+    1178   : 45;
+    1179   : 5D;
+    1180   : 72;
+    1181   : 82;
+    1182   : 8D;
+    1183   : 93;
+    1184   : 0E;
+    1185   : 2B;
+    1186   : 46;
+    1187   : 5E;
+    1188   : 72;
+    1189   : 83;
+    1190   : 8E;
+    1191   : 94;
+    1192   : 0E;
+    1193   : 2B;
+    1194   : 46;
+    1195   : 5E;
+    1196   : 73;
+    1197   : 84;
+    1198   : 8F;
+    1199   : 95;
+    1200   : 0E;
+    1201   : 2B;
+    1202   : 47;
+    1203   : 5F;
+    1204   : 74;
+    1205   : 84;
+    1206   : 90;
+    1207   : 96;
+    1208   : 0E;
+    1209   : 2C;
+    1210   : 47;
+    1211   : 60;
+    1212   : 75;
+    1213   : 85;
+    1214   : 91;
+    1215   : 97;
+    1216   : 0E;
+    1217   : 2C;
+    1218   : 47;
+    1219   : 60;
+    1220   : 76;
+    1221   : 86;
+    1222   : 92;
+    1223   : 98;
+    1224   : 0F;
+    1225   : 2C;
+    1226   : 48;
+    1227   : 61;
+    1228   : 76;
+    1229   : 87;
+    1230   : 93;
+    1231   : 99;
+    1232   : 0F;
+    1233   : 2C;
+    1234   : 48;
+    1235   : 62;
+    1236   : 77;
+    1237   : 88;
+    1238   : 94;
+    1239   : 9A;
+    1240   : 0F;
+    1241   : 2D;
+    1242   : 49;
+    1243   : 62;
+    1244   : 78;
+    1245   : 89;
+    1246   : 95;
+    1247   : 9B;
+    1248   : 0F;
+    1249   : 2D;
+    1250   : 49;
+    1251   : 63;
+    1252   : 79;
+    1253   : 8A;
+    1254   : 96;
+    1255   : 9C;
+    1256   : 0F;
+    1257   : 2D;
+    1258   : 4A;
+    1259   : 64;
+    1260   : 79;
+    1261   : 8B;
+    1262   : 96;
+    1263   : 9D;
+    1264   : 0F;
+    1265   : 2E;
+    1266   : 4A;
+    1267   : 64;
+    1268   : 7A;
+    1269   : 8C;
+    1270   : 97;
+    1271   : 9E;
+    1272   : 0F;
+    1273   : 2E;
+    1274   : 4B;
+    1275   : 65;
+    1276   : 7B;
+    1277   : 8C;
+    1278   : 98;
+    1279   : 9F;
+    1280   : 0F;
+    1281   : 2E;
+    1282   : 4B;
+    1283   : 65;
+    1284   : 7C;
+    1285   : 8D;
+    1286   : 99;
+    1287   : A0;
+    1288   : 0F;
+    1289   : 2E;
+    1290   : 4C;
+    1291   : 66;
+    1292   : 7D;
+    1293   : 8E;
+    1294   : 9A;
+    1295   : A1;
+    1296   : 0F;
+    1297   : 2F;
+    1298   : 4C;
+    1299   : 67;
+    1300   : 7D;
+    1301   : 8F;
+    1302   : 9B;
+    1303   : A2;
+    1304   : 10;
+    1305   : 2F;
+    1306   : 4D;
+    1307   : 67;
+    1308   : 7E;
+    1309   : 90;
+    1310   : 9C;
+    1311   : A3;
+    1312   : 10;
+    1313   : 2F;
+    1314   : 4D;
+    1315   : 68;
+    1316   : 7F;
+    1317   : 91;
+    1318   : 9D;
+    1319   : A4;
+    1320   : 10;
+    1321   : 30;
+    1322   : 4E;
+    1323   : 69;
+    1324   : 80;
+    1325   : 92;
+    1326   : 9E;
+    1327   : A5;
+    1328   : 10;
+    1329   : 30;
+    1330   : 4E;
+    1331   : 69;
+    1332   : 80;
+    1333   : 93;
+    1334   : 9F;
+    1335   : A6;
+    1336   : 10;
+    1337   : 30;
+    1338   : 4F;
+    1339   : 6A;
+    1340   : 81;
+    1341   : 93;
+    1342   : A0;
+    1343   : A7;
+    1344   : 10;
+    1345   : 31;
+    1346   : 4F;
+    1347   : 6B;
+    1348   : 82;
+    1349   : 94;
+    1350   : A1;
+    1351   : A8;
+    1352   : 10;
+    1353   : 31;
+    1354   : 50;
+    1355   : 6B;
+    1356   : 83;
+    1357   : 95;
+    1358   : A2;
+    1359   : A9;
+    1360   : 10;
+    1361   : 31;
+    1362   : 50;
+    1363   : 6C;
+    1364   : 84;
+    1365   : 96;
+    1366   : A3;
+    1367   : AA;
+    1368   : 10;
+    1369   : 31;
+    1370   : 50;
+    1371   : 6D;
+    1372   : 84;
+    1373   : 97;
+    1374   : A4;
+    1375   : AB;
+    1376   : 10;
+    1377   : 32;
+    1378   : 51;
+    1379   : 6D;
+    1380   : 85;
+    1381   : 98;
+    1382   : A5;
+    1383   : AC;
+    1384   : 11;
+    1385   : 32;
+    1386   : 51;
+    1387   : 6E;
+    1388   : 86;
+    1389   : 99;
+    1390   : A6;
+    1391   : AD;
+    1392   : 11;
+    1393   : 32;
+    1394   : 52;
+    1395   : 6E;
+    1396   : 87;
+    1397   : 9A;
+    1398   : A7;
+    1399   : AE;
+    1400   : 11;
+    1401   : 33;
+    1402   : 52;
+    1403   : 6F;
+    1404   : 87;
+    1405   : 9B;
+    1406   : A8;
+    1407   : AF;
+    1408   : 11;
+    1409   : 33;
+    1410   : 53;
+    1411   : 70;
+    1412   : 88;
+    1413   : 9B;
+    1414   : A9;
+    1415   : B0;
+    1416   : 11;
+    1417   : 33;
+    1418   : 53;
+    1419   : 70;
+    1420   : 89;
+    1421   : 9C;
+    1422   : AA;
+    1423   : B1;
+    1424   : 11;
+    1425   : 33;
+    1426   : 54;
+    1427   : 71;
+    1428   : 8A;
+    1429   : 9D;
+    1430   : AB;
+    1431   : B2;
+    1432   : 11;
+    1433   : 34;
+    1434   : 54;
+    1435   : 72;
+    1436   : 8B;
+    1437   : 9E;
+    1438   : AC;
+    1439   : B3;
+    1440   : 11;
+    1441   : 34;
+    1442   : 55;
+    1443   : 72;
+    1444   : 8B;
+    1445   : 9F;
+    1446   : AD;
+    1447   : B4;
+    1448   : 11;
+    1449   : 34;
+    1450   : 55;
+    1451   : 73;
+    1452   : 8C;
+    1453   : A0;
+    1454   : AE;
+    1455   : B5;
+    1456   : 11;
+    1457   : 35;
+    1458   : 56;
+    1459   : 74;
+    1460   : 8D;
+    1461   : A1;
+    1462   : AF;
+    1463   : B6;
+    1464   : 12;
+    1465   : 35;
+    1466   : 56;
+    1467   : 74;
+    1468   : 8E;
+    1469   : A2;
+    1470   : AF;
+    1471   : B7;
+    1472   : 12;
+    1473   : 35;
+    1474   : 57;
+    1475   : 75;
+    1476   : 8E;
+    1477   : A3;
+    1478   : B0;
+    1479   : B8;
+    1480   : 12;
+    1481   : 35;
+    1482   : 57;
+    1483   : 75;
+    1484   : 8F;
+    1485   : A3;
+    1486   : B1;
+    1487   : B9;
+    1488   : 12;
+    1489   : 36;
+    1490   : 58;
+    1491   : 76;
+    1492   : 90;
+    1493   : A4;
+    1494   : B2;
+    1495   : BA;
+    1496   : 12;
+    1497   : 36;
+    1498   : 58;
+    1499   : 77;
+    1500   : 91;
+    1501   : A5;
+    1502   : B3;
+    1503   : BB;
+    1504   : 12;
+    1505   : 36;
+    1506   : 59;
+    1507   : 77;
+    1508   : 92;
+    1509   : A6;
+    1510   : B4;
+    1511   : BC;
+    1512   : 12;
+    1513   : 37;
+    1514   : 59;
+    1515   : 78;
+    1516   : 92;
+    1517   : A7;
+    1518   : B5;
+    1519   : BD;
+    1520   : 12;
+    1521   : 37;
+    1522   : 59;
+    1523   : 79;
+    1524   : 93;
+    1525   : A8;
+    1526   : B6;
+    1527   : BE;
+    1528   : 12;
+    1529   : 37;
+    1530   : 5A;
+    1531   : 79;
+    1532   : 94;
+    1533   : A9;
+    1534   : B7;
+    1535   : BF;
+    1536   : 12;
+    1537   : 38;
+    1538   : 5A;
+    1539   : 7A;
+    1540   : 95;
+    1541   : AA;
+    1542   : B8;
+    1543   : C0;
+    1544   : 13;
+    1545   : 38;
+    1546   : 5B;
+    1547   : 7B;
+    1548   : 95;
+    1549   : AB;
+    1550   : B9;
+    1551   : C1;
+    1552   : 13;
+    1553   : 38;
+    1554   : 5B;
+    1555   : 7B;
+    1556   : 96;
+    1557   : AB;
+    1558   : BA;
+    1559   : C2;
+    1560   : 13;
+    1561   : 38;
+    1562   : 5C;
+    1563   : 7C;
+    1564   : 97;
+    1565   : AC;
+    1566   : BB;
+    1567   : C3;
+    1568   : 13;
+    1569   : 39;
+    1570   : 5C;
+    1571   : 7C;
+    1572   : 98;
+    1573   : AD;
+    1574   : BC;
+    1575   : C4;
+    1576   : 13;
+    1577   : 39;
+    1578   : 5D;
+    1579   : 7D;
+    1580   : 99;
+    1581   : AE;
+    1582   : BD;
+    1583   : C5;
+    1584   : 13;
+    1585   : 39;
+    1586   : 5D;
+    1587   : 7E;
+    1588   : 99;
+    1589   : AF;
+    1590   : BE;
+    1591   : C6;
+    1592   : 13;
+    1593   : 3A;
+    1594   : 5E;
+    1595   : 7E;
+    1596   : 9A;
+    1597   : B0;
+    1598   : BF;
+    1599   : C7;
+    1600   : 13;
+    1601   : 3A;
+    1602   : 5E;
+    1603   : 7F;
+    1604   : 9B;
+    1605   : B1;
+    1606   : C0;
+    1607   : C8;
+    1608   : 13;
+    1609   : 3A;
+    1610   : 5F;
+    1611   : 80;
+    1612   : 9C;
+    1613   : B2;
+    1614   : C1;
+    1615   : C9;
+    1616   : 13;
+    1617   : 3A;
+    1618   : 5F;
+    1619   : 80;
+    1620   : 9C;
+    1621   : B3;
+    1622   : C2;
+    1623   : CA;
+    1624   : 13;
+    1625   : 3B;
+    1626   : 60;
+    1627   : 81;
+    1628   : 9D;
+    1629   : B3;
+    1630   : C3;
+    1631   : CB;
+    1632   : 14;
+    1633   : 3B;
+    1634   : 60;
+    1635   : 82;
+    1636   : 9E;
+    1637   : B4;
+    1638   : C4;
+    1639   : CC;
+    1640   : 14;
+    1641   : 3B;
+    1642   : 61;
+    1643   : 82;
+    1644   : 9F;
+    1645   : B5;
+    1646   : C5;
+    1647   : CD;
+    1648   : 14;
+    1649   : 3C;
+    1650   : 61;
+    1651   : 83;
+    1652   : A0;
+    1653   : B6;
+    1654   : C6;
+    1655   : CE;
+    1656   : 14;
+    1657   : 3C;
+    1658   : 62;
+    1659   : 83;
+    1660   : A0;
+    1661   : B7;
+    1662   : C7;
+    1663   : CF;
+    1664   : 14;
+    1665   : 3C;
+    1666   : 62;
+    1667   : 84;
+    1668   : A1;
+    1669   : B8;
+    1670   : C8;
+    1671   : D0;
+    1672   : 14;
+    1673   : 3C;
+    1674   : 62;
+    1675   : 85;
+    1676   : A2;
+    1677   : B9;
+    1678   : C8;
+    1679   : D1;
+    1680   : 14;
+    1681   : 3D;
+    1682   : 63;
+    1683   : 85;
+    1684   : A3;
+    1685   : BA;
+    1686   : C9;
+    1687   : D2;
+    1688   : 14;
+    1689   : 3D;
+    1690   : 63;
+    1691   : 86;
+    1692   : A3;
+    1693   : BA;
+    1694   : CA;
+    1695   : D3;
+    1696   : 14;
+    1697   : 3D;
+    1698   : 64;
+    1699   : 87;
+    1700   : A4;
+    1701   : BB;
+    1702   : CB;
+    1703   : D4;
+    1704   : 14;
+    1705   : 3E;
+    1706   : 64;
+    1707   : 87;
+    1708   : A5;
+    1709   : BC;
+    1710   : CC;
+    1711   : D5;
+    1712   : 15;
+    1713   : 3E;
+    1714   : 65;
+    1715   : 88;
+    1716   : A6;
+    1717   : BD;
+    1718   : CD;
+    1719   : D6;
+    1720   : 15;
+    1721   : 3E;
+    1722   : 65;
+    1723   : 89;
+    1724   : A7;
+    1725   : BE;
+    1726   : CE;
+    1727   : D7;
+    1728   : 15;
+    1729   : 3F;
+    1730   : 66;
+    1731   : 89;
+    1732   : A7;
+    1733   : BF;
+    1734   : CF;
+    1735   : D8;
+    1736   : 15;
+    1737   : 3F;
+    1738   : 66;
+    1739   : 8A;
+    1740   : A8;
+    1741   : C0;
+    1742   : D0;
+    1743   : D9;
+    1744   : 15;
+    1745   : 3F;
+    1746   : 67;
+    1747   : 8A;
+    1748   : A9;
+    1749   : C1;
+    1750   : D1;
+    1751   : DA;
+    1752   : 15;
+    1753   : 3F;
+    1754   : 67;
+    1755   : 8B;
+    1756   : AA;
+    1757   : C2;
+    1758   : D2;
+    1759   : DB;
+    1760   : 15;
+    1761   : 40;
+    1762   : 68;
+    1763   : 8C;
+    1764   : AA;
+    1765   : C2;
+    1766   : D3;
+    1767   : DC;
+    1768   : 15;
+    1769   : 40;
+    1770   : 68;
+    1771   : 8C;
+    1772   : AB;
+    1773   : C3;
+    1774   : D4;
+    1775   : DD;
+    1776   : 15;
+    1777   : 40;
+    1778   : 69;
+    1779   : 8D;
+    1780   : AC;
+    1781   : C4;
+    1782   : D5;
+    1783   : DE;
+    1784   : 15;
+    1785   : 41;
+    1786   : 69;
+    1787   : 8E;
+    1788   : AD;
+    1789   : C5;
+    1790   : D6;
+    1791   : DF;
+    1792   : 16;
+    1793   : 41;
+    1794   : 6A;
+    1795   : 8E;
+    1796   : AD;
+    1797   : C6;
+    1798   : D7;
+    1799   : E0;
+    1800   : 16;
+    1801   : 41;
+    1802   : 6A;
+    1803   : 8F;
+    1804   : AE;
+    1805   : C7;
+    1806   : D8;
+    1807   : E1;
+    1808   : 16;
+    1809   : 41;
+    1810   : 6B;
+    1811   : 90;
+    1812   : AF;
+    1813   : C8;
+    1814   : D9;
+    1815   : E2;
+    1816   : 16;
+    1817   : 42;
+    1818   : 6B;
+    1819   : 90;
+    1820   : B0;
+    1821   : C9;
+    1822   : DA;
+    1823   : E3;
+    1824   : 16;
+    1825   : 42;
+    1826   : 6B;
+    1827   : 91;
+    1828   : B1;
+    1829   : CA;
+    1830   : DB;
+    1831   : E4;
+    1832   : 16;
+    1833   : 42;
+    1834   : 6C;
+    1835   : 91;
+    1836   : B1;
+    1837   : CA;
+    1838   : DC;
+    1839   : E5;
+    1840   : 16;
+    1841   : 43;
+    1842   : 6C;
+    1843   : 92;
+    1844   : B2;
+    1845   : CB;
+    1846   : DD;
+    1847   : E6;
+    1848   : 16;
+    1849   : 43;
+    1850   : 6D;
+    1851   : 93;
+    1852   : B3;
+    1853   : CC;
+    1854   : DE;
+    1855   : E7;
+    1856   : 16;
+    1857   : 43;
+    1858   : 6D;
+    1859   : 93;
+    1860   : B4;
+    1861   : CD;
+    1862   : DF;
+    1863   : E8;
+    1864   : 16;
+    1865   : 43;
+    1866   : 6E;
+    1867   : 94;
+    1868   : B4;
+    1869   : CE;
+    1870   : E0;
+    1871   : E9;
+    1872   : 17;
+    1873   : 44;
+    1874   : 6E;
+    1875   : 95;
+    1876   : B5;
+    1877   : CF;
+    1878   : E1;
+    1879   : EA;
+    1880   : 17;
+    1881   : 44;
+    1882   : 6F;
+    1883   : 95;
+    1884   : B6;
+    1885   : D0;
+    1886   : E1;
+    1887   : EB;
+    1888   : 17;
+    1889   : 44;
+    1890   : 6F;
+    1891   : 96;
+    1892   : B7;
+    1893   : D1;
+    1894   : E2;
+    1895   : EC;
+    1896   : 17;
+    1897   : 45;
+    1898   : 70;
+    1899   : 97;
+    1900   : B8;
+    1901   : D2;
+    1902   : E3;
+    1903   : ED;
+    1904   : 17;
+    1905   : 45;
+    1906   : 70;
+    1907   : 97;
+    1908   : B8;
+    1909   : D2;
+    1910   : E4;
+    1911   : EE;
+    1912   : 17;
+    1913   : 45;
+    1914   : 71;
+    1915   : 98;
+    1916   : B9;
+    1917   : D3;
+    1918   : E5;
+    1919   : EF;
+    1920   : 17;
+    1921   : 46;
+    1922   : 71;
+    1923   : 98;
+    1924   : BA;
+    1925   : D4;
+    1926   : E6;
+    1927   : F0;
+    1928   : 17;
+    1929   : 46;
+    1930   : 72;
+    1931   : 99;
+    1932   : BB;
+    1933   : D5;
+    1934   : E7;
+    1935   : F1;
+    1936   : 17;
+    1937   : 46;
+    1938   : 72;
+    1939   : 9A;
+    1940   : BB;
+    1941   : D6;
+    1942   : E8;
+    1943   : F2;
+    1944   : 17;
+    1945   : 46;
+    1946   : 73;
+    1947   : 9A;
+    1948   : BC;
+    1949   : D7;
+    1950   : E9;
+    1951   : F3;
+    1952   : 18;
+    1953   : 47;
+    1954   : 73;
+    1955   : 9B;
+    1956   : BD;
+    1957   : D8;
+    1958   : EA;
+    1959   : F4;
+    1960   : 18;
+    1961   : 47;
+    1962   : 74;
+    1963   : 9C;
+    1964   : BE;
+    1965   : D9;
+    1966   : EB;
+    1967   : F5;
+    1968   : 18;
+    1969   : 47;
+    1970   : 74;
+    1971   : 9C;
+    1972   : BF;
+    1973   : DA;
+    1974   : EC;
+    1975   : F6;
+    1976   : 18;
+    1977   : 48;
+    1978   : 74;
+    1979   : 9D;
+    1980   : BF;
+    1981   : DA;
+    1982   : ED;
+    1983   : F7;
+    1984   : 18;
+    1985   : 48;
+    1986   : 75;
+    1987   : 9E;
+    1988   : C0;
+    1989   : DB;
+    1990   : EE;
+    1991   : F8;
+    1992   : 18;
+    1993   : 48;
+    1994   : 75;
+    1995   : 9E;
+    1996   : C1;
+    1997   : DC;
+    1998   : EF;
+    1999   : F9;
+    2000   : 18;
+    2001   : 48;
+    2002   : 76;
+    2003   : 9F;
+    2004   : C2;
+    2005   : DD;
+    2006   : F0;
+    2007   : FA;
+    2008   : 18;
+    2009   : 49;
+    2010   : 76;
+    2011   : A0;
+    2012   : C2;
+    2013   : DE;
+    2014   : F1;
+    2015   : FB;
+    2016   : 18;
+    2017   : 49;
+    2018   : 77;
+    2019   : A0;
+    2020   : C3;
+    2021   : DF;
+    2022   : F2;
+    2023   : FC;
+    2024   : 18;
+    2025   : 49;
+    2026   : 77;
+    2027   : A1;
+    2028   : C4;
+    2029   : E0;
+    2030   : F3;
+    2031   : FD;
+    2032   : 19;
+    2033   : 4A;
+    2034   : 78;
+    2035   : A1;
+    2036   : C5;
+    2037   : E1;
+    2038   : F4;
+    2039   : FE;
+    2040   : 19;
+    2041   : 4A;
+    2042   : 78;
+    2043   : A2;
+    2044   : C6;
+    2045   : E1;
+    2046   : F5;
+    2047   : FF;
+END;
Index: mcctv/svideo/svideo.vhd
===================================================================
--- mcctv/svideo/svideo.vhd	(nonexistent)
+++ mcctv/svideo/svideo.vhd	(revision 181)
@@ -0,0 +1,404 @@
+-- ===================================================================================
+-- Package / Component definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+--PACKAGE svideo_pkg IS
+--  COMPONENT svideo
+--  PORT(
+--    -- Power up reset
+--    areset_n    : IN  STD_LOGIC;
+--    -- Main clock (28.636363 MHz)
+--    ecs_clk     : IN  STD_LOGIC;
+--    -- DAC clock (114.545454 MHz)
+--    dac_clk     : IN  STD_LOGIC;
+--    -- RGB input
+--    r_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    g_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    b_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    -- Start of frame flag
+--    sof         : IN  STD_LOGIC;
+--    -- PAL burst phase
+--    vpos_lsb    : IN  STD_LOGIC;
+--    -- Burst/Synchro/Blanking inputs
+--    blank       : IN  STD_LOGIC;
+--    burst       : IN  STD_LOGIC;
+--    csync_n     : IN  STD_LOGIC;
+--    -- S-Video output
+--    y_out       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    c_out       : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+--    -- PAL(0)/NTSC(1) mode
+--    pal_ntsc    : IN  STD_LOGIC
+--  );
+--  END COMPONENT;
+--
+--END PACKAGE;
+
+-- ===================================================================================
+-- Entity / Architecture definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+LIBRARY WORK;
+USE WORK.SIN_COS_PKG.ALL;
+
+ENTITY svideo IS
+  PORT(
+    -- Power up reset
+    areset_n    : IN  STD_LOGIC;
+    -- Main clock (28.636363 MHz)
+    ecs_clk     : IN  STD_LOGIC;
+    -- DAC clock (114.545454 MHz)
+    dac_clk     : IN  STD_LOGIC;
+    -- RGB input
+    r_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    g_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    b_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    -- Start of frame flag
+    sof         : IN  STD_LOGIC;
+    -- PAL burst phase
+    vpos_lsb    : IN  STD_LOGIC;
+    -- Burst/Synchro/Blanking inputs
+    blank       : IN  STD_LOGIC;
+    burst       : IN  STD_LOGIC;
+    csync_n     : IN  STD_LOGIC;
+    -- S-Video output
+    y_out       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    c_out       : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+    -- raw chroma/luma output
+    luma_out       : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+    chroma_out     : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    -- PAL(0)/NTSC(1) mode
+    pal_ntsc    : IN  STD_LOGIC
+  );
+END svideo;
+
+ARCHITECTURE rtl OF svideo IS
+
+  -- Color carrier phase (0 - 31)
+  SIGNAL   col_ctr      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+
+  -------------------------
+  -- RGB -> Y conversion --
+  -------------------------
+  -- 1st stage
+  SIGNAL   comp_YR      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_YG      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_YB      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_Y2      : STD_LOGIC_VECTOR(16 DOWNTO 0);
+  SIGNAL   comp_Y3      : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   comp_Y4      : STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+  CONSTANT Y_LVL_SYNC   : STD_LOGIC_VECTOR(16 DOWNTO 0) := "00000000000000000";
+  CONSTANT Y_LVL_BLANK  : STD_LOGIC_VECTOR(16 DOWNTO 0) := "01110011000000000";
+  CONSTANT Y_LVL_PICT   : STD_LOGIC_VECTOR(16 DOWNTO 0) := "01110011000000000";
+
+  -------------------------
+  -- RGB -> U conversion --
+  -------------------------
+  -- 1st stage
+  SIGNAL   comp_UR      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_UG      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_UB      : UNSIGNED(16 DOWNTO 0);
+  -- 2nd stage
+  SIGNAL   comp_pU      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  SIGNAL   comp_mU      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  -- 3rd stage
+  SIGNAL   sign_U       : STD_LOGIC;
+  SIGNAL   ampl_U       : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  -- 4th stage
+  SIGNAL   comp_U       : STD_LOGIC_VECTOR(8 DOWNTO 0);
+
+--  CONSTANT pU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "000100100000000000"; -- +15%
+--  CONSTANT mU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "111011100000000000"; -- -15%
+--  CONSTANT pU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "000110000000000000"; -- +20%
+--  CONSTANT mU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "111010000000000000"; -- -20%
+  CONSTANT pU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "000111111000000000"; -- +25%
+  CONSTANT mU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "111000000000000000"; -- -25%
+
+  -------------------------
+  -- RGB -> V conversion --
+  -------------------------
+  -- 1st stage
+  SIGNAL   comp_VR      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_VG      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_VB      : UNSIGNED(16 DOWNTO 0);
+  -- 2nd stage
+  SIGNAL   comp_pV      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  SIGNAL   comp_mV      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  -- 3rd stage
+  SIGNAL   sign_V       : STD_LOGIC;
+  SIGNAL   ampl_V       : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  -- 4th stage
+  SIGNAL   comp_V       : STD_LOGIC_VECTOR(8 DOWNTO 0);
+
+  -----------------
+  -- Y/C signals --
+  -----------------
+  SIGNAL   luma         : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   luma_1       : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   luma_2       : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   luma_acc     : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   chroma       : STD_LOGIC_VECTOR(8 DOWNTO 0);
+  SIGNAL   chroma_1     : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL   chroma_2     : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL   chroma_acc   : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  
+  -- Delayed input signals
+  SIGNAL   blank_dly    : STD_LOGIC;
+  SIGNAL   burst_dly    : STD_LOGIC;
+  SIGNAL   csync_dly    : STD_LOGIC;
+  SIGNAL   sof_dly      : STD_LOGIC_VECTOR(1 DOWNTO 0);
+
+BEGIN
+
+  PROCESS
+  (
+    areset_n,    -- Global reset
+    ecs_clk,     -- Main clock
+    csync_n,     -- Composite synchro (active low)
+    blank,       -- Composite blanking
+    burst,       -- Burst enable flag
+    pal_ntsc,    -- PAL(0) / NTSC(1)
+    sof          -- Start of frame flag
+  )
+  BEGIN
+    IF (areset_n = '0') THEN
+      -- Color carrier phase
+      col_ctr <= (OTHERS => '0');
+      -- Y component
+      comp_YR <= (OTHERS => '0');
+      comp_YG <= (OTHERS => '0');
+      comp_YB <= (OTHERS => '0');
+      comp_Y2 <= (OTHERS => '0');
+      comp_Y3 <= (OTHERS => '0');
+      comp_Y4 <= (OTHERS => '0');
+      -- U component
+      comp_UR <= (OTHERS => '0');
+      comp_UG <= (OTHERS => '0');
+      comp_UB <= (OTHERS => '0');
+      comp_pU <= (OTHERS => '0');
+      comp_mU <= (OTHERS => '0');
+      sign_U  <= '0';
+      ampl_U  <= (OTHERS => '0');
+      -- V component
+      comp_VR <= (OTHERS => '0');
+      comp_VG <= (OTHERS => '0');
+      comp_VB <= (OTHERS => '0');
+      comp_pV <= (OTHERS => '0');
+      comp_mV <= (OTHERS => '0');
+      sign_V  <= '0';
+      ampl_V  <= (OTHERS => '0');
+    ELSIF (rising_edge(ecs_clk)) THEN
+      -----------------
+      -----------------
+      -- First stage --
+      -----------------
+      -----------------
+
+      -- RGB -> Y conversion :
+      ------------------------
+      --     Y = (0.299*R + 0.587*G + 0.114*B) * 140 / 256
+      --     Y =  0.164*R + 0.321*G + 0.062*B
+      -- 512*Y =     84*R +   164*G +    32*B
+      comp_YR <= "001010100" * unsigned(r_in);
+      comp_YG <= "010100100" * unsigned(g_in);
+      comp_YB <= "000100000" * unsigned(b_in);
+
+      -- RGB -> U conversion :
+      ------------------------
+      --     U = -0.147*R - 0.289*G + 0.436*B
+      -- 512*U =    -75*R -   148*G +   223*B
+      comp_UR <= "001001011" * unsigned(r_in);
+      comp_UG <= "010010100" * unsigned(g_in);
+      comp_UB <= "011011111" * unsigned(b_in);
+
+      -- RGB -> V conversion :
+      ------------------------
+      --     V =  0.615*R - 0.515*G - 0.100*B
+      -- 512*V =    315*R -   264*G -    51*B
+      comp_VR <= "100111011" * unsigned(r_in);
+      comp_VG <= "100001000" * unsigned(g_in);
+      comp_VB <= "000110011" * unsigned(b_in);
+      
+      -- Delayed signals :
+      --------------------
+      csync_dly <= csync_n;          -- to 2nd stage
+      blank_dly <= blank;            -- to 2nd stage
+      burst_dly <= burst;            -- to 2nd stage
+      sof_dly   <= sof_dly(0) & sof; -- to 3rd stage
+
+      ------------------
+      ------------------
+      -- Second stage --
+      ------------------
+      ------------------
+
+      -- Compute Y
+      IF (csync_dly = '0') THEN
+        -- Synchro level
+        comp_Y2 <= Y_LVL_SYNC;
+      ELSIF (blank_dly = '1') THEN
+        -- Blanking level
+        comp_Y2 <= Y_LVL_BLANK;
+      ELSE
+        -- Picture level
+        comp_Y2 <= std_logic_vector(comp_YR)
+                 + std_logic_vector(comp_YG)
+                 + std_logic_vector(comp_YB)
+                 + Y_LVL_PICT;
+      END IF;
+
+      -- Compute U
+      IF (burst_dly = '1') THEN
+        comp_pU <= mU_LVL_BURST;
+        comp_mU <= pU_LVL_BURST;
+      ELSE
+        comp_pU <= std_logic_vector('0' & comp_UB)
+                 - std_logic_vector('0' & comp_UG)
+                 - std_logic_vector('0' & comp_UR);
+        comp_mU <= std_logic_vector('0' & comp_UR)
+                 + std_logic_vector('0' & comp_UG)
+                 - std_logic_vector('0' & comp_UB);
+      END IF;
+
+      -- Compute V
+      IF (burst_dly = '1') THEN
+        IF (pal_ntsc = '1') THEN
+          -- NTSC burst
+          comp_pV <= (OTHERS => '0');
+          comp_mV <= (OTHERS => '0');
+        ELSE
+          -- PAL burst
+          comp_pV <= pU_LVL_BURST;
+          comp_mV <= mU_LVL_BURST;
+        END IF;
+      ELSE
+        comp_pV <= std_logic_vector('0' & comp_VR)
+                 - std_logic_vector('0' & comp_VG)
+                 - std_logic_vector('0' & comp_VB);
+        comp_mV <= std_logic_vector('0' & comp_VB)
+                 + std_logic_vector('0' & comp_VG)
+                 - std_logic_vector('0' & comp_VR);
+      END IF;
+
+      -----------------
+      -----------------
+      -- Third stage --
+      -----------------
+      -----------------
+      
+      -- Copy Y
+      comp_Y3 <= comp_Y2(16 DOWNTO 7);
+
+      -- Phase and amplitude for U,V
+      sign_U <= comp_pU(17);
+      sign_V <= comp_pV(17) XOR (vpos_lsb AND (NOT pal_ntsc));
+      IF (comp_pU(17) = '1') THEN
+        ampl_U <= comp_mU(16 DOWNTO 9);
+      ELSE
+        ampl_U <= comp_pU(16 DOWNTO 9);
+      END IF;
+      IF (comp_pV(17) = '1') THEN
+        ampl_V <= comp_mV(16 DOWNTO 9);
+      ELSE
+        ampl_V <= comp_pV(16 DOWNTO 9);
+      END IF;
+
+      -- Color carrier phase
+      IF (sof_dly(1) = '1') THEN
+        col_ctr <= (OTHERS => '0');
+      ELSE
+        -- +4 for NTSC, +5 for PAL
+        col_ctr <= col_ctr + ("0010" & (NOT pal_ntsc));
+      END IF;
+
+      ------------------
+      ------------------
+      -- Fourth stage --
+      ------------------
+      ------------------
+      
+      -- Copy Y
+      comp_Y4 <= comp_Y3;
+
+      -----------------
+      -----------------
+      -- Fifth stage --
+      -----------------
+      -----------------
+
+      -- Y/C signal
+      luma <= comp_Y4;
+      chroma <= comp_U + comp_V;
+
+    END IF;
+
+  END PROCESS;
+
+  -----------------------------------
+  -----------------------------------
+  -- 4th stage : chroma modulation --
+  -----------------------------------
+  -----------------------------------
+
+  tab_inst : sin_cos
+  PORT MAP
+  (
+    clk                => ecs_clk,
+    clk_ena            => '1',
+    sin_ph(4)          => col_ctr(4) XOR sign_U,
+    sin_ph(3 DOWNTO 0) => col_ctr(3 DOWNTO 0),
+    sin_amp            => ampl_U,
+    sin_out            => comp_U,
+    cos_ph(4)          => col_ctr(4) XOR sign_V,
+    cos_ph(3 DOWNTO 0) => col_ctr(3 DOWNTO 0),
+    cos_amp            => ampl_V,
+    cos_out            => comp_V
+  );
+
+  -----------------------------------
+  -- High-speed DAC with dithering --
+  -----------------------------------
+  PROCESS
+  (
+    areset_n,   -- Global reset
+    dac_clk,    -- DAC clock (114.545454 MHz)
+    luma,       -- Luminance data
+    chroma      -- Chrominance data
+  )
+  BEGIN
+    IF (areset_n = '0') THEN
+      luma_1     <= (OTHERS => '0');
+      luma_2     <= (OTHERS => '0');
+      luma_acc   <= (OTHERS => '0');
+      chroma_1   <= (OTHERS => '0');
+      chroma_2   <= (OTHERS => '0');
+      chroma_acc <= (OTHERS => '0');
+    ELSE
+      IF (rising_edge(dac_clk)) THEN
+        -- Clock domain crossing
+        luma_1   <= luma;
+        luma_2   <= luma_1;
+        chroma_1 <= (NOT chroma(8)) & chroma(7 DOWNTO 1);
+        chroma_2 <= chroma_1;
+        -- First order delta-sigma
+        luma_acc   <= luma_2 + ("00000000" & luma_acc(1 DOWNTO 0));
+        chroma_acc <= chroma_2 + ("000000" & chroma_acc(1 DOWNTO 0));
+      END IF;
+    END IF;
+  END PROCESS;
+  -- Y/C outputs
+  y_out <= luma_acc(9 DOWNTO 2);
+  c_out <= chroma_acc(7 DOWNTO 2);
+
+  -- raw luma/chroma
+  luma_out <= luma;
+  chroma_out <= chroma;
+
+END rtl;
Index: mcctv/usb/USBF_Declares.vhd
===================================================================
--- mcctv/usb/USBF_Declares.vhd	(nonexistent)
+++ mcctv/usb/USBF_Declares.vhd	(revision 181)
@@ -0,0 +1,91 @@
+--==============================================================================
+--  USB Interface Declares
+------------------------------------------------------------------
+--Copywrite Johns Hopkins University ECE department
+--This software may be freely used and modified as long as this header is retained. 
+------------------------------------------------------------------
+--Description: Defines constants and components used to make the FPGA act as a 
+--  HID USB peripheral, and communicate over the D+/D- lines with the host.
+--   
+-- Authors: Brian Duddie, Brian Miller, R.E. Jenkins
+-- Last Modification: Jan 3, 2009
+--==============================================================================
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--==================================================================
+package USBF_Declares is
+--==================================================================
+
+--====================================================
+--USB_DRVR COMPONENT Declaration        ----------------------
+--====================================================
+  component USB_DRVR1 is
+                       port(
+                         clk_usb       : in    std_logic;  --12MHz clock
+								 pll_lock		: in    std_logic;
+                         reset         : in    std_logic;  --fpga reset
+                         dminus        : inout std_logic;  -- USB differential D+ line
+                         dplus         : inout std_logic;  -- USB differential D+ line
+								 joyright_out 	: out   std_logic_vector(7 downto 0);
+								 joyleft_out 	: out   std_logic_vector(7 downto 0);
+								 mousex_out		: out   std_logic_vector(11 downto 0);
+								 mousey_out		: out   std_logic_vector(11 downto 0)
+                         );
+  end component;
+-------------------------------------------------------
+  component USBF_IFC1 is
+                       port(
+                         clk_usb       : in    std_logic;  --12MHz clock
+								 pll_lock		: in    std_logic;
+                         reset         : in    std_logic;  -- XST reset push button
+                         ----USB CONNECTIONS  ---------
+                         dplus         : inout std_logic;
+                         dminus        : inout std_logic;
+                         ----------------------------------
+								 joyright_out 	: out   std_logic_vector(7 downto 0);
+								 joyleft_out 	: out   std_logic_vector(7 downto 0);
+								 mousex_out		: out   std_logic_vector(11 downto 0);
+								 mousey_out		: out   std_logic_vector(11 downto 0)
+                         );
+  end component;
+  
+--====================================================
+--USB_DRVR COMPONENT Declaration        ----------------------
+--====================================================
+  component USB_DRVR2 is
+                       port(
+                         clk_usb       : in    std_logic;  --12MHz clock
+								 pll_lock		: in    std_logic;
+                         reset         : in    std_logic;  --fpga reset
+                         dminus        : inout std_logic;  -- USB differential D+ line
+                         dplus         : inout std_logic;  -- USB differential D+ line
+								 joyright_out 	: out   std_logic_vector(7 downto 0);
+								 joyleft_out 	: out   std_logic_vector(7 downto 0);
+								 mousex_out		: out   std_logic_vector(11 downto 0);
+								 mousey_out		: out   std_logic_vector(11 downto 0)
+                         );
+  end component;
+-------------------------------------------------------
+  component USBF_IFC2 is
+                       port(
+                         clk_usb       : in    std_logic;  --12MHz clock
+								 pll_lock		: in    std_logic;
+                         reset         : in    std_logic;  -- XST reset push button
+                         ----USB CONNECTIONS  ---------
+                         dplus         : inout std_logic;
+                         dminus        : inout std_logic;
+                         ----------------------------------
+								 joyright_out 	: out   std_logic_vector(7 downto 0);
+								 joyleft_out 	: out   std_logic_vector(7 downto 0);
+								 mousex_out		: out   std_logic_vector(11 downto 0);
+								 mousey_out		: out   std_logic_vector(11 downto 0)
+                         );
+  end component;
+
+--==============================================================================
+END PACKAGE USBF_Declares;
+--==============================================================================
+
+--==============================================================================
Index: mcctv/usb/USB_INTF2.vhd
===================================================================
--- mcctv/usb/USB_INTF2.vhd	(nonexistent)
+++ mcctv/usb/USB_INTF2.vhd	(revision 181)
@@ -0,0 +1,70 @@
+--This file contains 2 Entities making up an HID USB interface
+--===========================================================================
+--  USB Interface module - Copywrite Johns Hopkins University ECE Dept.
+--This code may be used and freely distributed as long as the JHU credit is retained.
+--============================================================================
+--Implements an HID USB enumeration and communication through a tranceiver implemented
+--in the FPGA to directly drive the USB diferential pair data lines.
+--On an XESS xst-2 or -3 board this requires a connection of the usb cable wires with a 1.5K 
+--pullup to 3.3V on the D+ or D- line, and the data lines connecting to 2 FPGA pins.
+--The bit rate is determined by which line has the pullup. This code is currently set up
+--for usb full speed (12 Mhz) operation, but can be easily changed for 1.5Mhz low speed.
+
+--The inputs and outputs are arrays(1 to 8) of std_logic_vector(7 downto 0).
+--These arrays are the data packets sent and received via USB reports. The I/O
+--buffers for USB transactions in the tranceiver are also 8 byte arrays.
+
+-- The interface acts as an HID class, thus only control and interrupt xfers are possible.
+-- Any commented page references are to "USB Complete", 3rd Edition, by Jan Axelson
+--
+-- Author: Robert Jenkins
+-- Last Modification: Jan 30, 2009
+--==============================================================================
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use WORK.USBF_Declares.all;             --Package containing declarations needed by the USB interface        
+
+--------------------------------------------------------------------------------
+entity USBF_IFC2 is
+  port(
+    clk_usb     	 	: in    std_logic;      --100MHz project clock
+	 pll_lock			: in std_logic;
+    reset       	: in    std_logic;      -- usually tied to the XST reset button.
+    ----USB CONNECTIONS                 -----------------------------------------
+    dplus       	: inout std_logic;      --differential + line to/from usb hub(pulled up to 3.3)
+    dminus      	: inout std_logic;      --differential minus line to/from usb hub
+    ------------------------------------------------------------
+	 joyright_out 	: out   std_logic_vector(7 downto 0);
+	 joyleft_out 	: out   std_logic_vector(7 downto 0);
+	 mousex_out		: out   std_logic_vector(11 downto 0);
+	 mousey_out		: out   std_logic_vector(11 downto 0)
+    );
+end USBF_IFC2;
+----------------------------------------------------------------------
+
+architecture arch of USBF_IFC2 is
+
+begin
+
+  UDRVR : USB_DRVR2                   
+    port map(
+		clk_usb       	=> clk_usb, 
+		pll_lock			=> pll_lock,
+		reset 			=> reset, 
+		dplus 			=> dplus, 
+		dminus 			=> dminus,
+		joyright_out	=> joyright_out,
+		joyleft_out		=> joyleft_out,
+		mousex_out		=> mousex_out,
+		mousey_out		=> mousey_out
+		);
+
+---=============================
+end arch;  --END of USBF_IFC
+---=============================
+
+
+
+
+
Index: mcctv/usb/rom_com.vhd
===================================================================
--- mcctv/usb/rom_com.vhd	(nonexistent)
+++ mcctv/usb/rom_com.vhd	(revision 181)
@@ -0,0 +1,173 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: rom_com.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY rom_com IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END rom_com;
+
+
+ARCHITECTURE SYN OF rom_com IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rden_a	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./usb/rom_com.mif",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=NONE",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 9,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		rden_a => rden,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./usb/rom_com.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./usb/rom_com.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=NONE"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com_inst.vhd TRUE
Index: mcctv/usb/rom_com2.cmp
===================================================================
--- mcctv/usb/rom_com2.cmp	(nonexistent)
+++ mcctv/usb/rom_com2.cmp	(revision 181)
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component rom_com2
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: mcctv/usb/usb_driver2.vhd
===================================================================
--- mcctv/usb/usb_driver2.vhd	(nonexistent)
+++ mcctv/usb/usb_driver2.vhd	(revision 181)
@@ -0,0 +1,1576 @@
+
+--===============================================================================
+---USB_DRVR Entity (Drives and Reads D+ and D- lines to send and receive packets)
+--===============================================================================
+-- USB Driver - Copywrite Hakim Haddadi arcade retro gaming.
+--------------------------------------------------
+--==============================================================================
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+use WORK.USBF_Declares.all;
+
+--------------------------------------------------
+entity USB_DRVR2 is
+  port(                                 
+    clk_usb       : in    std_logic;    -- 5MHz clock
+	 pll_lock		: in    std_logic;
+    reset         : in    std_logic;    -- fpga reset
+    dminus        : inout std_logic;    -- USB differential D+ line
+    dplus         : inout std_logic;    -- USB differential D+ line
+	 joyright_out 	: out   std_logic_vector(7 downto 0);
+	 joyleft_out 	: out   std_logic_vector(7 downto 0);
+	 mousex_out		: out   std_logic_vector(11 downto 0);
+	 mousey_out		: out   std_logic_vector(11 downto 0)
+    );
+end USB_DRVR2;
+---------------------------------------------------
+
+architecture arch of USB_DRVR2 is
+------------------------
+
+component sub_pll IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0				: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END component sub_pll;
+
+component rom_com1 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock			: IN STD_LOGIC  := '1';
+		rden			: IN STD_LOGIC  := '1';
+		q				: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component rom_com1;
+ 
+  signal dp_last, dp_prev, dp1_last,dm1_last    : std_logic;
+  signal nb_bits                 : std_logic_vector(3 downto 0);  --bit counter for receive bits
+  signal stuffin1        			: integer range 0 to 7;  --counters for stuff-bits out and in
+  signal usb_lock				 		: std_logic := '0';
+  --signal clk_usb						: std_logic;
+  signal reg_10bits					: std_logic_vector(9 downto 0);
+  signal reg_10bits_receive		: std_logic_vector(9 downto 0);
+  signal dp2_prev						: std_logic;
+  signal CLOCK12MHz					: std_logic;
+  signal CLOCK12MHz_receive		: std_logic;
+  signal token_pid2					: std_logic_vector(3 downto 0);
+  signal data_pkt1					: std_logic_vector(7 downto 0);
+  signal data_temp					: std_logic_vector(7 downto 0);
+  signal data_rom						: std_logic_vector(7 downto 0);
+  -- ROM signals
+  signal address_rom					: std_logic_vector(8 downto 0);
+  signal rom_out						: std_logic_vector(7 downto 0);
+  signal rden_sig						: std_logic;
+  
+  signal data_tosend					: std_logic_vector(7 downto 0);
+  signal nb_byte_tosend				: std_logic_vector(7 downto 0);
+  signal address_start				: std_logic_vector(8 downto 0);
+  signal dm_previous					: std_logic;
+  signal dp_previous					: std_logic;
+  signal dplus_buf1					: std_logic;
+  signal dplus_buf2					: std_logic;
+  signal dminus_buf1					: std_logic;
+  signal dminus_buf2					: std_logic;
+  signal start_sendcom				: std_logic;
+  signal send_frame					: std_logic;
+  signal usb_reset					: std_logic;
+  signal synch							: std_logic;
+  signal read_byte_valid			: std_logic;
+  signal read_byte_valid_c			: std_logic;
+  signal data_available				: std_logic;
+  signal data_valid					: std_logic; 
+  signal data_valid_temp			: std_logic;
+  signal gamepad_basic				: std_logic;  
+  signal detach_ack					: std_logic;
+  signal detach						: std_logic;
+  signal joystick_type						: std_logic;
+  signal joystick_updown						: std_logic;
+  signal set_command						: std_logic_vector(1 downto 0);
+  signal counter1						: std_logic_vector(7 downto 0);
+  signal counterdetach					: std_logic_vector(3 downto 0);
+  signal counter2							: std_logic_vector(3 downto 0); 
+  signal counter30ms						: std_logic_vector(18 downto 0);
+  signal counter1_3ms					: std_logic_vector(14 downto 0);
+  signal joyright_temp					: std_logic_vector(7 downto 0);  
+  signal joyleft_temp					: std_logic_vector(7 downto 0);
+  signal data_byte2						: std_logic_vector(7 downto 0);
+  
+  signal nb_reset							: std_logic_vector(7 downto 0);
+  signal val								: std_logic;
+  signal mouse_valid						: std_logic;	
+  signal mouse_counter1					: std_logic_vector(8 downto 0);  
+  
+  signal mousex_temp						: std_logic_vector(7 downto 0);  
+  signal mousey_temp						: std_logic_vector(7 downto 0);
+  signal mousex_ctr						: std_logic_vector(11 downto 0);  
+  signal mousey_ctr						: std_logic_vector(11 downto 0); 
+ 
+  type usb1_sm_type is (                 -- receive state machine
+    state1, state2, state3,              --,
+    state4);
+	 
+  type usb_com_type is (                 	--send state machine #1 to read D+/D- lines
+    Idle, 
+	 send1, send2,send3, reset_start,             			--
+	 send4, send5,send6, reset_released,            			--
+	 send_bit0, send_bit1,send_bit2,             			--
+	 send_bit3, send_bit4,send_bit5,             		--
+	 send_bit6, send_bit7,send15,             		--
+	 end_send1, end_send2, send_complete             		--
+ );
+
+  type usb_manage_type is (                 	--Tranceiver state machine #1 to read D+/D- lines
+    Idle, 
+	 usb_manage1, usb_manage2,             			-- 
+	 usb_reset_state, crc_complete, usb_waitdetachrelease, wait_for_deviceconnect,
+	 usb_wait30ms, end_set_address, end_set_configuration, end_set_idle,
+	 read_pktin2, read_pktin3, read_pktin4, wait_pktin4,
+	 setaddress_sendpkt1, setaddress_sendpkt1_end,
+	 setaddress_sendpkt2, setaddress_sendpkt2_end,
+	 setaddress_sendpkt3, setaddress_sendpkt3_end,	 
+	 send_ack, send_ack_start, send_ack_end,
+	 getreport_sendpkt1, getreport_sendpkt1_start, getreport_sendpkt1_end,
+	 wait_pktin1, wait_pktin2, wait_pktin3,
+	 wait_report_start, start_get_report,
+	 send_getreport_ack, send_getreport_ack_start, send_getreport_ack_end,
+	 start_get_data, 
+	 wait_read_byte2, wait_read_byte3, wait_read_byte4, wait_read_byte5, wait_read_byte6,
+	 wait_read_byte7, wait_read_byte8, wait_read_byte9, wait_read_byte10, wait_read_byte11,
+	 read_byte1, read_byte2, read_byte3, read_byte4, read_byte5, read_byte6,
+	 read_byte7, read_byte8, read_byte9, read_byte10, read_byte11,
+	 wait1, wait2, wait4, wait6,  
+	 wait20, wait21, wait30, wait40, 
+	 wait_ack2,
+	 usb_reset_1ms_start, usb_reset_1ms_wait1, usb_reset_1ms_wait2, usb_reset_1ms_release
+ ); 
+ 
+ type usb_detach_type is (                 	--Tranceiver state machine #1 to read D+/D- lines
+    Idle, 
+	 detach_start, detach_wait,detach_valid             			--            		--
+ );
+ 
+ type mouse_state_type is (                 	--Tranceiver state machine #1 to read D+/D- lines
+    Idle, 
+	 state1             			--            		--
+ );
+	 
+  signal                                usb_detach             : usb_detach_type;
+  signal                                usb1_state             : usb1_sm_type;
+  signal                                usb_send_com    			: usb_com_type;
+  signal                                usb_manage    			: usb_manage_type;
+  signal                                mouse_state    			: mouse_state_type; 
+  ------------------------------------------------------------
+
+  ATTRIBUTE keep : boolean;
+  ATTRIBUTE keep OF dminus  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF dplus  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF clk_usb  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF CLOCK12MHz  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF rom_out  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF joyright_out  : SIGNAL IS TRUE;  
+  ATTRIBUTE keep OF joyleft_out  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF joyright_temp  : SIGNAL IS TRUE;  
+  ATTRIBUTE keep OF joyleft_temp  : SIGNAL IS TRUE;
+ 
+begin
+
+----------------------------------
+-- instantiate the rom commands --
+----------------------------------
+rom_com_inst : rom_com1 
+PORT MAP (
+			address	 	=> address_rom,
+			clock	 		=> clk_usb,
+			rden	 		=> rden_sig AND CLOCK12MHz,
+			q	 			=> rom_out
+			);
+		
+   usb_lock <= pll_lock;
+  
+-----------------------------
+-- update of joystick data	--
+-----------------------------
+  PROCESS
+  (
+    usb_lock, 		-- External asynchronous reset
+    clk_usb    	-- 15 MHz clock (usb over sampling)
+
+  )
+  BEGIN
+    -- 
+   IF (usb_lock = '0') THEN
+		joyright_out 			<= "11111111";
+		joyleft_out 			<= "11111111";
+   ELSIF (rising_edge(clk_usb)) THEN
+		IF (data_available = '1') THEN
+			IF (data_valid = '1') THEN
+				-- bit 0 : 2
+				-- bit 1 : 4
+				-- bit 2 : 3
+				-- bit 3 : 1
+				-- bit 4 : fire button / start
+				-- bit 5 : fire button / start
+				-- bit 6 : button front right "2"  
+				-- bit 7 : button front right "1"
+				joyright_out <= joyright_temp;
+				-- bit 0 : right
+				-- bit 1 : left
+				-- bit 2 : down
+				-- bit 3 : up
+				-- bit 4 : fire button / select
+				-- bit 5 : fire button / select
+				-- bit 6 : button front left "2"  
+				-- bit 7 : button front left "1"							
+				joyleft_out <= joyleft_temp;
+			ELSE
+				-- bit 0 : 2
+				-- bit 1 : 4
+				-- bit 2 : 3
+				-- bit 3 : 1
+				-- bit 4 : fire button / start
+				-- bit 5 : fire button / start
+				-- bit 6 : button front right "2"  
+				-- bit 7 : button front right "1"
+				joyright_out <= joyright_temp;
+				-- bit 0 : Not active
+				-- bit 1 : Not active
+				-- bit 2 : Not active
+				-- bit 3 : Not active
+				-- bit 4 : fire button / select
+				-- bit 5 : fire button / select
+				-- bit 6 : button front left "2"  
+				-- bit 7 : button front left "1"							
+				joyleft_out(7 downto 4) <= joyleft_temp(7 downto 4);	
+				joyleft_out(3 downto 0) <= "1111";
+			END IF;
+      END IF;
+   END IF;			
+  END PROCESS;
+	
+ ----------------------------------------------
+ --  usb clock enable generation for sending --
+ ----------------------------------------------
+  PROCESS
+  (
+    usb_lock, -- reset_process, 	-- External asynchronous reset
+    clk_usb    		-- over sampling clk 15MHz
+  )
+  BEGIN
+    -- 
+   IF (usb_lock = '0') THEN
+		reg_10bits <= "0000000001";
+   ELSIF (rising_edge(clk_usb)) THEN
+		reg_10bits 		<= reg_10bits(8 downto 0) & reg_10bits(9); -- 
+   END IF;			
+  END PROCESS;
+  
+ -- update clock enable USB
+ CLOCK12MHz 		<= reg_10bits(4);
+ 
+ ------------------------------------------------
+ --  usb clock enable generation for receiving --
+ ------------------------------------------------
+ -- process generating a 15 MHz clk enable signal in phase with the incoming data from the device
+ -- the process is using an oversampling clk of 15 MHz
+  PROCESS
+  (
+    usb_lock, --reset_process, 		-- External asynchronous reset
+    clk_usb    -- over sampling clk 48MHz
+  )
+  BEGIN
+    -- 
+   IF (usb_lock = '0') THEN
+		reg_10bits_receive 	<= "0000000001";
+		dp2_prev     		 	<= dplus_buf2;
+   ELSIF (rising_edge(clk_usb)) THEN
+		dp2_prev     			<= dplus_buf2;           -- sample the input D+ line
+		IF (dp2_prev /= dplus_buf2) THEN
+			reg_10bits_receive <= "0000000001";				-- reset the phase of the USB clk
+		ELSE
+			reg_10bits_receive 				<= reg_10bits_receive(8 downto 0) & reg_10bits_receive(9); -- 
+      END IF;
+   END IF;			
+  END PROCESS;
+  
+  -- update clock USB
+ CLOCK12MHz_receive 		<= reg_10bits_receive(4); 
+  
+  --------------------------------------------------------------------------------------
+  ---------------------  buffering of Dplus - Dminus to avoid metastability ------------
+  --------------------------------------------------------------------------------------
+  process (clk_usb, usb_lock) is
+  begin
+    if usb_lock = '0' then
+		dplus_buf1      	<= '0';
+		dplus_buf2      	<= '0';
+		dminus_buf1      	<= '0';
+		dminus_buf2      	<= '0';
+    elsif rising_edge(clk_usb) then     	--
+		dplus_buf1     	<= dplus;  
+		dplus_buf2     	<= dplus_buf1;
+		dminus_buf1      	<= dminus;
+		dminus_buf2      	<= dminus_buf1;
+    end if;
+  end process;
+  
+  ---------------------------------------------------------------------
+  ------------------  state machine for acquiring usb data
+  ---------------------------------------------------------------------
+  process (reset, clk_usb, CLOCK12MHz_receive) is
+  begin
+    if (reset = '0') then    
+		dp1_last				<= dplus_buf2;
+		dm1_last				<= dminus_buf2;
+      data_pkt1			<= "00000000";
+      data_temp   		<= "00000000";
+		read_byte_valid	<= '0';
+		usb1_state       	<= state1;   
+		nb_bits				<= "0000";
+		stuffin1          <= 0;
+		synch       		<= '0';
+    elsif (rising_edge(clk_usb) AND CLOCK12MHz_receive = '1') then     
+      case usb1_state is
+        -------------- state1 ----------------
+			when state1		=>   
+				read_byte_valid	<= '1';
+				data_pkt1   <= "00000000";
+				data_temp   <= "00000000";
+				if dplus_buf2 = '0' and dminus_buf2 = '0' then
+					usb1_state	<= state1;				-- reset state
+				elsif dplus_buf2 = '1' and dminus_buf2 = '0' then
+					dp1_last		<= dplus_buf2;
+					dm1_last		<= dminus_buf2;
+					usb1_state	<= state2;				-- go to state2 and wait for synch
+				end if;
+				nb_bits				<= "0000"; 
+		  -------------- state2 ----------------
+        when state2     =>
+				dp1_last		<= dplus_buf2;
+				dm1_last		<= dminus_buf2;
+				if dp1_last /= dplus_buf2 and dm1_last /= dminus_buf2 then               
+					nb_bits     	<= nb_bits + 1;			-- start of synch
+				elsif dplus_buf2 = '0' and dminus_buf2 = '0' then  
+					usb1_state	<= state1;				-- reset state
+					nb_bits		<= "0000";
+				end if;
+  
+          if nb_bits = "0110" then               
+				usb1_state	<= state3;				-- go to state 3 and wait for final synch
+          end if; 
+		  -------------- state3 ----------------
+        when state3     =>
+				dp1_last		<= dplus_buf2;
+				dm1_last		<= dminus_buf2;
+          if dplus_buf2 = '0' and dminus_buf2 = '1' then               
+            nb_bits     <= nb_bits + 1;			-- start of synch
+          elsif dplus_buf2 = '0' and dminus_buf2 = '0' then  
+            usb1_state	<= state1;				-- reset state
+				data_pkt1   <= "00000000";
+				data_temp   <= "00000000";
+				nb_bits		<= "0000";
+          end if;
+
+			 if nb_bits = "0111" then               
+				usb1_state	<= state4;				-- synch byte complete start aquiring packets
+				data_pkt1   <= "10000000";
+				data_temp	<= "10000000";
+				read_byte_valid	<= Not read_byte_valid;
+				nb_bits		<= "0000";
+				synch       <= '1';
+          end if; 
+		  -------------- state4 ----------------
+        when state4     =>
+		if detach = '1' then
+			usb1_state   	<= state1;
+		else
+          if dplus_buf2 = '0' and dminus_buf2 = '0' then  
+            usb1_state	<= state1;				-- reset state
+				data_pkt1   <= data_temp;
+				data_temp   <= "00000000";
+				nb_bits		<= "0000";
+			 else
+				dp1_last        <= dplus_buf2;
+				
+				if (stuffin1 = 6 and nb_bits = "0000") then
+					stuffin1           <= 0;
+					val					 <= '1';	
+				elsif stuffin1 = 6 then           				--	after 6 '1's in a row = This is a stuff bit.
+					stuffin1           <= 0;     				--	ignore it and reset the stuff count.
+					val					 <= '0';
+				else                          				--	no stuff bit, get the real bit based on D+/D- lines. 
+					val					 <= '0';
+					nb_bits         <= nb_bits + 1;  	--	Count the real bits. Current 'bitin' is always coming in.
+					if dp1_last = dplus_buf2 then     				--	NRZI test. no change -> 1
+						stuffin1           <= stuffin1 + 1;  	--	count the consecutive 1's
+						if(nb_bits = "0000") then
+							data_temp(0) <= '1';
+						elsif(nb_bits = "0001") then
+							data_temp(1) <= '1';
+						elsif(nb_bits = "0010") then
+							data_temp(2) <= '1';
+						elsif(nb_bits = "0011") then
+							data_temp(3) <= '1';
+						elsif(nb_bits = "0100") then
+							data_temp(4) <= '1';
+						elsif(nb_bits = "0101") then
+							data_temp(5) <= '1';
+						elsif(nb_bits = "0110") then
+							data_temp(6) <= '1';
+						else
+							data_temp(7) <= '1';
+						end if;
+					else
+						if(nb_bits = "0000") then
+							data_temp(0) <= '0';
+						elsif(nb_bits = "0001") then
+							data_temp(1) <= '0';
+						elsif(nb_bits = "0010") then
+							data_temp(2) <= '0';
+						elsif(nb_bits = "0011") then
+							data_temp(3) <= '0';
+						elsif(nb_bits = "0100") then
+							data_temp(4) <= '0';
+						elsif(nb_bits = "0101") then
+							data_temp(5) <= '0';
+						elsif(nb_bits = "0110") then
+							data_temp(6) <= '0';
+						else
+							data_temp(7) <= '0';
+						end if;
+						stuffin1         	<= 0;     --reset the stuff-bit count when a 0
+					end if;
+				end if;
+			end if;
+			
+			if (nb_bits = "0111") AND (stuffin1 /= 6) then  
+				usb1_state	<= state4;
+				nb_bits		<= "0000"; 
+         end if; 
+			
+			if nb_bits = "0000" AND synch = '1' then  
+				synch       <= '0';
+			elsif nb_bits = "0000" AND val = '1' then
+				data_pkt1   <= data_temp;
+			elsif nb_bits = "0000" then
+				data_pkt1   <= data_temp;			
+				read_byte_valid	<= Not read_byte_valid;
+         end if; 
+		end if;
+		when others  => 
+			 usb1_state <= state1;
+			 nb_bits		<= "0000";
+	   end case;
+    end if;
+  end process; 		 
+  
+  ------------------------------------------------------
+  ------  state machine for sending usb data
+  ------------------------------------------------------
+  process (usb_lock, clk_usb, CLOCK12MHz) is
+  begin
+    if (usb_lock = '0') then                                 
+      data_tosend			<= "00000000";
+		nb_byte_tosend		<= "00000000";
+		dp_previous			<= '1';
+		dm_previous			<= '0';
+		dplus					<= '1';
+		dminus				<= '0';
+		usb_send_com		<= idle;
+    elsif (rising_edge(clk_usb) AND CLOCK12MHz = '1') then     
+      case usb_send_com is
+        -------------- wait for the reset start trigger ----------------
+			when idle		=>   
+				data_tosend   <= "00000000";
+				send_frame		<= '0';
+				if (usb_reset = '1') then				-- the start of sending data is initiated by the usb manage state machine
+					usb_send_com	<= reset_start;	-- reset start state
+					dplus			<= '0';
+					dminus		<= '0';
+				else 
+					usb_send_com	<= idle;					-- go to idle state
+				end if;
+        -------------- wait for the start trigger ----------------
+			when reset_start		=>   
+				if (usb_reset = '0') then					-- The reset is released
+					usb_send_com	<= reset_released;	-- end of reset state
+					dplus				<= 'Z';
+					dminus			<= 'Z';
+				else 
+					usb_send_com	<= reset_start;			
+				end if;				
+        -------------- wait for the start trigger ----------------
+			when reset_released		=>   
+				data_tosend   <= "00000000";
+				send_frame		<= '0';
+				if (usb_reset = '1') then
+					dplus				<= '0';
+					dminus			<= '0';
+					usb_send_com	<= reset_start;
+				elsif (start_sendcom = '1') then				-- the start of sending data is initiated by the usb manage state machine
+					usb_send_com	<= send1;				-- next state
+					rden_sig			<= '1';					
+					address_rom		<= address_start;		-- inialise the address_com with the address set by the usb state machine
+				else 
+					dplus				<= 'Z';
+					dminus			<= 'Z';
+					usb_send_com	<= reset_released;	-- wait for send com trigger
+				end if;
+		  -------------- prepare for the next read ----------------
+        when send1     =>              
+				address_rom			<= address_rom + "000000001";	-- prepare for the next read
+				rden_sig				<= '1';					-- read the first byte
+				usb_send_com		<= send2;		  
+		  -------------- read the rom first byte ----------------
+        when send2     =>  
+				nb_byte_tosend		<= rom_out;				-- read the first byte
+				usb_send_com		<= send3;
+		  -------------- read the next bytes to send ----------------
+        when send3     =>    
+				data_tosend			<= rom_out;				-- read the next byte
+				rden_sig				<= '0';
+				usb_send_com		<= send_bit0;
+		  -------------- send_bit0 ----------------
+        when send_bit0 =>
+		  	 nb_byte_tosend   <= nb_byte_tosend - "00000001";
+			 rden_sig			<= '0';					-- disable the rom read
+          if data_tosend(0) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit1;
+		  -------------- send_bit1 ----------------			 
+		  when send_bit1 =>
+          if data_tosend(1) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+				else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit2;
+		  -------------- send_bit2 ----------------
+        when send_bit2 =>
+          if data_tosend(2) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit3;
+		  -------------- send_bit3 ----------------			 
+		  when send_bit3 =>
+          if data_tosend(3) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit4;
+		  -------------- send_bit4 ----------------
+        when send_bit4 =>
+          if data_tosend(4) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit5;
+		  -------------- send_bit5 ----------------			 
+		  when send_bit5 =>
+          if data_tosend(5) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 address_rom	<= address_rom + "000000001";	-- prepare for the next read
+			 rden_sig		<= '1';								
+			 usb_send_com	<= send_bit6;
+		  -------------- send_bit6 ----------------
+        when send_bit6 =>
+          if data_tosend(6) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 rden_sig		<= '0';
+			 usb_send_com	<= send_bit7;
+		  -------------- send_bit7 ----------------			 
+		  when send_bit7 =>
+          if data_tosend(7) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 data_tosend 	<= rom_out;
+			 rden_sig		<= '0';								
+			 if nb_byte_tosend = "00000000" then
+				usb_send_com	<= end_send1;
+			 else
+				usb_send_com	<= send_bit0; -- send next byte
+			 end if;
+		  -------------- send_end of frame ----------------			 
+		  when end_send1 =>              
+			 dplus		<= '0';
+			 dminus		<= '0';
+			 usb_send_com	<= end_send2; 
+		  -------------- send_end of frame ----------------			 
+		  when end_send2 =>              
+			 dplus			<= '0';
+			 dminus			<= '0';
+			 usb_send_com	<= send_complete; 
+		  -------------- send_complete ----------------			 
+		  when send_complete =>              
+			 send_frame		<= '1';
+			 dplus			<= 'Z';
+			 dminus			<= 'Z';
+			 dp_previous	<= '1';
+			 dm_previous	<= '0';
+			 usb_send_com	<= reset_released; 	
+		  when others  => 
+			 usb_send_com <= idle;		 
+	   end case;
+    end if;
+  end process; 		 
+  
+  
+  --------------------------------------------------------------------------
+  ------  state machine for managing sending and receiving usb data
+  --------------------------------------------------------------------------
+  process (usb_lock, clk_usb) is
+  begin
+    if (usb_lock = '0') then 
+		joystick_type 		<= '0';
+		usb_reset			<= '0';
+		data_available		<= '0';
+		data_valid			<= '0';
+		data_valid_temp	<= '0';
+      start_sendcom		<= '0';
+		counter1				<= "11111111";
+		counter2				<= "1000";
+		counter30ms			<= "0101100110000100101";
+		counter1_3ms		<= "100000100011011";
+		detach_ack			<= '0';
+		usb_manage			<= idle;
+		
+    elsif (falling_edge(clk_usb)) then     
+      case usb_manage is
+        -------------- idle state ----------------
+			when idle		=>   
+				set_command				<= "00";
+				start_sendcom			<= '0';
+				joystick_type 			<= '0';
+				mouse_valid				<= '0';
+				if dplus = '1' then	
+					usb_manage			<= wait_for_deviceconnect;	
+				else 
+					usb_manage			<= idle;
+				end if; -- 
+		  -------------- confirm device connected ----------------
+        when wait_for_deviceconnect     =>              
+				counter1					<= counter1 - 1;
+				if counter1	= "00000000" then
+					usb_reset			<= '1';
+					usb_manage			<= usb_reset_state;	
+				else
+					usb_manage			<= wait_for_deviceconnect;
+				end if;		
+		  -------------- reset device state ----------------
+        when usb_reset_state     =>              
+				counter30ms				<= counter30ms - 1;
+				if counter30ms	 = "0000000000000000000" then
+				   counter30ms			<= "1111111111111111111";
+					counter1_3ms		<= "100000100011011";
+					counter2				<= "1011";
+					usb_reset			<= '0';
+					detach_ack			<= '1';
+					nb_reset	 			<= "00011101"; -- 29 keep alive
+					usb_manage			<= usb_reset_1ms_start;	
+				else
+					usb_manage			<= usb_reset_state;
+				end if;
+		  -------------- usb_reset_1ms_start ----------------
+        when usb_reset_1ms_start     =>              
+				counter1_3ms				<= counter1_3ms - 1;
+				if counter1_3ms	 = "0000000000000000" then
+					counter1_3ms		<= "100000100011011";
+					counter2				<= "1011";
+					counter1_3ms		<= counter1_3ms - 1;
+					detach_ack			<= '0';
+					usb_reset			<= '1';
+					usb_manage			<= usb_reset_1ms_wait1;	
+				else
+					usb_manage			<= usb_reset_1ms_start;
+				end if;			
+		  -------------- usb_reset_1ms_start ----------------
+        when usb_reset_1ms_wait1     =>  
+				usb_reset				<= '1';
+				counter2					<= counter2 - '1';
+				if counter2 = "0000" then
+					usb_reset			<= '0';
+					usb_manage			<= usb_reset_1ms_release;	
+				else
+					usb_manage			<= usb_reset_1ms_wait1;
+				end if;
+		
+		  -------------- usb_reset_1ms_start ----------------
+        when usb_reset_1ms_release     =>          
+				usb_reset				<= '0';		  
+				nb_reset					<= nb_reset - 1;
+				if nb_reset	 = "00000000" then
+					usb_manage			<= usb_manage2;	
+				else
+					counter1_3ms		<= "100000100011011";
+					counter2				<= "1011";
+					usb_manage			<= usb_reset_1ms_start;
+				end if;				
+	
+		  -------------- reset release state ----------------
+        when usb_wait30ms     =>              
+				counter1			<= counter1 - 1;
+				if counter1	= "00000000" then
+					detach_ack		<= '0';
+					counter1			<= "11111111";
+					usb_manage			<= usb_waitdetachrelease;	
+				else
+					usb_manage			<= usb_wait30ms;
+				end if;	
+		  -------------- confirm device attached ----------------
+        when usb_waitdetachrelease     =>              
+				counter2				<= counter2 - 1;
+				if counter2	= "0000" then
+					usb_manage			<= usb_manage2;	
+				else
+					usb_manage			<= usb_waitdetachrelease;
+				end if;
+		  -------------- end of reset state ----------------
+        when usb_manage2     =>  
+				if detach = '1' then
+					usb_manage   		<= idle;
+				else
+					start_sendcom	<= '0';
+					address_start	<= "000010010";
+					usb_manage		<= wait1;	-- start set address	
+				end if;	
+		  ------------------------------------------------
+		  -------------- SET ADDRESS 0x01 ----------------
+		  ------------------------------------------------
+		  
+		  -------------- waiting state -------------------
+        when wait1 =>
+				counter2					<= counter2 - 1;
+				if counter2	= "0000" then
+					counter2				<= "1111";
+					usb_manage			<= setaddress_sendpkt1;		  
+				else
+					usb_manage			<= wait1;
+				end if;			 
+		  -------------- send first packet "SETUP" packet ----------------
+        when setaddress_sendpkt1     =>  
+				start_sendcom			<= '1';
+				if set_command = "00" then
+					-- set address
+					address_start		<= "000010010"; -- 0x12  - 0x2D 0x00 0x10  - 3 bytes
+				elsif set_command = "01" then
+					-- set configuration
+					address_start		<= "001010000"; -- 0x50  - 0x2D 0x01 0xE8  - 3 bytes
+				else
+					-- set idle
+					address_start		<= "001110000"; -- 0x70  - 0x2D 0x01 0xE8  - 3 bytes
+				end if;
+				usb_manage				<= setaddress_sendpkt1_end; -- 
+		  -------------- wait for completion of sending frame ----------------			 
+		  when setaddress_sendpkt1_end =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom	<= '0';
+						counter1			<= "01010011";
+						usb_manage		<= wait2;
+					else 
+						usb_manage		<= setaddress_sendpkt1_end;
+					end if;
+				end if;
+			---------------------  waiting state ----------------------
+			when wait2 =>
+				counter1					<= counter1 - 1;
+				if counter1	= "00000000" then
+					counter1				<= "01010011";
+					usb_manage			<= setaddress_sendpkt2;		  
+				else
+					usb_manage			<= wait2;
+				end if;			 
+		  -------------- send the data packet for set address ---------
+        when setaddress_sendpkt2     =>  
+				start_sendcom		<= '1';
+				if set_command = "00" then
+					-- set address
+					address_start		<= "000010111"; -- 0x17  -   - 11 bytes
+				elsif set_command = "01" then
+					-- set configuration
+					address_start		<= "001010101"; -- 0x55  -   - 11 bytes
+				else
+					-- set idle
+					address_start		<= "001110101"; -- 0x75  -   - 11 bytes
+				end if;
+				usb_manage			<= setaddress_sendpkt2_end; -- 	
+		  -------------- wait for completion of sending frame ----------------			 
+		  when setaddress_sendpkt2_end =>
+			 if detach = '1' then
+					usb_manage   	<= idle;
+			 else
+				if send_frame = '1' then  
+					start_sendcom			<= '0';
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= wait_ack2;
+				else 
+					usb_manage				<= setaddress_sendpkt2_end;
+				end if;
+			end if;
+		  -------------- waiting ACK ----------------
+        when wait_ack2 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					counter1_3ms			<= counter1_3ms - 1;
+					if data_pkt1 = "11010010" then
+						counter1_3ms		<= "100000100011011";
+						usb_manage			<= wait4;		-- ack go top the next stage
+					elsif counter1_3ms	= "000000000000000" then
+						counter1_3ms		<= "100000100011011"; -- no ack, retry sending the command
+						usb_manage			<= setaddress_sendpkt1;
+					else
+						usb_manage			<= wait_ack2;
+					end if;
+				end if;
+		  ---------------- waiting state  ---------------------
+		  when wait4 =>
+				counter2			<= counter2 - 1;
+				if counter2	= "0000" then
+					counter2		<= "1111";
+					usb_manage			<= setaddress_sendpkt3;		  
+				else
+					usb_manage					<= wait4;
+				end if;			 
+		  -------------- prepare for sending the second packet ----------------
+        when setaddress_sendpkt3     =>  
+				start_sendcom		<= '1';
+				if set_command = "00" then
+					-- set address
+					address_start		<= "000100100"; -- 0x24  -   - 4 bytes
+				elsif set_command = "01" then
+					-- set configuration
+					address_start		<= "001100010"; -- 0x62  -   - 4 bytes
+				else
+					-- set idle
+					address_start		<= "010000010"; -- 0x82  -   - 4 bytes
+				end if;
+				usb_manage			<= setaddress_sendpkt3_end; -- 
+		  -------------- wait for completion of sending frame ----------------			 
+		  when setaddress_sendpkt3_end =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom			<= '0';
+						counter1_3ms			<= "100000100011011";
+						usb_manage				<= wait_pktin1;
+					else 
+						usb_manage				<= setaddress_sendpkt3_end;
+					end if;
+				end if;
+		  -------------- waiting for 1st byte ----------------
+        when wait_pktin1 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					counter1_3ms			<= counter1_3ms - 1;
+					if data_pkt1 = "10000000" then -- 0x80 wait for synch
+						usb_manage			<= wait_pktin2;		-- ack go to the next stage
+					elsif counter1_3ms	= "000000000000000" then
+						counter1_3ms		<= "100000100011011";    -- no ack, retry sending the command
+						usb_manage			<= setaddress_sendpkt3;
+					else
+						usb_manage			<= wait_pktin1;
+					end if;
+				end if;
+		  --------------  pktin2 "0x4B"  -------------------------
+		  when wait_pktin2 =>
+				if detach = '1' then
+					usb_manage   		<= idle;
+				else
+					if read_byte_valid = '0' then
+						usb_manage		<= wait_pktin2;	  
+					else
+						usb_manage		<= read_pktin2;
+					end if;	
+				end if;
+		  ------------------ read_pktin2 "0x4B" ---------------------
+		  when read_pktin2 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if data_pkt1 = "01001011" then -- 0x4B
+						usb_manage			<= wait_pktin3;					-- ack go top the next stage
+					else 
+						usb_manage			<= setaddress_sendpkt3; -- no ack, retry sending the command
+					end if;
+				end if;	
+		  --------------  pktin3 "0x00"  -------------------------
+		  when wait_pktin3 =>
+				if detach = '1' then
+					usb_manage   		<= idle;
+				else
+					if read_byte_valid = '1'  then
+						usb_manage		<= wait_pktin3;	  
+					else
+						usb_manage		<= read_pktin3;
+					end if;	
+				end if;
+		  ------------------ read_pktin3 "0x00" ---------------------
+		  when read_pktin3 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if data_pkt1 = "00000000" then -- 0x00
+						usb_manage			<= wait_pktin4;					-- ack go top the next stage
+					else 
+						usb_manage			<= setaddress_sendpkt3; -- no ack, retry sending the command
+					end if;
+				end if;	
+		  --------------  pktin4 "0x00"  -------------------------
+		  when wait_pktin4 =>
+				if detach = '1' then
+					usb_manage   		<= idle;
+				else
+					if read_byte_valid = '0' then
+						usb_manage		<= wait_pktin4;	  
+					else
+						usb_manage		<= read_pktin4;
+					end if;	
+				end if;
+		  ------------------ read_pktin4 "0x00" ---------------------
+		  when read_pktin4 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if data_pkt1 = "00000000" then -- 0x00
+						counter1				<= "00001111"; 
+						usb_manage			<= wait6;					-- go to "send ack" state
+					else 
+						usb_manage			<= setaddress_sendpkt3; -- no ack, retry sending the command
+					end if;
+				end if;	
+		  --------------------   waiting state before sending ack  --------------------------
+        when wait6 =>
+				counter1					<= counter1 - 1;
+				if counter1	= "00000000" then
+					counter1				<= "11111111";
+					usb_manage			<= send_ack;		  
+				else
+					usb_manage			<= wait6;
+				end if;	
+		  -------------- inialise ROM address for send ack ----------------
+        when send_ack     =>  
+				start_sendcom		<= '1';
+				address_start		<= "001000000"; -- 0x40  -   - 2 bytes
+				usb_manage			<= send_ack_end; -- send_ack_start;	-- 	
+		  -------------- wait for completion of sending frame ----------------			 
+		  when send_ack_end =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom			<= '0';
+						counter1_3ms			<= "000000000000001";
+						if set_command = "00" then
+							usb_manage				<= end_set_address;
+						elsif set_command = "01" then
+							usb_manage				<= end_set_configuration;
+						else
+							usb_manage				<= end_set_idle;
+						end if;
+					else 
+						usb_manage				<= send_ack_end;
+					end if;	
+				end if;
+		  ------------------------------  End of Set Address   -----------------------------
+		  
+        when end_set_address =>
+				counter1_3ms					<= counter1_3ms - 1;
+				if counter1_3ms	= "000000000000000" then
+					counter1_3ms				<= "100000100011011";
+					set_command					<= "01"; -- set_command set to SetConfiguration
+					nb_reset	 					<= "00000000"; -- 1 keep alive
+					usb_manage					<= usb_reset_1ms_start;		  
+				else
+					usb_manage					<= end_set_address;
+				end if; 
+				
+        when end_set_configuration =>
+				counter1_3ms					<= counter1_3ms - 1;
+				if counter1_3ms	= "000000000000000" then
+					counter1_3ms				<= "100000100011011";
+					set_command					<= "10"; -- set_command set to SetConfiguration
+					nb_reset	 					<= "00000000"; -- 1 keep alive
+					usb_manage					<= usb_reset_1ms_start;		  
+				else
+					usb_manage					<= end_set_configuration;
+				end if; 
+
+		  when end_set_idle =>
+				counter1_3ms					<= counter1_3ms - 1;
+				if counter1_3ms	= "000000000000000" then
+					counter1_3ms				<= "100000100011011";
+					counter1						<= "00011001";
+					set_command					<= "00"; -- set_command set to Setaddress in case of a detach/attach
+					usb_manage					<= wait21; -- wait20; -- go to get report	  
+				else
+					usb_manage					<= end_set_idle;
+				end if; 
+
+
+			---------------------------------------------------------------
+			---------------------------------------------------------------
+			---------------------------------------------------------------
+			-------------- GET REPORT ----------------
+        when wait20 =>    -- wait 1.3ms * 9
+				counter1_3ms				<= counter1_3ms - 1;
+				if counter1_3ms	= "000000000000000" then
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= wait21;		  
+				else
+					usb_manage				<= wait20;
+				end if;		
+		  ---------------------   wait  -------------
+        when wait21 =>    -- 
+				counter1						<= counter1 - 1;
+				if counter1	= "00000000" then
+					data_available			<=	'0';
+					data_valid				<= '0';
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= getreport_sendpkt1;		  
+				else
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= wait21;
+				end if;		
+		  -------------- read the next bytes to send ----------------
+        when getreport_sendpkt1     =>  
+				start_sendcom		<= '1';
+				address_start		<= "010010000"; -- 0x90  - 0x69 0x81 0x58  - 3 bytes
+				usb_manage			<= getreport_sendpkt1_end; 
+		  -------------- wait for completion of sending frame ----------------			 
+		  when getreport_sendpkt1_end =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom		<= '0';
+						counter1				<= "00000111";
+						usb_manage			<= wait30;
+					else 
+						usb_manage			<= getreport_sendpkt1_end;
+					end if;
+				end if;
+			-------------   waiting state  ------------------------
+		   when wait30 =>
+				counter1						<= counter1 - 1;
+				if counter1	= "00000000" then
+					counter1					<= "11111111";
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= wait_report_start;		  
+				else
+					usb_manage				<= wait30;
+				end if;			 
+		  -------------- waiting ACK ----------------
+        when wait_report_start =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					counter1_3ms			<= counter1_3ms - 1;
+					if data_pkt1 = "10000000" then  -- wait for synch
+						counter1_3ms		<= "100000100011011";
+						counter1				<= "01111000";
+						read_byte_valid_c <= read_byte_valid;
+						usb_manage			<= start_get_data;	-- ack go top the next stage
+					elsif counter1_3ms	= "000000000000000" then
+						counter1_3ms		<= "100000100011011"; 	-- no ack, retry sending the command
+						usb_manage			<= getreport_sendpkt1;
+					else
+						usb_manage			<= wait_report_start;
+					end if;
+				end if;
+		  --------------  byte1  -------------------------
+		  when start_get_data =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c then
+						usb_manage			<= start_get_data;	  
+					else
+						read_byte_valid_c <= read_byte_valid;
+						usb_manage			<= read_byte1;
+					end if;	
+				end if;
+		  ------------------ read_byte1 ---------------------
+		  when read_byte1 =>
+				if (data_pkt1 = "01001011" or data_pkt1 = "11000011") then
+					data_valid_temp 	<= '1';
+					read_byte_valid_c <= read_byte_valid;
+					usb_manage			<= wait_read_byte2;
+					counter1				<= "11111111";
+				else
+					counter1				<= "11111111";
+					usb_manage			<= wait21;
+				end if;
+		  --------------  byte2  -------------------------
+		  when wait_read_byte2 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte2;	  
+					else
+						usb_manage		<= read_byte2;
+					end if;	
+				end if;
+		  ------------------ read_byte2 ---------------------
+		  when read_byte2 =>
+				if joystick_type = '0' then
+					--joyleft_temp ( 1 downto 0) <= NOT ((NOT data_pkt1(6)) & data_pkt1(7)); -- game pad joystick
+					data_byte2  		<= data_pkt1;
+					---
+					if (data_pkt1 = "01111111" OR data_pkt1 = "11111111" OR data_pkt1 = "00000000") then
+						data_valid_temp 			<= '1';
+					else
+						data_valid_temp 			<= '0';
+					end if;
+				else 
+					-- data_valid_temp 			<= '1';
+					if (data_pkt1 = "10000000") then
+						joystick_updown 	<= '1'; -- either up or down
+					elsif (data_pkt1 = "00000000") then
+						joystick_updown 	<= '0'; -- left
+						joyright_temp(1 downto 0) 	<= "10";
+					elsif (data_pkt1 = "11111111") then
+						joystick_updown 	<= '0'; -- left
+						joyright_temp(1 downto 0) 	<= "01";					
+					end if;
+				end if;
+
+				---
+				read_byte_valid_c <= read_byte_valid;
+				counter1 			<= "11111111";
+				usb_manage			<= wait_read_byte3;		
+		  --------------  byte3  -------------------------
+		  when wait_read_byte3 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte3;	  
+					else
+						usb_manage		<= read_byte3;
+					end if;	
+				end if;
+		  ------------------ read_byte3 ---------------------
+		  when read_byte3 =>
+				if joystick_type = '1' then
+					joyright_temp(3 downto 2) 	<= NOT (data_pkt1(0) &  NOT data_pkt1(0));
+				else
+					--- not actif
+					if (data_byte2 = "01111111" AND data_pkt1 = "01111111") then 
+						joyleft_temp(3 downto 0) <= "1111";
+					--- up right
+					elsif (data_byte2 = "11111111" AND data_pkt1 = "00000000") then 
+						joyleft_temp(3 downto 0) <= "0110";		
+					--- up left
+					elsif (data_byte2 = "00000000" AND data_pkt1 = "00000000") then 
+						joyleft_temp(3 downto 0) <= "0101";
+					--- down right
+					elsif (data_byte2 = "11111111" AND data_pkt1 = "11111111") then 
+						joyleft_temp(3 downto 0) <= "1010";
+					--- down left
+					elsif (data_byte2 = "00000000" AND data_pkt1 = "11111111") then 
+						joyleft_temp(3 downto 0) <= "1001";		
+					--- up
+					elsif (data_byte2 = "01111111" AND data_pkt1 = "00000000") then 
+						joyleft_temp(3 downto 0) <= "0111";
+					--- down
+					elsif (data_byte2 = "01111111" AND data_pkt1 = "11111111") then
+						joyleft_temp(3 downto 0) <= "1011";
+					--- right
+					elsif (data_byte2 = "11111111" AND data_pkt1 = "01111111") then
+						joyleft_temp(3 downto 0) <= "1110";
+					--- left
+					elsif (data_byte2 = "00000000" AND data_pkt1 = "01111111") then
+						joyleft_temp(3 downto 0) <= "1101";
+					else
+						-- mouse detected, 
+						mousex_temp 				 <= data_byte2;
+						mousey_temp 				 <= data_pkt1;
+						joyleft_temp(3 downto 0) <= "1111";
+						mouse_valid					 <= '1';
+					end if;		
+				end if;
+				read_byte_valid_c <= read_byte_valid;
+				counter1 			<= "11111111";
+				usb_manage			<= wait_read_byte4;		
+		  --------------  byte4  -------------------------
+		  when wait_read_byte4 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte4;	  
+					else
+						usb_manage		<= read_byte4;
+					end if;
+				end if;
+		  ------------------ read_byte4 ---------------------
+		  when read_byte4 =>
+				mouse_valid				<= '0';
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte5;		
+		  --------------  byte5  -------------------------
+		  when wait_read_byte5 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte5;	  
+					else
+						usb_manage		<= read_byte5;
+					end if;	
+				end if;
+		  ------------------ read_byte11 ---------------------
+		  when read_byte5 =>
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte6;		
+		  --------------  byte6  -------------------------
+		  when wait_read_byte6 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte6;	  
+					else
+						usb_manage		<= read_byte6;
+					end if;		
+				end if;
+		  ------------------ read_byte6 ---------------------	
+		  when read_byte6 =>
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte7; -- joystick type = gamepad
+		  --------------  byte7  -------------------------
+		  when wait_read_byte7 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte7;	  
+					else
+						usb_manage		<= read_byte7;
+					end if;	
+				end if;
+		  ------------------ read_byte7 ---------------------
+		  when read_byte7 =>
+				if data_pkt1(3 downto 0) = "1111" then  -- checking if data valid
+					joyright_temp(3 downto 0) 	<= NOT (data_pkt1(4) &  data_pkt1(6) & data_pkt1(7) &  data_pkt1(5));
+				else
+					data_valid_temp	<= '0';
+				end if;
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte8;		
+		  --------------  byte8  -------------------------
+		  when wait_read_byte8 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte8;	  
+					else
+						usb_manage		<= read_byte8;
+					end if;
+				end if;
+		  ------------------ read_byte8 ---------------------
+		  when read_byte8 =>
+				joyright_temp(7 downto 4) 	<= NOT (data_pkt1(1) &  data_pkt1(3) & data_pkt1(5) &  data_pkt1(5));
+				joyleft_temp(7 downto 4) 	<= NOT (data_pkt1(0) &  data_pkt1(2) & data_pkt1(4) &  data_pkt1(4)); 
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte9;		
+		  --------------  byte9  -------------------------
+		  when wait_read_byte9 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte9;	  
+					else
+						usb_manage		<= read_byte9;
+					end if;	
+				end if;
+		  ------------------ read_byte9 ---------------------
+		  when read_byte9 =>
+				--- test if analogue ON/OFF
+				if (data_pkt1 = "01000000") then 
+					-- analogue ON 
+					data_valid		<= '0';
+				elsif (data_pkt1 = "00000000" OR data_pkt1 = "11000000") then
+					data_valid		<= data_valid_temp;
+				else
+					data_valid		<= '0';
+				end if;
+				read_byte_valid_c <= read_byte_valid;
+				counter1 			<= "11111111";
+				usb_manage			<= wait_read_byte10;		
+		  --------------  byte10  -------------------------
+		  when wait_read_byte10 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte10;	  
+					else
+						usb_manage		<= read_byte10;
+					end if;	
+				end if;	
+		  ------------------ read_byte10 ---------------------
+		  when read_byte10 =>
+				read_byte_valid_c <= read_byte_valid;
+				counter1 			<= "11111111";
+				usb_manage			<= wait_read_byte11;		
+		  --------------  byte11  -------------------------
+		  when wait_read_byte11 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte11;	  
+					else
+						usb_manage		<= read_byte11;
+					end if;	
+				end if;
+		  ------------------ read_byte11 ---------------------
+		  when read_byte11 =>
+				counter1				<= "00001111";
+				usb_manage			<= wait40;				
+	
+		  ----------------------------------------------------
+		  ------------  check CRC  ---------------------------
+		  ----------------------------------------------------
+		  ------------- if valid data then issue an ack   ----
+        when wait40 =>
+				counter1					<= counter1 - 1;
+				if counter1	= "00000000" then
+					counter1				<= "11111111";
+					usb_manage			<= send_getreport_ack;		  
+				else
+					usb_manage			<=wait40;
+				end if;	
+		  -------------- read the next bytes to send ----------
+        when send_getreport_ack     =>  
+				counter2				<= "1111";
+				start_sendcom		<= '1';
+				address_start		<= "001000000"; -- 0x40  -   - 2 bytes
+				counter1 				<= "11111111";
+				usb_manage			<= send_getreport_ack_end; 
+		  -------------- wait for completion of sending frame ----------------			 
+		  when send_getreport_ack_end =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom			<= '0';
+						counter1_3ms			<= "100000100011011";
+						counter2					<= "1111";
+						usb_manage				<= crc_complete;  -- 
+					else 
+						usb_manage				<= send_getreport_ack_end;
+					end if;	
+				end if;
+		  ------------------------------  CRC check   -----------------------------
+		  when crc_complete	=>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					data_available		<=	'1';
+					usb_manage			<= wait20;
+				end if;
+		  when others  => 
+			 usb_manage 		<= idle;		 
+	   end case;
+    end if;
+  end process; 
+
+  --------------------------------------------------------------------------
+  ------  detach detection process
+  --------------------------------------------------------------------------
+  process (
+  usb_lock, 
+  CLOCK12MHz,
+  detach_ack,
+  counterdetach,
+  dplus_buf2,
+  dminus_buf2
+  ) is
+  begin
+    if (usb_lock = '0') then  
+		counterdetach		<= "1111";
+		detach 				<= '0';
+		usb_detach			<= idle;
+    elsif (falling_edge(CLOCK12MHz)) then     
+      case usb_detach is
+        -------------- wait for the start trigger ----------------
+			when idle		=>   
+				if dplus_buf2 = '0' AND dminus_buf2 = '0' then	
+					counterdetach		<= "1111";
+					usb_detach			<= detach_start;	
+				else 
+					usb_detach			<= idle;
+				end if; -- 
+				
+		  -------------- read the rom first byte ----------------
+        when detach_start     =>              
+				if dplus_buf2 = '0' AND dminus_buf2 = '0' then
+					if counterdetach = "0000" then
+						usb_detach		<= detach_valid;	
+					else
+						usb_detach		<= detach_start;
+						counterdetach	<= counterdetach - 1;
+					end if;
+				else
+					counterdetach		<= "1111";
+					usb_detach			<= idle;
+				end if;
+		  -------------- wait for 30ms ----------------
+        when detach_valid     =>              
+				detach				<= '1';
+				usb_detach			<= detach_wait;	
+
+		  -------------- wait for 30ms ----------------
+        when detach_wait     =>              
+				if detach_ack	= '1' then
+					detach			<= '0';
+					counterdetach	<= "1111";
+					usb_detach		<= idle;				
+				else
+					usb_detach		<= detach_wait;
+				end if;
+		  when others  => 
+				counterdetach		<= "1111";
+				usb_detach 			<= idle;		 
+	   end case;
+    end if;
+  end process;	  
+  
+  ------------------------------------------------------
+  ------  state machine for the mouse
+  ------------------------------------------------------
+  process (usb_lock, clk_usb, CLOCK12MHz) is
+  begin
+    if (usb_lock = '0') then                                 
+      mouse_counter1			<= "000000000";
+		mousex_ctr				<= "000000000000";
+		mousey_ctr				<= "000000000000";
+		mouse_state				<= idle;
+    elsif (rising_edge(CLOCK12MHz) AND mouse_valid = '1') then     
+      case mouse_state is
+        -------------- xxxxxxxxxxxxxxxxxxxxxxxxxxx ----------------
+			when idle		=>   
+				if (mouse_counter1 = "000000000") then					-- 
+					mouse_state		<= state1;				-- 
+				else 
+					mouse_counter1	<= mouse_counter1 - 1;
+					mouse_state		<= idle;					-- 
+				end if;
+        -------------- xxxxxxxxxxxxxxxxxxxxxxxxxxx ----------------
+			when state1	=>   
+				-- 
+				IF ((mousex_temp /= "10000000")) THEN
+					IF ((mousex_temp(7) = '1') OR (mousex_temp = "01111110")) THEN
+					-- move right
+					mousex_ctr		<= mousex_ctr + ("00000000" & mousex_temp(7 downto 4));
+					ELSE
+					-- move left
+					mousex_ctr		<= mousex_ctr - ("00000000" & NOT(mousex_temp(7 downto 4)));
+					END IF;
+				END IF;
+				IF (mousey_temp /= "10000000") THEN
+					IF ((mousey_temp(7) = '0')) THEN
+						--IF ((mousex_temp /= "01111110") AND (mousex_temp /= "11111110")) THEN
+							-- move up
+							mousey_ctr		<= mousey_ctr + ("00000000" & NOT (mousey_temp(7 downto 4)));
+						--END IF;
+					ELSE
+					-- move down
+					mousey_ctr		<= mousey_ctr - ("00000000" & mousey_temp(7 downto 4));
+					END IF;
+				END IF;
+				mousex_out		<= mousex_ctr;
+				mousey_out		<= mousey_ctr;
+				mouse_counter1	<= "000000111";
+				mouse_state		<= idle;			
+			when others => 
+				mouse_state 	<= idle;		 
+	   end case;
+    end if;
+  end process; 		 
+  
+  
+  
+------------------------------------------------------------
+end arch;
\ No newline at end of file
Index: mcctv/usb/USB_INTF1.vhd
===================================================================
--- mcctv/usb/USB_INTF1.vhd	(nonexistent)
+++ mcctv/usb/USB_INTF1.vhd	(revision 181)
@@ -0,0 +1,70 @@
+--This file contains 2 Entities making up an HID USB interface
+--===========================================================================
+--  USB Interface module - Copywrite Johns Hopkins University ECE Dept.
+--This code may be used and freely distributed as long as the JHU credit is retained.
+--============================================================================
+--Implements an HID USB enumeration and communication through a tranceiver implemented
+--in the FPGA to directly drive the USB diferential pair data lines.
+--On an XESS xst-2 or -3 board this requires a connection of the usb cable wires with a 1.5K 
+--pullup to 3.3V on the D+ or D- line, and the data lines connecting to 2 FPGA pins.
+--The bit rate is determined by which line has the pullup. This code is currently set up
+--for usb full speed (12 Mhz) operation, but can be easily changed for 1.5Mhz low speed.
+
+--The inputs and outputs are arrays(1 to 8) of std_logic_vector(7 downto 0).
+--These arrays are the data packets sent and received via USB reports. The I/O
+--buffers for USB transactions in the tranceiver are also 8 byte arrays.
+
+-- The interface acts as an HID class, thus only control and interrupt xfers are possible.
+-- Any commented page references are to "USB Complete", 3rd Edition, by Jan Axelson
+--
+-- Author: Robert Jenkins
+-- Last Modification: Jan 30, 2009
+--==============================================================================
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use WORK.USBF_Declares.all;             --Package containing declarations needed by the USB interface        
+
+--------------------------------------------------------------------------------
+entity USBF_IFC1 is
+  port(
+    clk_usb     	 	: in    std_logic;      --100MHz project clock
+	 pll_lock			: in std_logic;
+    reset       	: in    std_logic;      -- usually tied to the XST reset button.
+    ----USB CONNECTIONS                 -----------------------------------------
+    dplus       	: inout std_logic;      --differential + line to/from usb hub(pulled up to 3.3)
+    dminus      	: inout std_logic;      --differential minus line to/from usb hub
+    ------------------------------------------------------------
+	 joyright_out 	: out   std_logic_vector(7 downto 0);
+	 joyleft_out 	: out   std_logic_vector(7 downto 0);
+	 mousex_out		: out   std_logic_vector(11 downto 0);
+	 mousey_out		: out   std_logic_vector(11 downto 0)
+    );
+end USBF_IFC1;
+----------------------------------------------------------------------
+
+architecture arch of USBF_IFC1 is
+
+begin
+
+  UDRVR : USB_DRVR1                   
+    port map(
+		clk_usb       	=> clk_usb, 
+		pll_lock			=> pll_lock,
+		reset 			=> reset, 
+		dplus 			=> dplus, 
+		dminus 			=> dminus,
+		joyright_out	=> joyright_out,
+		joyleft_out		=> joyleft_out,
+		mousex_out		=> mousex_out,
+		mousey_out		=> mousey_out
+		);
+
+---=============================
+end arch;  --END of USBF_IFC
+---=============================
+
+
+
+
+
Index: mcctv/usb/rom_com.qip
===================================================================
--- mcctv/usb/rom_com.qip	(nonexistent)
+++ mcctv/usb/rom_com.qip	(revision 181)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "10.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rom_com.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rom_com_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rom_com.cmp"]
Index: mcctv/usb/rom_com1.vhd
===================================================================
--- mcctv/usb/rom_com1.vhd	(nonexistent)
+++ mcctv/usb/rom_com1.vhd	(revision 181)
@@ -0,0 +1,178 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: rom_com1.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY rom_com1 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END rom_com1;
+
+
+ARCHITECTURE SYN OF rom_com1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rden_a	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./usb/rom_com.mif",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=NONE",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 9,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		rden_a => rden,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./usb/rom_com.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./usb/rom_com.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=NONE"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com_inst.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com1.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com1_inst.vhd FALSE
Index: mcctv/usb/usb_driver1.vhd
===================================================================
--- mcctv/usb/usb_driver1.vhd	(nonexistent)
+++ mcctv/usb/usb_driver1.vhd	(revision 181)
@@ -0,0 +1,1576 @@
+
+--===============================================================================
+---USB_DRVR Entity (Drives and Reads D+ and D- lines to send and receive packets)
+--===============================================================================
+-- USB Driver - Copywrite Hakim Haddadi arcade retro gaming.
+--------------------------------------------------
+--==============================================================================
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+use WORK.USBF_Declares.all;
+
+--------------------------------------------------
+entity USB_DRVR1 is
+  port(                                 
+    clk_usb       : in    std_logic;    -- 5MHz clock
+	 pll_lock		: in    std_logic;
+    reset         : in    std_logic;    -- fpga reset
+    dminus        : inout std_logic;    -- USB differential D+ line
+    dplus         : inout std_logic;    -- USB differential D+ line
+	 joyright_out 	: out   std_logic_vector(7 downto 0);
+	 joyleft_out 	: out   std_logic_vector(7 downto 0);
+	 mousex_out		: out   std_logic_vector(11 downto 0);
+	 mousey_out		: out   std_logic_vector(11 downto 0)
+    );
+end USB_DRVR1;
+---------------------------------------------------
+
+architecture arch of USB_DRVR1 is
+------------------------
+
+component sub_pll IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0				: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END component sub_pll;
+
+component rom_com1 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock			: IN STD_LOGIC  := '1';
+		rden			: IN STD_LOGIC  := '1';
+		q				: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component rom_com1;
+ 
+  signal dp_last, dp_prev, dp1_last,dm1_last    : std_logic;
+  signal nb_bits                 : std_logic_vector(3 downto 0);  --bit counter for receive bits
+  signal stuffin1        			: integer range 0 to 7;  --counters for stuff-bits out and in
+  signal usb_lock				 		: std_logic := '0';
+  --signal clk_usb						: std_logic;
+  signal reg_10bits					: std_logic_vector(9 downto 0);
+  signal reg_10bits_receive		: std_logic_vector(9 downto 0);
+  signal dp2_prev						: std_logic;
+  signal CLOCK12MHz					: std_logic;
+  signal CLOCK12MHz_receive		: std_logic;
+  signal token_pid2					: std_logic_vector(3 downto 0);
+  signal data_pkt1					: std_logic_vector(7 downto 0);
+  signal data_temp					: std_logic_vector(7 downto 0);
+  signal data_rom						: std_logic_vector(7 downto 0);
+  -- ROM signals
+  signal address_rom					: std_logic_vector(8 downto 0);
+  signal rom_out						: std_logic_vector(7 downto 0);
+  signal rden_sig						: std_logic;
+  
+  signal data_tosend					: std_logic_vector(7 downto 0);
+  signal nb_byte_tosend				: std_logic_vector(7 downto 0);
+  signal address_start				: std_logic_vector(8 downto 0);
+  signal dm_previous					: std_logic;
+  signal dp_previous					: std_logic;
+  signal dplus_buf1					: std_logic;
+  signal dplus_buf2					: std_logic;
+  signal dminus_buf1					: std_logic;
+  signal dminus_buf2					: std_logic;
+  signal start_sendcom				: std_logic;
+  signal send_frame					: std_logic;
+  signal usb_reset					: std_logic;
+  signal synch							: std_logic;
+  signal read_byte_valid			: std_logic;
+  signal read_byte_valid_c			: std_logic;
+  signal data_available				: std_logic;
+  signal data_valid					: std_logic; 
+  signal data_valid_temp			: std_logic;
+  signal gamepad_basic				: std_logic;  
+  signal detach_ack					: std_logic;
+  signal detach						: std_logic;
+  signal joystick_type						: std_logic;
+  signal joystick_updown						: std_logic;
+  signal set_command						: std_logic_vector(1 downto 0);
+  signal counter1						: std_logic_vector(7 downto 0);
+  signal counterdetach					: std_logic_vector(3 downto 0);
+  signal counter2							: std_logic_vector(3 downto 0); 
+  signal counter30ms						: std_logic_vector(18 downto 0);
+  signal counter1_3ms					: std_logic_vector(14 downto 0);
+  signal joyright_temp					: std_logic_vector(7 downto 0);  
+  signal joyleft_temp					: std_logic_vector(7 downto 0);
+  signal data_byte2						: std_logic_vector(7 downto 0);
+  
+  signal nb_reset							: std_logic_vector(7 downto 0);
+  signal val								: std_logic;
+  signal mouse_valid						: std_logic;	
+  signal mouse_counter1					: std_logic_vector(8 downto 0);  
+  
+  signal mousex_temp						: std_logic_vector(7 downto 0);  
+  signal mousey_temp						: std_logic_vector(7 downto 0);
+  signal mousex_ctr						: std_logic_vector(11 downto 0);  
+  signal mousey_ctr						: std_logic_vector(11 downto 0); 
+ 
+  type usb1_sm_type is (                 -- receive state machine
+    state1, state2, state3,              --,
+    state4);
+	 
+  type usb_com_type is (                 	--send state machine #1 to read D+/D- lines
+    Idle, 
+	 send1, send2,send3, reset_start,             			--
+	 send4, send5,send6, reset_released,            			--
+	 send_bit0, send_bit1,send_bit2,             			--
+	 send_bit3, send_bit4,send_bit5,             		--
+	 send_bit6, send_bit7,send15,             		--
+	 end_send1, end_send2, send_complete             		--
+ );
+
+  type usb_manage_type is (                 	--Tranceiver state machine #1 to read D+/D- lines
+    Idle, 
+	 usb_manage1, usb_manage2,             			-- 
+	 usb_reset_state, crc_complete, usb_waitdetachrelease, wait_for_deviceconnect,
+	 usb_wait30ms, end_set_address, end_set_configuration, end_set_idle,
+	 read_pktin2, read_pktin3, read_pktin4, wait_pktin4,
+	 setaddress_sendpkt1, setaddress_sendpkt1_end,
+	 setaddress_sendpkt2, setaddress_sendpkt2_end,
+	 setaddress_sendpkt3, setaddress_sendpkt3_end,	 
+	 send_ack, send_ack_start, send_ack_end,
+	 getreport_sendpkt1, getreport_sendpkt1_start, getreport_sendpkt1_end,
+	 wait_pktin1, wait_pktin2, wait_pktin3,
+	 wait_report_start, start_get_report,
+	 send_getreport_ack, send_getreport_ack_start, send_getreport_ack_end,
+	 start_get_data, 
+	 wait_read_byte2, wait_read_byte3, wait_read_byte4, wait_read_byte5, wait_read_byte6,
+	 wait_read_byte7, wait_read_byte8, wait_read_byte9, wait_read_byte10, wait_read_byte11,
+	 read_byte1, read_byte2, read_byte3, read_byte4, read_byte5, read_byte6,
+	 read_byte7, read_byte8, read_byte9, read_byte10, read_byte11,
+	 wait1, wait2, wait4, wait6,  
+	 wait20, wait21, wait30, wait40, 
+	 wait_ack2,
+	 usb_reset_1ms_start, usb_reset_1ms_wait1, usb_reset_1ms_wait2, usb_reset_1ms_release
+ ); 
+ 
+ type usb_detach_type is (                 	--Tranceiver state machine #1 to read D+/D- lines
+    Idle, 
+	 detach_start, detach_wait,detach_valid             			--            		--
+ );
+ 
+ type mouse_state_type is (                 	--Tranceiver state machine #1 to read D+/D- lines
+    Idle, 
+	 state1             			--            		--
+ );
+	 
+  signal                                usb_detach             : usb_detach_type;
+  signal                                usb1_state             : usb1_sm_type;
+  signal                                usb_send_com    			: usb_com_type;
+  signal                                usb_manage    			: usb_manage_type;
+  signal                                mouse_state    			: mouse_state_type; 
+  ------------------------------------------------------------
+
+  ATTRIBUTE keep : boolean;
+  ATTRIBUTE keep OF dminus  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF dplus  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF clk_usb  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF CLOCK12MHz  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF rom_out  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF joyright_out  : SIGNAL IS TRUE;  
+  ATTRIBUTE keep OF joyleft_out  : SIGNAL IS TRUE;
+  ATTRIBUTE keep OF joyright_temp  : SIGNAL IS TRUE;  
+  ATTRIBUTE keep OF joyleft_temp  : SIGNAL IS TRUE;
+ 
+begin
+
+----------------------------------
+-- instantiate the rom commands --
+----------------------------------
+rom_com_inst : rom_com1 
+PORT MAP (
+			address	 	=> address_rom,
+			clock	 		=> clk_usb,
+			rden	 		=> rden_sig AND CLOCK12MHz,
+			q	 			=> rom_out
+			);
+		
+   usb_lock <= pll_lock;
+  
+-----------------------------
+-- update of joystick data	--
+-----------------------------
+  PROCESS
+  (
+    usb_lock, 		-- External asynchronous reset
+    clk_usb    	-- 15 MHz clock (usb over sampling)
+
+  )
+  BEGIN
+    -- 
+   IF (usb_lock = '0') THEN
+		joyright_out 			<= "11111111";
+		joyleft_out 			<= "11111111";
+   ELSIF (rising_edge(clk_usb)) THEN
+		IF (data_available = '1') THEN
+			IF (data_valid = '1') THEN
+				-- bit 0 : 2
+				-- bit 1 : 4
+				-- bit 2 : 3
+				-- bit 3 : 1
+				-- bit 4 : fire button / start
+				-- bit 5 : fire button / start
+				-- bit 6 : button front right "2"  
+				-- bit 7 : button front right "1"
+				joyright_out <= joyright_temp;
+				-- bit 0 : right
+				-- bit 1 : left
+				-- bit 2 : down
+				-- bit 3 : up
+				-- bit 4 : fire button / select
+				-- bit 5 : fire button / select
+				-- bit 6 : button front left "2"  
+				-- bit 7 : button front left "1"							
+				joyleft_out <= joyleft_temp;
+			ELSE
+				-- bit 0 : 2
+				-- bit 1 : 4
+				-- bit 2 : 3
+				-- bit 3 : 1
+				-- bit 4 : fire button / start
+				-- bit 5 : fire button / start
+				-- bit 6 : button front right "2"  
+				-- bit 7 : button front right "1"
+				joyright_out <= joyright_temp;
+				-- bit 0 : Not active
+				-- bit 1 : Not active
+				-- bit 2 : Not active
+				-- bit 3 : Not active
+				-- bit 4 : fire button / select
+				-- bit 5 : fire button / select
+				-- bit 6 : button front left "2"  
+				-- bit 7 : button front left "1"							
+				joyleft_out(7 downto 4) <= joyleft_temp(7 downto 4);	
+				joyleft_out(3 downto 0) <= "1111";
+			END IF;
+      END IF;
+   END IF;			
+  END PROCESS;
+	
+ ----------------------------------------------
+ --  usb clock enable generation for sending --
+ ----------------------------------------------
+  PROCESS
+  (
+    usb_lock, -- reset_process, 	-- External asynchronous reset
+    clk_usb    		-- over sampling clk 15MHz
+  )
+  BEGIN
+    -- 
+   IF (usb_lock = '0') THEN
+		reg_10bits <= "0000000001";
+   ELSIF (rising_edge(clk_usb)) THEN
+		reg_10bits 		<= reg_10bits(8 downto 0) & reg_10bits(9); -- 
+   END IF;			
+  END PROCESS;
+  
+ -- update clock enable USB
+ CLOCK12MHz 		<= reg_10bits(4);
+ 
+ ------------------------------------------------
+ --  usb clock enable generation for receiving --
+ ------------------------------------------------
+ -- process generating a 15 MHz clk enable signal in phase with the incoming data from the device
+ -- the process is using an oversampling clk of 15 MHz
+  PROCESS
+  (
+    usb_lock, --reset_process, 		-- External asynchronous reset
+    clk_usb    -- over sampling clk 48MHz
+  )
+  BEGIN
+    -- 
+   IF (usb_lock = '0') THEN
+		reg_10bits_receive 	<= "0000000001";
+		dp2_prev     		 	<= dplus_buf2;
+   ELSIF (rising_edge(clk_usb)) THEN
+		dp2_prev     			<= dplus_buf2;           -- sample the input D+ line
+		IF (dp2_prev /= dplus_buf2) THEN
+			reg_10bits_receive <= "0000000001";				-- reset the phase of the USB clk
+		ELSE
+			reg_10bits_receive 				<= reg_10bits_receive(8 downto 0) & reg_10bits_receive(9); -- 
+      END IF;
+   END IF;			
+  END PROCESS;
+  
+  -- update clock USB
+ CLOCK12MHz_receive 		<= reg_10bits_receive(4); 
+  
+  --------------------------------------------------------------------------------------
+  ---------------------  buffering of Dplus - Dminus to avoid metastability ------------
+  --------------------------------------------------------------------------------------
+  process (clk_usb, usb_lock) is
+  begin
+    if usb_lock = '0' then
+		dplus_buf1      	<= '0';
+		dplus_buf2      	<= '0';
+		dminus_buf1      	<= '0';
+		dminus_buf2      	<= '0';
+    elsif rising_edge(clk_usb) then     	--
+		dplus_buf1     	<= dplus;  
+		dplus_buf2     	<= dplus_buf1;
+		dminus_buf1      	<= dminus;
+		dminus_buf2      	<= dminus_buf1;
+    end if;
+  end process;
+  
+  ---------------------------------------------------------------------
+  ------------------  state machine for acquiring usb data
+  ---------------------------------------------------------------------
+  process (reset, clk_usb, CLOCK12MHz_receive) is
+  begin
+    if (reset = '0') then    
+		dp1_last				<= dplus_buf2;
+		dm1_last				<= dminus_buf2;
+      data_pkt1			<= "00000000";
+      data_temp   		<= "00000000";
+		read_byte_valid	<= '0';
+		usb1_state       	<= state1;   
+		nb_bits				<= "0000";
+		stuffin1          <= 0;
+		synch       		<= '0';
+    elsif (rising_edge(clk_usb) AND CLOCK12MHz_receive = '1') then     
+      case usb1_state is
+        -------------- state1 ----------------
+			when state1		=>   
+				read_byte_valid	<= '1';
+				data_pkt1   <= "00000000";
+				data_temp   <= "00000000";
+				if dplus_buf2 = '0' and dminus_buf2 = '0' then
+					usb1_state	<= state1;				-- reset state
+				elsif dplus_buf2 = '1' and dminus_buf2 = '0' then
+					dp1_last		<= dplus_buf2;
+					dm1_last		<= dminus_buf2;
+					usb1_state	<= state2;				-- go to state2 and wait for synch
+				end if;
+				nb_bits				<= "0000"; 
+		  -------------- state2 ----------------
+        when state2     =>
+				dp1_last		<= dplus_buf2;
+				dm1_last		<= dminus_buf2;
+				if dp1_last /= dplus_buf2 and dm1_last /= dminus_buf2 then               
+					nb_bits     	<= nb_bits + 1;			-- start of synch
+				elsif dplus_buf2 = '0' and dminus_buf2 = '0' then  
+					usb1_state	<= state1;				-- reset state
+					nb_bits		<= "0000";
+				end if;
+  
+          if nb_bits = "0110" then               
+				usb1_state	<= state3;				-- go to state 3 and wait for final synch
+          end if; 
+		  -------------- state3 ----------------
+        when state3     =>
+				dp1_last		<= dplus_buf2;
+				dm1_last		<= dminus_buf2;
+          if dplus_buf2 = '0' and dminus_buf2 = '1' then               
+            nb_bits     <= nb_bits + 1;			-- start of synch
+          elsif dplus_buf2 = '0' and dminus_buf2 = '0' then  
+            usb1_state	<= state1;				-- reset state
+				data_pkt1   <= "00000000";
+				data_temp   <= "00000000";
+				nb_bits		<= "0000";
+          end if;
+
+			 if nb_bits = "0111" then               
+				usb1_state	<= state4;				-- synch byte complete start aquiring packets
+				data_pkt1   <= "10000000";
+				data_temp	<= "10000000";
+				read_byte_valid	<= Not read_byte_valid;
+				nb_bits		<= "0000";
+				synch       <= '1';
+          end if; 
+		  -------------- state4 ----------------
+        when state4     =>
+		if detach = '1' then
+			usb1_state   	<= state1;
+		else
+          if dplus_buf2 = '0' and dminus_buf2 = '0' then  
+            usb1_state	<= state1;				-- reset state
+				data_pkt1   <= data_temp;
+				data_temp   <= "00000000";
+				nb_bits		<= "0000";
+			 else
+				dp1_last        <= dplus_buf2;
+				
+				if (stuffin1 = 6 and nb_bits = "0000") then
+					stuffin1           <= 0;
+					val					 <= '1';	
+				elsif stuffin1 = 6 then           				--	after 6 '1's in a row = This is a stuff bit.
+					stuffin1           <= 0;     				--	ignore it and reset the stuff count.
+					val					 <= '0';
+				else                          				--	no stuff bit, get the real bit based on D+/D- lines. 
+					val					 <= '0';
+					nb_bits         <= nb_bits + 1;  	--	Count the real bits. Current 'bitin' is always coming in.
+					if dp1_last = dplus_buf2 then     				--	NRZI test. no change -> 1
+						stuffin1           <= stuffin1 + 1;  	--	count the consecutive 1's
+						if(nb_bits = "0000") then
+							data_temp(0) <= '1';
+						elsif(nb_bits = "0001") then
+							data_temp(1) <= '1';
+						elsif(nb_bits = "0010") then
+							data_temp(2) <= '1';
+						elsif(nb_bits = "0011") then
+							data_temp(3) <= '1';
+						elsif(nb_bits = "0100") then
+							data_temp(4) <= '1';
+						elsif(nb_bits = "0101") then
+							data_temp(5) <= '1';
+						elsif(nb_bits = "0110") then
+							data_temp(6) <= '1';
+						else
+							data_temp(7) <= '1';
+						end if;
+					else
+						if(nb_bits = "0000") then
+							data_temp(0) <= '0';
+						elsif(nb_bits = "0001") then
+							data_temp(1) <= '0';
+						elsif(nb_bits = "0010") then
+							data_temp(2) <= '0';
+						elsif(nb_bits = "0011") then
+							data_temp(3) <= '0';
+						elsif(nb_bits = "0100") then
+							data_temp(4) <= '0';
+						elsif(nb_bits = "0101") then
+							data_temp(5) <= '0';
+						elsif(nb_bits = "0110") then
+							data_temp(6) <= '0';
+						else
+							data_temp(7) <= '0';
+						end if;
+						stuffin1         	<= 0;     --reset the stuff-bit count when a 0
+					end if;
+				end if;
+			end if;
+			
+			if (nb_bits = "0111") AND (stuffin1 /= 6) then  
+				usb1_state	<= state4;
+				nb_bits		<= "0000"; 
+         end if; 
+			
+			if nb_bits = "0000" AND synch = '1' then  
+				synch       <= '0';
+			elsif nb_bits = "0000" AND val = '1' then
+				data_pkt1   <= data_temp;
+			elsif nb_bits = "0000" then
+				data_pkt1   <= data_temp;			
+				read_byte_valid	<= Not read_byte_valid;
+         end if; 
+		end if;
+		when others  => 
+			 usb1_state <= state1;
+			 nb_bits		<= "0000";
+	   end case;
+    end if;
+  end process; 		 
+  
+  ------------------------------------------------------
+  ------  state machine for sending usb data
+  ------------------------------------------------------
+  process (usb_lock, clk_usb, CLOCK12MHz) is
+  begin
+    if (usb_lock = '0') then                                 
+      data_tosend			<= "00000000";
+		nb_byte_tosend		<= "00000000";
+		dp_previous			<= '1';
+		dm_previous			<= '0';
+		dplus					<= '1';
+		dminus				<= '0';
+		usb_send_com		<= idle;
+    elsif (rising_edge(clk_usb) AND CLOCK12MHz = '1') then     
+      case usb_send_com is
+        -------------- wait for the reset start trigger ----------------
+			when idle		=>   
+				data_tosend   <= "00000000";
+				send_frame		<= '0';
+				if (usb_reset = '1') then				-- the start of sending data is initiated by the usb manage state machine
+					usb_send_com	<= reset_start;	-- reset start state
+					dplus			<= '0';
+					dminus		<= '0';
+				else 
+					usb_send_com	<= idle;					-- go to idle state
+				end if;
+        -------------- wait for the start trigger ----------------
+			when reset_start		=>   
+				if (usb_reset = '0') then					-- The reset is released
+					usb_send_com	<= reset_released;	-- end of reset state
+					dplus				<= 'Z';
+					dminus			<= 'Z';
+				else 
+					usb_send_com	<= reset_start;			
+				end if;				
+        -------------- wait for the start trigger ----------------
+			when reset_released		=>   
+				data_tosend   <= "00000000";
+				send_frame		<= '0';
+				if (usb_reset = '1') then
+					dplus				<= '0';
+					dminus			<= '0';
+					usb_send_com	<= reset_start;
+				elsif (start_sendcom = '1') then				-- the start of sending data is initiated by the usb manage state machine
+					usb_send_com	<= send1;				-- next state
+					rden_sig			<= '1';					
+					address_rom		<= address_start;		-- inialise the address_com with the address set by the usb state machine
+				else 
+					dplus				<= 'Z';
+					dminus			<= 'Z';
+					usb_send_com	<= reset_released;	-- wait for send com trigger
+				end if;
+		  -------------- prepare for the next read ----------------
+        when send1     =>              
+				address_rom			<= address_rom + "000000001";	-- prepare for the next read
+				rden_sig				<= '1';					-- read the first byte
+				usb_send_com		<= send2;		  
+		  -------------- read the rom first byte ----------------
+        when send2     =>  
+				nb_byte_tosend		<= rom_out;				-- read the first byte
+				usb_send_com		<= send3;
+		  -------------- read the next bytes to send ----------------
+        when send3     =>    
+				data_tosend			<= rom_out;				-- read the next byte
+				rden_sig				<= '0';
+				usb_send_com		<= send_bit0;
+		  -------------- send_bit0 ----------------
+        when send_bit0 =>
+		  	 nb_byte_tosend   <= nb_byte_tosend - "00000001";
+			 rden_sig			<= '0';					-- disable the rom read
+          if data_tosend(0) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit1;
+		  -------------- send_bit1 ----------------			 
+		  when send_bit1 =>
+          if data_tosend(1) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+				else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit2;
+		  -------------- send_bit2 ----------------
+        when send_bit2 =>
+          if data_tosend(2) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit3;
+		  -------------- send_bit3 ----------------			 
+		  when send_bit3 =>
+          if data_tosend(3) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit4;
+		  -------------- send_bit4 ----------------
+        when send_bit4 =>
+          if data_tosend(4) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 usb_send_com	<= send_bit5;
+		  -------------- send_bit5 ----------------			 
+		  when send_bit5 =>
+          if data_tosend(5) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 address_rom	<= address_rom + "000000001";	-- prepare for the next read
+			 rden_sig		<= '1';								
+			 usb_send_com	<= send_bit6;
+		  -------------- send_bit6 ----------------
+        when send_bit6 =>
+          if data_tosend(6) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 rden_sig		<= '0';
+			 usb_send_com	<= send_bit7;
+		  -------------- send_bit7 ----------------			 
+		  when send_bit7 =>
+          if data_tosend(7) = '0' then               
+				dplus			<= NOT dp_previous;
+				dminus		<= NOT dm_previous;
+				dp_previous <= NOT dp_previous;
+				dm_previous <= NOT dm_previous;
+          else 
+				dplus			<= dp_previous;
+				dminus		<= dm_previous;
+          end if;
+			 data_tosend 	<= rom_out;
+			 rden_sig		<= '0';								
+			 if nb_byte_tosend = "00000000" then
+				usb_send_com	<= end_send1;
+			 else
+				usb_send_com	<= send_bit0; -- send next byte
+			 end if;
+		  -------------- send_end of frame ----------------			 
+		  when end_send1 =>              
+			 dplus		<= '0';
+			 dminus		<= '0';
+			 usb_send_com	<= end_send2; 
+		  -------------- send_end of frame ----------------			 
+		  when end_send2 =>              
+			 dplus			<= '0';
+			 dminus			<= '0';
+			 usb_send_com	<= send_complete; 
+		  -------------- send_complete ----------------			 
+		  when send_complete =>              
+			 send_frame		<= '1';
+			 dplus			<= 'Z';
+			 dminus			<= 'Z';
+			 dp_previous	<= '1';
+			 dm_previous	<= '0';
+			 usb_send_com	<= reset_released; 	
+		  when others  => 
+			 usb_send_com <= idle;		 
+	   end case;
+    end if;
+  end process; 		 
+  
+  
+  --------------------------------------------------------------------------
+  ------  state machine for managing sending and receiving usb data
+  --------------------------------------------------------------------------
+  process (usb_lock, clk_usb) is
+  begin
+    if (usb_lock = '0') then 
+		joystick_type 		<= '0';
+		usb_reset			<= '0';
+		data_available		<= '0';
+		data_valid			<= '0';
+		data_valid_temp	<= '0';
+      start_sendcom		<= '0';
+		counter1				<= "11111111";
+		counter2				<= "1000";
+		counter30ms			<= "0101100110000100101";
+		counter1_3ms		<= "100000100011011";
+		detach_ack			<= '0';
+		usb_manage			<= idle;
+		
+    elsif (falling_edge(clk_usb)) then     
+      case usb_manage is
+        -------------- idle state ----------------
+			when idle		=>   
+				set_command				<= "00";
+				start_sendcom			<= '0';
+				joystick_type 			<= '0';
+				mouse_valid				<= '0';
+				if dplus = '1' then	
+					usb_manage			<= wait_for_deviceconnect;	
+				else 
+					usb_manage			<= idle;
+				end if; -- 
+		  -------------- confirm device connected ----------------
+        when wait_for_deviceconnect     =>              
+				counter1					<= counter1 - 1;
+				if counter1	= "00000000" then
+					usb_reset			<= '1';
+					usb_manage			<= usb_reset_state;	
+				else
+					usb_manage			<= wait_for_deviceconnect;
+				end if;		
+		  -------------- reset device state ----------------
+        when usb_reset_state     =>              
+				counter30ms				<= counter30ms - 1;
+				if counter30ms	 = "0000000000000000000" then
+				   counter30ms			<= "1111111111111111111";
+					counter1_3ms		<= "100000100011011";
+					counter2				<= "1011";
+					usb_reset			<= '0';
+					detach_ack			<= '1';
+					nb_reset	 			<= "00011101"; -- 29 keep alive
+					usb_manage			<= usb_reset_1ms_start;	
+				else
+					usb_manage			<= usb_reset_state;
+				end if;
+		  -------------- usb_reset_1ms_start ----------------
+        when usb_reset_1ms_start     =>              
+				counter1_3ms				<= counter1_3ms - 1;
+				if counter1_3ms	 = "0000000000000000" then
+					counter1_3ms		<= "100000100011011";
+					counter2				<= "1011";
+					counter1_3ms		<= counter1_3ms - 1;
+					detach_ack			<= '0';
+					usb_reset			<= '1';
+					usb_manage			<= usb_reset_1ms_wait1;	
+				else
+					usb_manage			<= usb_reset_1ms_start;
+				end if;			
+		  -------------- usb_reset_1ms_start ----------------
+        when usb_reset_1ms_wait1     =>  
+				usb_reset				<= '1';
+				counter2					<= counter2 - '1';
+				if counter2 = "0000" then
+					usb_reset			<= '0';
+					usb_manage			<= usb_reset_1ms_release;	
+				else
+					usb_manage			<= usb_reset_1ms_wait1;
+				end if;
+		
+		  -------------- usb_reset_1ms_start ----------------
+        when usb_reset_1ms_release     =>          
+				usb_reset				<= '0';		  
+				nb_reset					<= nb_reset - 1;
+				if nb_reset	 = "00000000" then
+					usb_manage			<= usb_manage2;	
+				else
+					counter1_3ms		<= "100000100011011";
+					counter2				<= "1011";
+					usb_manage			<= usb_reset_1ms_start;
+				end if;				
+	
+		  -------------- reset release state ----------------
+        when usb_wait30ms     =>              
+				counter1			<= counter1 - 1;
+				if counter1	= "00000000" then
+					detach_ack		<= '0';
+					counter1			<= "11111111";
+					usb_manage			<= usb_waitdetachrelease;	
+				else
+					usb_manage			<= usb_wait30ms;
+				end if;	
+		  -------------- confirm device attached ----------------
+        when usb_waitdetachrelease     =>              
+				counter2				<= counter2 - 1;
+				if counter2	= "0000" then
+					usb_manage			<= usb_manage2;	
+				else
+					usb_manage			<= usb_waitdetachrelease;
+				end if;
+		  -------------- end of reset state ----------------
+        when usb_manage2     =>  
+				if detach = '1' then
+					usb_manage   		<= idle;
+				else
+					start_sendcom	<= '0';
+					address_start	<= "000010010";
+					usb_manage		<= wait1;	-- start set address	
+				end if;	
+		  ------------------------------------------------
+		  -------------- SET ADDRESS 0x01 ----------------
+		  ------------------------------------------------
+		  
+		  -------------- waiting state -------------------
+        when wait1 =>
+				counter2					<= counter2 - 1;
+				if counter2	= "0000" then
+					counter2				<= "1111";
+					usb_manage			<= setaddress_sendpkt1;		  
+				else
+					usb_manage			<= wait1;
+				end if;			 
+		  -------------- send first packet "SETUP" packet ----------------
+        when setaddress_sendpkt1     =>  
+				start_sendcom			<= '1';
+				if set_command = "00" then
+					-- set address
+					address_start		<= "000010010"; -- 0x12  - 0x2D 0x00 0x10  - 3 bytes
+				elsif set_command = "01" then
+					-- set configuration
+					address_start		<= "001010000"; -- 0x50  - 0x2D 0x01 0xE8  - 3 bytes
+				else
+					-- set idle
+					address_start		<= "001110000"; -- 0x70  - 0x2D 0x01 0xE8  - 3 bytes
+				end if;
+				usb_manage				<= setaddress_sendpkt1_end; -- 
+		  -------------- wait for completion of sending frame ----------------			 
+		  when setaddress_sendpkt1_end =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom	<= '0';
+						counter1			<= "01010011";
+						usb_manage		<= wait2;
+					else 
+						usb_manage		<= setaddress_sendpkt1_end;
+					end if;
+				end if;
+			---------------------  waiting state ----------------------
+			when wait2 =>
+				counter1					<= counter1 - 1;
+				if counter1	= "00000000" then
+					counter1				<= "01010011";
+					usb_manage			<= setaddress_sendpkt2;		  
+				else
+					usb_manage			<= wait2;
+				end if;			 
+		  -------------- send the data packet for set address ---------
+        when setaddress_sendpkt2     =>  
+				start_sendcom		<= '1';
+				if set_command = "00" then
+					-- set address
+					address_start		<= "000010111"; -- 0x17  -   - 11 bytes
+				elsif set_command = "01" then
+					-- set configuration
+					address_start		<= "001010101"; -- 0x55  -   - 11 bytes
+				else
+					-- set idle
+					address_start		<= "001110101"; -- 0x75  -   - 11 bytes
+				end if;
+				usb_manage			<= setaddress_sendpkt2_end; -- 	
+		  -------------- wait for completion of sending frame ----------------			 
+		  when setaddress_sendpkt2_end =>
+			 if detach = '1' then
+					usb_manage   	<= idle;
+			 else
+				if send_frame = '1' then  
+					start_sendcom			<= '0';
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= wait_ack2;
+				else 
+					usb_manage				<= setaddress_sendpkt2_end;
+				end if;
+			end if;
+		  -------------- waiting ACK ----------------
+        when wait_ack2 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					counter1_3ms			<= counter1_3ms - 1;
+					if data_pkt1 = "11010010" then
+						counter1_3ms		<= "100000100011011";
+						usb_manage			<= wait4;		-- ack go top the next stage
+					elsif counter1_3ms	= "000000000000000" then
+						counter1_3ms		<= "100000100011011"; -- no ack, retry sending the command
+						usb_manage			<= setaddress_sendpkt1;
+					else
+						usb_manage			<= wait_ack2;
+					end if;
+				end if;
+		  ---------------- waiting state  ---------------------
+		  when wait4 =>
+				counter2			<= counter2 - 1;
+				if counter2	= "0000" then
+					counter2		<= "1111";
+					usb_manage			<= setaddress_sendpkt3;		  
+				else
+					usb_manage					<= wait4;
+				end if;			 
+		  -------------- prepare for sending the second packet ----------------
+        when setaddress_sendpkt3     =>  
+				start_sendcom		<= '1';
+				if set_command = "00" then
+					-- set address
+					address_start		<= "000100100"; -- 0x24  -   - 4 bytes
+				elsif set_command = "01" then
+					-- set configuration
+					address_start		<= "001100010"; -- 0x62  -   - 4 bytes
+				else
+					-- set idle
+					address_start		<= "010000010"; -- 0x82  -   - 4 bytes
+				end if;
+				usb_manage			<= setaddress_sendpkt3_end; -- 
+		  -------------- wait for completion of sending frame ----------------			 
+		  when setaddress_sendpkt3_end =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom			<= '0';
+						counter1_3ms			<= "100000100011011";
+						usb_manage				<= wait_pktin1;
+					else 
+						usb_manage				<= setaddress_sendpkt3_end;
+					end if;
+				end if;
+		  -------------- waiting for 1st byte ----------------
+        when wait_pktin1 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					counter1_3ms			<= counter1_3ms - 1;
+					if data_pkt1 = "10000000" then -- 0x80 wait for synch
+						usb_manage			<= wait_pktin2;		-- ack go to the next stage
+					elsif counter1_3ms	= "000000000000000" then
+						counter1_3ms		<= "100000100011011";    -- no ack, retry sending the command
+						usb_manage			<= setaddress_sendpkt3;
+					else
+						usb_manage			<= wait_pktin1;
+					end if;
+				end if;
+		  --------------  pktin2 "0x4B"  -------------------------
+		  when wait_pktin2 =>
+				if detach = '1' then
+					usb_manage   		<= idle;
+				else
+					if read_byte_valid = '0' then
+						usb_manage		<= wait_pktin2;	  
+					else
+						usb_manage		<= read_pktin2;
+					end if;	
+				end if;
+		  ------------------ read_pktin2 "0x4B" ---------------------
+		  when read_pktin2 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if data_pkt1 = "01001011" then -- 0x4B
+						usb_manage			<= wait_pktin3;					-- ack go top the next stage
+					else 
+						usb_manage			<= setaddress_sendpkt3; -- no ack, retry sending the command
+					end if;
+				end if;	
+		  --------------  pktin3 "0x00"  -------------------------
+		  when wait_pktin3 =>
+				if detach = '1' then
+					usb_manage   		<= idle;
+				else
+					if read_byte_valid = '1'  then
+						usb_manage		<= wait_pktin3;	  
+					else
+						usb_manage		<= read_pktin3;
+					end if;	
+				end if;
+		  ------------------ read_pktin3 "0x00" ---------------------
+		  when read_pktin3 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if data_pkt1 = "00000000" then -- 0x00
+						usb_manage			<= wait_pktin4;					-- ack go top the next stage
+					else 
+						usb_manage			<= setaddress_sendpkt3; -- no ack, retry sending the command
+					end if;
+				end if;	
+		  --------------  pktin4 "0x00"  -------------------------
+		  when wait_pktin4 =>
+				if detach = '1' then
+					usb_manage   		<= idle;
+				else
+					if read_byte_valid = '0' then
+						usb_manage		<= wait_pktin4;	  
+					else
+						usb_manage		<= read_pktin4;
+					end if;	
+				end if;
+		  ------------------ read_pktin4 "0x00" ---------------------
+		  when read_pktin4 =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if data_pkt1 = "00000000" then -- 0x00
+						counter1				<= "00001111"; 
+						usb_manage			<= wait6;					-- go to "send ack" state
+					else 
+						usb_manage			<= setaddress_sendpkt3; -- no ack, retry sending the command
+					end if;
+				end if;	
+		  --------------------   waiting state before sending ack  --------------------------
+        when wait6 =>
+				counter1					<= counter1 - 1;
+				if counter1	= "00000000" then
+					counter1				<= "11111111";
+					usb_manage			<= send_ack;		  
+				else
+					usb_manage			<= wait6;
+				end if;	
+		  -------------- inialise ROM address for send ack ----------------
+        when send_ack     =>  
+				start_sendcom		<= '1';
+				address_start		<= "001000000"; -- 0x40  -   - 2 bytes
+				usb_manage			<= send_ack_end; -- send_ack_start;	-- 	
+		  -------------- wait for completion of sending frame ----------------			 
+		  when send_ack_end =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom			<= '0';
+						counter1_3ms			<= "000000000000001";
+						if set_command = "00" then
+							usb_manage				<= end_set_address;
+						elsif set_command = "01" then
+							usb_manage				<= end_set_configuration;
+						else
+							usb_manage				<= end_set_idle;
+						end if;
+					else 
+						usb_manage				<= send_ack_end;
+					end if;	
+				end if;
+		  ------------------------------  End of Set Address   -----------------------------
+		  
+        when end_set_address =>
+				counter1_3ms					<= counter1_3ms - 1;
+				if counter1_3ms	= "000000000000000" then
+					counter1_3ms				<= "100000100011011";
+					set_command					<= "01"; -- set_command set to SetConfiguration
+					nb_reset	 					<= "00000000"; -- 1 keep alive
+					usb_manage					<= usb_reset_1ms_start;		  
+				else
+					usb_manage					<= end_set_address;
+				end if; 
+				
+        when end_set_configuration =>
+				counter1_3ms					<= counter1_3ms - 1;
+				if counter1_3ms	= "000000000000000" then
+					counter1_3ms				<= "100000100011011";
+					set_command					<= "10"; -- set_command set to SetConfiguration
+					nb_reset	 					<= "00000000"; -- 1 keep alive
+					usb_manage					<= usb_reset_1ms_start;		  
+				else
+					usb_manage					<= end_set_configuration;
+				end if; 
+
+		  when end_set_idle =>
+				counter1_3ms					<= counter1_3ms - 1;
+				if counter1_3ms	= "000000000000000" then
+					counter1_3ms				<= "100000100011011";
+					counter1						<= "00011001";
+					set_command					<= "00"; -- set_command set to Setaddress in case of a detach/attach
+					usb_manage					<= wait21; -- wait20; -- go to get report	  
+				else
+					usb_manage					<= end_set_idle;
+				end if; 
+
+
+			---------------------------------------------------------------
+			---------------------------------------------------------------
+			---------------------------------------------------------------
+			-------------- GET REPORT ----------------
+        when wait20 =>    -- wait 1.3ms * 9
+				counter1_3ms				<= counter1_3ms - 1;
+				if counter1_3ms	= "000000000000000" then
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= wait21;		  
+				else
+					usb_manage				<= wait20;
+				end if;		
+		  ---------------------   wait  -------------
+        when wait21 =>    -- 
+				counter1						<= counter1 - 1;
+				if counter1	= "00000000" then
+					data_available			<=	'0';
+					data_valid				<= '0';
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= getreport_sendpkt1;		  
+				else
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= wait21;
+				end if;		
+		  -------------- read the next bytes to send ----------------
+        when getreport_sendpkt1     =>  
+				start_sendcom		<= '1';
+				address_start		<= "010010000"; -- 0x90  - 0x69 0x81 0x58  - 3 bytes
+				usb_manage			<= getreport_sendpkt1_end; 
+		  -------------- wait for completion of sending frame ----------------			 
+		  when getreport_sendpkt1_end =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom		<= '0';
+						counter1				<= "00000111";
+						usb_manage			<= wait30;
+					else 
+						usb_manage			<= getreport_sendpkt1_end;
+					end if;
+				end if;
+			-------------   waiting state  ------------------------
+		   when wait30 =>
+				counter1						<= counter1 - 1;
+				if counter1	= "00000000" then
+					counter1					<= "11111111";
+					counter1_3ms			<= "100000100011011";
+					usb_manage				<= wait_report_start;		  
+				else
+					usb_manage				<= wait30;
+				end if;			 
+		  -------------- waiting ACK ----------------
+        when wait_report_start =>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					counter1_3ms			<= counter1_3ms - 1;
+					if data_pkt1 = "10000000" then  -- wait for synch
+						counter1_3ms		<= "100000100011011";
+						counter1				<= "01111000";
+						read_byte_valid_c <= read_byte_valid;
+						usb_manage			<= start_get_data;	-- ack go top the next stage
+					elsif counter1_3ms	= "000000000000000" then
+						counter1_3ms		<= "100000100011011"; 	-- no ack, retry sending the command
+						usb_manage			<= getreport_sendpkt1;
+					else
+						usb_manage			<= wait_report_start;
+					end if;
+				end if;
+		  --------------  byte1  -------------------------
+		  when start_get_data =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c then
+						usb_manage			<= start_get_data;	  
+					else
+						read_byte_valid_c <= read_byte_valid;
+						usb_manage			<= read_byte1;
+					end if;	
+				end if;
+		  ------------------ read_byte1 ---------------------
+		  when read_byte1 =>
+				if (data_pkt1 = "01001011" or data_pkt1 = "11000011") then
+					data_valid_temp 	<= '1';
+					read_byte_valid_c <= read_byte_valid;
+					usb_manage			<= wait_read_byte2;
+					counter1				<= "11111111";
+				else
+					counter1				<= "11111111";
+					usb_manage			<= wait21;
+				end if;
+		  --------------  byte2  -------------------------
+		  when wait_read_byte2 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte2;	  
+					else
+						usb_manage		<= read_byte2;
+					end if;	
+				end if;
+		  ------------------ read_byte2 ---------------------
+		  when read_byte2 =>
+				if joystick_type = '0' then
+					--joyleft_temp ( 1 downto 0) <= NOT ((NOT data_pkt1(6)) & data_pkt1(7)); -- game pad joystick
+					data_byte2  		<= data_pkt1;
+					---
+					if (data_pkt1 = "01111111" OR data_pkt1 = "11111111" OR data_pkt1 = "00000000") then
+						data_valid_temp 			<= '1';
+					else
+						data_valid_temp 			<= '0';
+					end if;
+				else 
+					-- data_valid_temp 			<= '1';
+					if (data_pkt1 = "10000000") then
+						joystick_updown 	<= '1'; -- either up or down
+					elsif (data_pkt1 = "00000000") then
+						joystick_updown 	<= '0'; -- left
+						joyright_temp(1 downto 0) 	<= "10";
+					elsif (data_pkt1 = "11111111") then
+						joystick_updown 	<= '0'; -- left
+						joyright_temp(1 downto 0) 	<= "01";					
+					end if;
+				end if;
+
+				---
+				read_byte_valid_c <= read_byte_valid;
+				counter1 			<= "11111111";
+				usb_manage			<= wait_read_byte3;		
+		  --------------  byte3  -------------------------
+		  when wait_read_byte3 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte3;	  
+					else
+						usb_manage		<= read_byte3;
+					end if;	
+				end if;
+		  ------------------ read_byte3 ---------------------
+		  when read_byte3 =>
+				if joystick_type = '1' then
+					joyright_temp(3 downto 2) 	<= NOT (data_pkt1(0) &  NOT data_pkt1(0));
+				else
+					--- not actif
+					if (data_byte2 = "01111111" AND data_pkt1 = "01111111") then 
+						joyleft_temp(3 downto 0) <= "1111";
+					--- up right
+					elsif (data_byte2 = "11111111" AND data_pkt1 = "00000000") then 
+						joyleft_temp(3 downto 0) <= "0110";		
+					--- up left
+					elsif (data_byte2 = "00000000" AND data_pkt1 = "00000000") then 
+						joyleft_temp(3 downto 0) <= "0101";
+					--- down right
+					elsif (data_byte2 = "11111111" AND data_pkt1 = "11111111") then 
+						joyleft_temp(3 downto 0) <= "1010";
+					--- down left
+					elsif (data_byte2 = "00000000" AND data_pkt1 = "11111111") then 
+						joyleft_temp(3 downto 0) <= "1001";		
+					--- up
+					elsif (data_byte2 = "01111111" AND data_pkt1 = "00000000") then 
+						joyleft_temp(3 downto 0) <= "0111";
+					--- down
+					elsif (data_byte2 = "01111111" AND data_pkt1 = "11111111") then
+						joyleft_temp(3 downto 0) <= "1011";
+					--- right
+					elsif (data_byte2 = "11111111" AND data_pkt1 = "01111111") then
+						joyleft_temp(3 downto 0) <= "1110";
+					--- left
+					elsif (data_byte2 = "00000000" AND data_pkt1 = "01111111") then
+						joyleft_temp(3 downto 0) <= "1101";
+					else
+						-- mouse detected, 
+						mousex_temp 				 <= data_byte2;
+						mousey_temp 				 <= data_pkt1;
+						joyleft_temp(3 downto 0) <= "1111";
+						mouse_valid					 <= '1';
+					end if;		
+				end if;
+				read_byte_valid_c <= read_byte_valid;
+				counter1 			<= "11111111";
+				usb_manage			<= wait_read_byte4;		
+		  --------------  byte4  -------------------------
+		  when wait_read_byte4 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte4;	  
+					else
+						usb_manage		<= read_byte4;
+					end if;
+				end if;
+		  ------------------ read_byte4 ---------------------
+		  when read_byte4 =>
+				mouse_valid				<= '0';
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte5;		
+		  --------------  byte5  -------------------------
+		  when wait_read_byte5 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte5;	  
+					else
+						usb_manage		<= read_byte5;
+					end if;	
+				end if;
+		  ------------------ read_byte11 ---------------------
+		  when read_byte5 =>
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte6;		
+		  --------------  byte6  -------------------------
+		  when wait_read_byte6 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte6;	  
+					else
+						usb_manage		<= read_byte6;
+					end if;		
+				end if;
+		  ------------------ read_byte6 ---------------------	
+		  when read_byte6 =>
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte7; -- joystick type = gamepad
+		  --------------  byte7  -------------------------
+		  when wait_read_byte7 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte7;	  
+					else
+						usb_manage		<= read_byte7;
+					end if;	
+				end if;
+		  ------------------ read_byte7 ---------------------
+		  when read_byte7 =>
+				if data_pkt1(3 downto 0) = "1111" then  -- checking if data valid
+					joyright_temp(3 downto 0) 	<= NOT (data_pkt1(4) &  data_pkt1(6) & data_pkt1(7) &  data_pkt1(5));
+				else
+					data_valid_temp	<= '0';
+				end if;
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte8;		
+		  --------------  byte8  -------------------------
+		  when wait_read_byte8 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte8;	  
+					else
+						usb_manage		<= read_byte8;
+					end if;
+				end if;
+		  ------------------ read_byte8 ---------------------
+		  when read_byte8 =>
+				joyright_temp(7 downto 4) 	<= NOT (data_pkt1(1) &  data_pkt1(3) & data_pkt1(5) &  data_pkt1(5));
+				joyleft_temp(7 downto 4) 	<= NOT (data_pkt1(0) &  data_pkt1(2) & data_pkt1(4) &  data_pkt1(4)); 
+				read_byte_valid_c 	<= read_byte_valid;
+				counter1 				<= "11111111";
+				usb_manage				<= wait_read_byte9;		
+		  --------------  byte9  -------------------------
+		  when wait_read_byte9 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte9;	  
+					else
+						usb_manage		<= read_byte9;
+					end if;	
+				end if;
+		  ------------------ read_byte9 ---------------------
+		  when read_byte9 =>
+				--- test if analogue ON/OFF
+				if (data_pkt1 = "01000000") then 
+					-- analogue ON 
+					data_valid		<= '0';
+				elsif (data_pkt1 = "00000000" OR data_pkt1 = "11000000") then
+					data_valid		<= data_valid_temp;
+				else
+					data_valid		<= '0';
+				end if;
+				read_byte_valid_c <= read_byte_valid;
+				counter1 			<= "11111111";
+				usb_manage			<= wait_read_byte10;		
+		  --------------  byte10  -------------------------
+		  when wait_read_byte10 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte10;	  
+					else
+						usb_manage		<= read_byte10;
+					end if;	
+				end if;	
+		  ------------------ read_byte10 ---------------------
+		  when read_byte10 =>
+				read_byte_valid_c <= read_byte_valid;
+				counter1 			<= "11111111";
+				usb_manage			<= wait_read_byte11;		
+		  --------------  byte11  -------------------------
+		  when wait_read_byte11 =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if read_byte_valid = read_byte_valid_c  then
+						usb_manage		<= wait_read_byte11;	  
+					else
+						usb_manage		<= read_byte11;
+					end if;	
+				end if;
+		  ------------------ read_byte11 ---------------------
+		  when read_byte11 =>
+				counter1				<= "00001111";
+				usb_manage			<= wait40;				
+	
+		  ----------------------------------------------------
+		  ------------  check CRC  ---------------------------
+		  ----------------------------------------------------
+		  ------------- if valid data then issue an ack   ----
+        when wait40 =>
+				counter1					<= counter1 - 1;
+				if counter1	= "00000000" then
+					counter1				<= "11111111";
+					usb_manage			<= send_getreport_ack;		  
+				else
+					usb_manage			<=wait40;
+				end if;	
+		  -------------- read the next bytes to send ----------
+        when send_getreport_ack     =>  
+				counter2				<= "1111";
+				start_sendcom		<= '1';
+				address_start		<= "001000000"; -- 0x40  -   - 2 bytes
+				counter1 				<= "11111111";
+				usb_manage			<= send_getreport_ack_end; 
+		  -------------- wait for completion of sending frame ----------------			 
+		  when send_getreport_ack_end =>
+				counter1				<= counter1 - 1;
+				if detach = '1' OR counter1 = "00000000" then
+					usb_manage   	<= idle;
+				else
+					if send_frame = '1' then  
+						start_sendcom			<= '0';
+						counter1_3ms			<= "100000100011011";
+						counter2					<= "1111";
+						usb_manage				<= crc_complete;  -- 
+					else 
+						usb_manage				<= send_getreport_ack_end;
+					end if;	
+				end if;
+		  ------------------------------  CRC check   -----------------------------
+		  when crc_complete	=>
+				if detach = '1' then
+					usb_manage   	<= idle;
+				else
+					data_available		<=	'1';
+					usb_manage			<= wait20;
+				end if;
+		  when others  => 
+			 usb_manage 		<= idle;		 
+	   end case;
+    end if;
+  end process; 
+
+  --------------------------------------------------------------------------
+  ------  detach detection process
+  --------------------------------------------------------------------------
+  process (
+  usb_lock, 
+  CLOCK12MHz,
+  detach_ack,
+  counterdetach,
+  dplus_buf2,
+  dminus_buf2
+  ) is
+  begin
+    if (usb_lock = '0') then  
+		counterdetach		<= "1111";
+		detach 				<= '0';
+		usb_detach			<= idle;
+    elsif (falling_edge(CLOCK12MHz)) then     
+      case usb_detach is
+        -------------- wait for the start trigger ----------------
+			when idle		=>   
+				if dplus_buf2 = '0' AND dminus_buf2 = '0' then	
+					counterdetach		<= "1111";
+					usb_detach			<= detach_start;	
+				else 
+					usb_detach			<= idle;
+				end if; -- 
+				
+		  -------------- read the rom first byte ----------------
+        when detach_start     =>              
+				if dplus_buf2 = '0' AND dminus_buf2 = '0' then
+					if counterdetach = "0000" then
+						usb_detach		<= detach_valid;	
+					else
+						usb_detach		<= detach_start;
+						counterdetach	<= counterdetach - 1;
+					end if;
+				else
+					counterdetach		<= "1111";
+					usb_detach			<= idle;
+				end if;
+		  -------------- wait for 30ms ----------------
+        when detach_valid     =>              
+				detach				<= '1';
+				usb_detach			<= detach_wait;	
+
+		  -------------- wait for 30ms ----------------
+        when detach_wait     =>              
+				if detach_ack	= '1' then
+					detach			<= '0';
+					counterdetach	<= "1111";
+					usb_detach		<= idle;				
+				else
+					usb_detach		<= detach_wait;
+				end if;
+		  when others  => 
+				counterdetach		<= "1111";
+				usb_detach 			<= idle;		 
+	   end case;
+    end if;
+  end process;	  
+  
+  ------------------------------------------------------
+  ------  state machine for the mouse
+  ------------------------------------------------------
+  process (usb_lock, clk_usb, CLOCK12MHz) is
+  begin
+    if (usb_lock = '0') then                                 
+      mouse_counter1			<= "000000000";
+		mousex_ctr				<= "000000000000";
+		mousey_ctr				<= "000000000000";
+		mouse_state				<= idle;
+    elsif (rising_edge(CLOCK12MHz) AND mouse_valid = '1') then     
+      case mouse_state is
+        -------------- xxxxxxxxxxxxxxxxxxxxxxxxxxx ----------------
+			when idle		=>   
+				if (mouse_counter1 = "000000000") then					-- 
+					mouse_state		<= state1;				-- 
+				else 
+					mouse_counter1	<= mouse_counter1 - 1;
+					mouse_state		<= idle;					-- 
+				end if;
+        -------------- xxxxxxxxxxxxxxxxxxxxxxxxxxx ----------------
+			when state1	=>   
+				-- 
+				IF ((mousex_temp /= "10000000")) THEN
+					IF ((mousex_temp(7) = '1') OR (mousex_temp = "01111110")) THEN
+					-- move right
+					mousex_ctr		<= mousex_ctr + ("00000000" & mousex_temp(7 downto 4));
+					ELSE
+					-- move left
+					mousex_ctr		<= mousex_ctr - ("00000000" & NOT(mousex_temp(7 downto 4)));
+					END IF;
+				END IF;
+				IF (mousey_temp /= "10000000") THEN
+					IF ((mousey_temp(7) = '0')) THEN
+						--IF ((mousex_temp /= "01111110") AND (mousex_temp /= "11111110")) THEN
+							-- move up
+							mousey_ctr		<= mousey_ctr + ("00000000" & NOT (mousey_temp(7 downto 4)));
+						--END IF;
+					ELSE
+					-- move down
+					mousey_ctr		<= mousey_ctr - ("00000000" & mousey_temp(7 downto 4));
+					END IF;
+				END IF;
+				mousex_out		<= mousex_ctr;
+				mousey_out		<= mousey_ctr;
+				mouse_counter1	<= "000000111";
+				mouse_state		<= idle;			
+			when others => 
+				mouse_state 	<= idle;		 
+	   end case;
+    end if;
+  end process; 		 
+  
+  
+  
+------------------------------------------------------------
+end arch;
\ No newline at end of file
Index: mcctv/usb/PCK_CRC16_D8.vhd
===================================================================
--- mcctv/usb/PCK_CRC16_D8.vhd	(nonexistent)
+++ mcctv/usb/PCK_CRC16_D8.vhd	(revision 181)
@@ -0,0 +1,70 @@
+--------------------------------------------------------------------------------
+-- Copyright (C) 1999-2008 Easics NV.
+-- This source file may be used and distributed without restriction
+-- provided that this copyright statement is not removed from the file
+-- and that any derivative work contains the original copyright notice
+-- and the associated disclaimer.
+--
+-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+--
+-- Purpose : synthesizable CRC function
+--   * polynomial: (0 2 15 16)
+--   * data width: 8
+--
+-- Info : tools@easics.be
+--        http://www.easics.com
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+package PCK_CRC16_D8 is
+  -- polynomial: (0 2 15 16)
+  -- data width: 8
+  -- convention: the first serial bit is D[7]
+  function nextCRC16_D8
+    (Data: std_logic_vector(7 downto 0);
+     crc:  std_logic_vector(15 downto 0))
+    return std_logic_vector;
+end PCK_CRC16_D8;
+
+
+package body PCK_CRC16_D8 is
+
+  -- polynomial: (0 2 15 16)
+  -- data width: 8
+  -- convention: the first serial bit is D[7]
+  function nextCRC16_D8
+    (Data: std_logic_vector(7 downto 0);
+     crc:  std_logic_vector(15 downto 0))
+    return std_logic_vector is
+
+    variable d:      std_logic_vector(7 downto 0);
+    variable c:      std_logic_vector(15 downto 0);
+    variable newcrc: std_logic_vector(15 downto 0);
+
+  begin
+    d := Data;
+    c := crc;
+
+    newcrc(0) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0) xor c(8) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
+    newcrc(1) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
+    newcrc(2) := d(1) xor d(0) xor c(8) xor c(9);
+    newcrc(3) := d(2) xor d(1) xor c(9) xor c(10);
+    newcrc(4) := d(3) xor d(2) xor c(10) xor c(11);
+    newcrc(5) := d(4) xor d(3) xor c(11) xor c(12);
+    newcrc(6) := d(5) xor d(4) xor c(12) xor c(13);
+    newcrc(7) := d(6) xor d(5) xor c(13) xor c(14);
+    newcrc(8) := d(7) xor d(6) xor c(0) xor c(14) xor c(15);
+    newcrc(9) := d(7) xor c(1) xor c(15);
+    newcrc(10) := c(2);
+    newcrc(11) := c(3);
+    newcrc(12) := c(4);
+    newcrc(13) := c(5);
+    newcrc(14) := c(6);
+    newcrc(15) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0) xor c(7) xor c(8) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
+    return newcrc;
+  end nextCRC16_D8;
+
+end PCK_CRC16_D8;
Index: mcctv/usb/rom_com.cmp
===================================================================
--- mcctv/usb/rom_com.cmp	(nonexistent)
+++ mcctv/usb/rom_com.cmp	(revision 181)
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component rom_com
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: mcctv/usb/rom_com1.cmp
===================================================================
--- mcctv/usb/rom_com1.cmp	(nonexistent)
+++ mcctv/usb/rom_com1.cmp	(revision 181)
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component rom_com1
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: mcctv/usb/rom_com2.qip
===================================================================
--- mcctv/usb/rom_com2.qip	(nonexistent)
+++ mcctv/usb/rom_com2.qip	(revision 181)
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "10.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rom_com2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rom_com2.cmp"]
Index: mcctv/zpu.wcfg
===================================================================
--- mcctv/zpu.wcfg	(nonexistent)
+++ mcctv/zpu.wcfg	(revision 181)
@@ -0,0 +1,232 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+            <top_module name="zpupkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="47" />
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_fetch</obj_property>
+      <obj_property name="ObjectShortName">zpu_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_32bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_32bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_32bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_16bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_16bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_16bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_8bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_8bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_8bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_read_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_read_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_read_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_memory_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_memory_ready</obj_property>
+      <obj_property name="ObjectShortName">zpu_memory_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_memory_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_memory_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_memory_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_addr_fetch" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_fetch[23:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_fetch[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/cpu_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_fetch</obj_property>
+      <obj_property name="ObjectShortName">cpu_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/antic_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">antic_fetch</obj_property>
+      <obj_property name="ObjectShortName">antic_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request</obj_property>
+      <obj_property name="ObjectShortName">sdram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_request_complete" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/ram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_request</obj_property>
+      <obj_property name="ObjectShortName">ram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/ram_request_complete" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_request_complete</obj_property>
+      <obj_property name="ObjectShortName">ram_request_complete</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out1" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out1[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out1[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out2[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out2[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out3" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out3[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out3[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out4" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out4[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out4[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/reset_atari" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_atari</obj_property>
+      <obj_property name="ObjectShortName">reset_atari</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/pause_atari" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_atari</obj_property>
+      <obj_property name="ObjectShortName">pause_atari</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_reset_n_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_reset_n_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_ram_sel" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_ram_sel</obj_property>
+      <obj_property name="ObjectShortName">ap1_ram_sel</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_address" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_address[23:1]</obj_property>
+      <obj_property name="ObjectShortName">ap1_address[23:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_rden" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_rden</obj_property>
+      <obj_property name="ObjectShortName">ap1_rden</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wren" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wren</obj_property>
+      <obj_property name="ObjectShortName">ap1_wren</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_bena" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_bena[1:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_bena[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_rddata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_rddata[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_rddata[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wrdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wrdata[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_wrdata[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_bst_siz" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_bst_siz[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_bst_siz[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wr_bst_act" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wr_bst_act</obj_property>
+      <obj_property name="ObjectShortName">ap1_wr_bst_act</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/pause_zpu" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_zpu</obj_property>
+      <obj_property name="ObjectShortName">pause_zpu</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/pause_next" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_next[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pause_next[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/pause_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_reg[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pause_reg[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">addr[4:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[4:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/cpu_data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/wr_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">wr_en</obj_property>
+      <obj_property name="ObjectShortName">wr_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_dat0" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat0</obj_property>
+      <obj_property name="ObjectShortName">sd_dat0</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_clk</obj_property>
+      <obj_property name="ObjectShortName">sd_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_cmd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_cmd</obj_property>
+      <obj_property name="ObjectShortName">sd_cmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_dat3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat3</obj_property>
+      <obj_property name="ObjectShortName">sd_dat3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.opcode" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.opcode</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.opcode</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.pc" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.pc</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.pc</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.sp" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.sp</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.sp</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_a</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_a</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_b" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_b</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_b</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv/usb/rom_com.mif
===================================================================
--- mcctv/usb/rom_com.mif	(nonexistent)
+++ mcctv/usb/rom_com.mif	(revision 181)
@@ -0,0 +1,2053 @@
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- Quartus II generated Memory Initialization File (.mif)
+
+WIDTH=8;
+DEPTH=2048;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	000  :   04;
+	001  :   80;
+	002  :   2D;
+	003  :   00;
+	004  :   10;
+	005  :   0C;
+	006  :   80;
+	007  :   C3;
+	008  :   80;
+	009  :   06;
+	00A  :   00;
+	00B  :   01;
+	[00C..00D]  :   00;
+	00E  :   40;
+	00F  :   00;
+	010  :   DD;
+	011  :   94;
+	012  :   04;
+	013  :   80;
+	014  :   2D;
+	015  :   00;
+	016  :   10;
+	017  :   0C;
+	018  :   80;
+	019  :   C3;
+	01A  :   00;
+	01B  :   05;
+	01C  :   01;
+	[01D..021]  :   00;
+	022  :   EB;
+	023  :   25;
+	024  :   04;
+	025  :   80;
+	026  :   69;
+	027  :   00;
+	028  :   10;
+	029  :   01;
+	02A  :   02;
+	[02B..02C]  :   03;
+	[02D..02E]  :   04;
+	02F  :   05;
+	030  :   00;
+	031  :   01;
+	032  :   02;
+	033  :   03;
+	034  :   04;
+	[035..036]  :   05;
+	037  :   06;
+	038  :   00;
+	039  :   02;
+	03A  :   03;
+	03B  :   04;
+	03C  :   05;
+	[03D..03E]  :   06;
+	03F  :   07;
+	040  :   02;
+	041  :   80;
+	042  :   D2;
+	043  :   05;
+	044  :   06;
+	[045..046]  :   07;
+	047  :   08;
+	048  :   00;
+	049  :   02;
+	04A  :   04;
+	04B  :   05;
+	04C  :   06;
+	04D  :   07;
+	04E  :   08;
+	04F  :   09;
+	050  :   04;
+	051  :   80;
+	052  :   2D;
+	053  :   01;
+	054  :   E8;
+	055  :   0C;
+	056  :   80;
+	057  :   C3;
+	058  :   00;
+	059  :   09;
+	05A  :   01;
+	[05B..05F]  :   00;
+	060  :   27;
+	061  :   25;
+	062  :   04;
+	063  :   80;
+	064  :   69;
+	065  :   01;
+	066  :   E8;
+	067  :   0C;
+	068  :   01;
+	069  :   03;
+	06A  :   06;
+	06B  :   08;
+	06C  :   0A;
+	06D  :   0B;
+	06E  :   0C;
+	06F  :   0D;
+	070  :   04;
+	071  :   80;
+	072  :   2D;
+	073  :   01;
+	074  :   E8;
+	075  :   0C;
+	076  :   80;
+	077  :   C3;
+	078  :   21;
+	079  :   0A;
+	[07A..07F]  :   00;
+	080  :   D6;
+	081  :   20;
+	082  :   04;
+	083  :   80;
+	084  :   69;
+	085  :   01;
+	086  :   E8;
+	087  :   10;
+	088  :   01;
+	089  :   04;
+	08A  :   08;
+	08B  :   0A;
+	08C  :   0D;
+	08D  :   0F;
+	08E  :   10;
+	08F  :   11;
+	090  :   04;
+	091  :   80;
+	092  :   69;
+	093  :   81;
+	094  :   58;
+	095  :   0F;
+	096  :   11;
+	097  :   12;
+	098  :   01;
+	099  :   05;
+	09A  :   08;
+	09B  :   0C;
+	09C  :   0E;
+	09D  :   10;
+	09E  :   12;
+	09F  :   13;
+	0A0  :   01;
+	0A1  :   05;
+	0A2  :   09;
+	0A3  :   0C;
+	0A4  :   0F;
+	0A5  :   11;
+	0A6  :   13;
+	0A7  :   14;
+	0A8  :   02;
+	0A9  :   06;
+	0AA  :   09;
+	0AB  :   0D;
+	0AC  :   10;
+	0AD  :   12;
+	0AE  :   14;
+	0AF  :   15;
+	0B0  :   02;
+	0B1  :   06;
+	0B2  :   0A;
+	0B3  :   0E;
+	0B4  :   11;
+	0B5  :   13;
+	0B6  :   15;
+	0B7  :   16;
+	0B8  :   02;
+	0B9  :   06;
+	0BA  :   0A;
+	0BB  :   0E;
+	0BC  :   11;
+	0BD  :   14;
+	0BE  :   16;
+	0BF  :   17;
+	0C0  :   02;
+	0C1  :   07;
+	0C2  :   0B;
+	0C3  :   0F;
+	0C4  :   12;
+	0C5  :   15;
+	0C6  :   17;
+	0C7  :   18;
+	0C8  :   02;
+	0C9  :   07;
+	0CA  :   0B;
+	0CB  :   0F;
+	0CC  :   13;
+	0CD  :   16;
+	0CE  :   18;
+	0CF  :   19;
+	0D0  :   02;
+	0D1  :   07;
+	0D2  :   0C;
+	0D3  :   10;
+	0D4  :   14;
+	0D5  :   17;
+	0D6  :   19;
+	0D7  :   1A;
+	0D8  :   02;
+	0D9  :   07;
+	0DA  :   0C;
+	0DB  :   11;
+	0DC  :   14;
+	0DD  :   17;
+	0DE  :   19;
+	0DF  :   1B;
+	0E0  :   02;
+	0E1  :   08;
+	0E2  :   0D;
+	0E3  :   11;
+	0E4  :   15;
+	0E5  :   18;
+	0E6  :   1A;
+	0E7  :   1C;
+	0E8  :   02;
+	0E9  :   08;
+	0EA  :   0D;
+	0EB  :   12;
+	0EC  :   16;
+	0ED  :   19;
+	0EE  :   1B;
+	0EF  :   1D;
+	0F0  :   02;
+	0F1  :   08;
+	0F2  :   0E;
+	0F3  :   13;
+	0F4  :   17;
+	0F5  :   1A;
+	0F6  :   1C;
+	0F7  :   1E;
+	0F8  :   03;
+	0F9  :   09;
+	0FA  :   0E;
+	0FB  :   13;
+	0FC  :   18;
+	0FD  :   1B;
+	0FE  :   1D;
+	0FF  :   1F;
+	100  :   03;
+	101  :   09;
+	102  :   0F;
+	103  :   14;
+	104  :   18;
+	105  :   1C;
+	106  :   1E;
+	107  :   20;
+	108  :   03;
+	109  :   09;
+	10A  :   0F;
+	10B  :   15;
+	10C  :   19;
+	10D  :   1D;
+	10E  :   1F;
+	10F  :   21;
+	110  :   03;
+	111  :   09;
+	112  :   10;
+	113  :   15;
+	114  :   1A;
+	115  :   1E;
+	116  :   20;
+	117  :   22;
+	118  :   03;
+	119  :   0A;
+	11A  :   10;
+	11B  :   16;
+	11C  :   1B;
+	11D  :   1F;
+	11E  :   21;
+	11F  :   23;
+	120  :   03;
+	121  :   0A;
+	122  :   11;
+	123  :   16;
+	124  :   1B;
+	125  :   1F;
+	126  :   22;
+	127  :   24;
+	128  :   03;
+	129  :   0A;
+	12A  :   11;
+	12B  :   17;
+	12C  :   1C;
+	12D  :   20;
+	12E  :   23;
+	12F  :   25;
+	130  :   03;
+	131  :   0B;
+	132  :   11;
+	133  :   18;
+	134  :   1D;
+	135  :   21;
+	136  :   24;
+	137  :   26;
+	138  :   03;
+	139  :   0B;
+	13A  :   12;
+	13B  :   18;
+	13C  :   1E;
+	13D  :   22;
+	13E  :   25;
+	13F  :   27;
+	140  :   03;
+	141  :   0B;
+	142  :   12;
+	143  :   19;
+	144  :   1F;
+	145  :   23;
+	146  :   26;
+	147  :   28;
+	148  :   04;
+	149  :   0B;
+	14A  :   13;
+	14B  :   1A;
+	14C  :   1F;
+	14D  :   24;
+	14E  :   27;
+	14F  :   29;
+	150  :   04;
+	151  :   0C;
+	152  :   13;
+	153  :   1A;
+	154  :   20;
+	155  :   25;
+	156  :   28;
+	157  :   2A;
+	158  :   04;
+	159  :   0C;
+	15A  :   14;
+	15B  :   1B;
+	15C  :   21;
+	15D  :   26;
+	15E  :   29;
+	15F  :   2B;
+	160  :   04;
+	161  :   0C;
+	162  :   14;
+	163  :   1C;
+	164  :   22;
+	165  :   26;
+	166  :   2A;
+	167  :   2C;
+	168  :   04;
+	169  :   0D;
+	16A  :   15;
+	16B  :   1C;
+	16C  :   22;
+	16D  :   27;
+	16E  :   2B;
+	16F  :   2D;
+	170  :   04;
+	171  :   0D;
+	172  :   15;
+	173  :   1D;
+	174  :   23;
+	175  :   28;
+	176  :   2C;
+	177  :   2E;
+	178  :   04;
+	179  :   0D;
+	17A  :   16;
+	17B  :   1D;
+	17C  :   24;
+	17D  :   29;
+	17E  :   2D;
+	17F  :   2F;
+	180  :   04;
+	181  :   0E;
+	182  :   16;
+	183  :   1E;
+	184  :   25;
+	185  :   2A;
+	186  :   2E;
+	187  :   30;
+	188  :   04;
+	189  :   0E;
+	18A  :   17;
+	18B  :   1F;
+	18C  :   26;
+	18D  :   2B;
+	18E  :   2F;
+	18F  :   31;
+	190  :   04;
+	191  :   0E;
+	192  :   17;
+	193  :   1F;
+	194  :   26;
+	195  :   2C;
+	196  :   30;
+	197  :   32;
+	198  :   05;
+	199  :   0E;
+	19A  :   18;
+	19B  :   20;
+	19C  :   27;
+	19D  :   2D;
+	19E  :   31;
+	19F  :   33;
+	1A0  :   05;
+	1A1  :   0F;
+	1A2  :   18;
+	1A3  :   21;
+	1A4  :   28;
+	1A5  :   2E;
+	1A6  :   32;
+	1A7  :   34;
+	1A8  :   05;
+	1A9  :   0F;
+	1AA  :   19;
+	1AB  :   21;
+	1AC  :   29;
+	1AD  :   2E;
+	1AE  :   32;
+	1AF  :   35;
+	1B0  :   05;
+	1B1  :   0F;
+	1B2  :   19;
+	1B3  :   22;
+	1B4  :   29;
+	1B5  :   2F;
+	1B6  :   33;
+	1B7  :   36;
+	1B8  :   05;
+	1B9  :   10;
+	1BA  :   1A;
+	1BB  :   23;
+	1BC  :   2A;
+	1BD  :   30;
+	1BE  :   34;
+	1BF  :   37;
+	1C0  :   05;
+	1C1  :   10;
+	1C2  :   1A;
+	1C3  :   23;
+	1C4  :   2B;
+	1C5  :   31;
+	1C6  :   35;
+	1C7  :   38;
+	1C8  :   05;
+	1C9  :   10;
+	1CA  :   1A;
+	1CB  :   24;
+	1CC  :   2C;
+	1CD  :   32;
+	1CE  :   36;
+	1CF  :   39;
+	1D0  :   05;
+	1D1  :   10;
+	1D2  :   1B;
+	1D3  :   24;
+	1D4  :   2D;
+	1D5  :   33;
+	1D6  :   37;
+	1D7  :   3A;
+	1D8  :   05;
+	1D9  :   11;
+	1DA  :   1B;
+	1DB  :   25;
+	1DC  :   2D;
+	1DD  :   34;
+	1DE  :   38;
+	1DF  :   3B;
+	1E0  :   05;
+	1E1  :   11;
+	1E2  :   1C;
+	1E3  :   26;
+	1E4  :   2E;
+	1E5  :   35;
+	1E6  :   39;
+	1E7  :   3C;
+	1E8  :   06;
+	1E9  :   11;
+	1EA  :   1C;
+	1EB  :   26;
+	1EC  :   2F;
+	1ED  :   36;
+	1EE  :   3A;
+	1EF  :   3D;
+	1F0  :   06;
+	1F1  :   12;
+	1F2  :   1D;
+	1F3  :   27;
+	1F4  :   30;
+	1F5  :   36;
+	1F6  :   3B;
+	1F7  :   3E;
+	1F8  :   06;
+	1F9  :   12;
+	1FA  :   1D;
+	1FB  :   28;
+	1FC  :   30;
+	1FD  :   37;
+	1FE  :   3C;
+	1FF  :   3F;
+	200  :   06;
+	201  :   12;
+	202  :   1E;
+	203  :   28;
+	204  :   31;
+	205  :   38;
+	206  :   3D;
+	207  :   40;
+	208  :   06;
+	209  :   12;
+	20A  :   1E;
+	20B  :   29;
+	20C  :   32;
+	20D  :   39;
+	20E  :   3E;
+	20F  :   41;
+	210  :   06;
+	211  :   13;
+	212  :   1F;
+	213  :   2A;
+	214  :   33;
+	215  :   3A;
+	216  :   3F;
+	217  :   42;
+	218  :   06;
+	219  :   13;
+	21A  :   1F;
+	21B  :   2A;
+	21C  :   34;
+	21D  :   3B;
+	21E  :   40;
+	21F  :   43;
+	220  :   06;
+	221  :   13;
+	222  :   20;
+	223  :   2B;
+	224  :   34;
+	225  :   3C;
+	226  :   41;
+	227  :   44;
+	228  :   06;
+	229  :   14;
+	22A  :   20;
+	22B  :   2B;
+	22C  :   35;
+	22D  :   3D;
+	22E  :   42;
+	22F  :   45;
+	230  :   06;
+	231  :   14;
+	232  :   21;
+	233  :   2C;
+	234  :   36;
+	235  :   3E;
+	236  :   43;
+	237  :   46;
+	238  :   06;
+	239  :   14;
+	23A  :   21;
+	23B  :   2D;
+	23C  :   37;
+	23D  :   3E;
+	23E  :   44;
+	23F  :   47;
+	240  :   07;
+	241  :   15;
+	242  :   22;
+	243  :   2D;
+	244  :   37;
+	245  :   3F;
+	246  :   45;
+	247  :   48;
+	248  :   07;
+	249  :   15;
+	24A  :   22;
+	24B  :   2E;
+	24C  :   38;
+	24D  :   40;
+	24E  :   46;
+	24F  :   49;
+	250  :   07;
+	251  :   15;
+	252  :   23;
+	253  :   2F;
+	254  :   39;
+	255  :   41;
+	256  :   47;
+	257  :   4A;
+	258  :   07;
+	259  :   15;
+	25A  :   23;
+	25B  :   2F;
+	25C  :   3A;
+	25D  :   42;
+	25E  :   48;
+	25F  :   4B;
+	260  :   07;
+	261  :   16;
+	262  :   23;
+	263  :   30;
+	264  :   3B;
+	265  :   43;
+	266  :   49;
+	267  :   4C;
+	268  :   07;
+	269  :   16;
+	26A  :   24;
+	26B  :   31;
+	26C  :   3B;
+	26D  :   44;
+	26E  :   4A;
+	26F  :   4D;
+	270  :   07;
+	271  :   16;
+	272  :   24;
+	273  :   31;
+	274  :   3C;
+	275  :   45;
+	276  :   4B;
+	277  :   4E;
+	278  :   07;
+	279  :   17;
+	27A  :   25;
+	27B  :   32;
+	27C  :   3D;
+	27D  :   46;
+	27E  :   4B;
+	27F  :   4F;
+	280  :   07;
+	281  :   17;
+	282  :   25;
+	283  :   32;
+	284  :   3E;
+	285  :   46;
+	286  :   4C;
+	287  :   50;
+	288  :   07;
+	289  :   17;
+	28A  :   26;
+	28B  :   33;
+	28C  :   3E;
+	28D  :   47;
+	28E  :   4D;
+	28F  :   51;
+	290  :   08;
+	291  :   17;
+	292  :   26;
+	293  :   34;
+	294  :   3F;
+	295  :   48;
+	296  :   4E;
+	297  :   52;
+	298  :   08;
+	299  :   18;
+	29A  :   27;
+	29B  :   34;
+	29C  :   40;
+	29D  :   49;
+	29E  :   4F;
+	29F  :   53;
+	2A0  :   08;
+	2A1  :   18;
+	2A2  :   27;
+	2A3  :   35;
+	2A4  :   41;
+	2A5  :   4A;
+	2A6  :   50;
+	2A7  :   54;
+	2A8  :   08;
+	2A9  :   18;
+	2AA  :   28;
+	2AB  :   36;
+	2AC  :   42;
+	2AD  :   4B;
+	2AE  :   51;
+	2AF  :   55;
+	2B0  :   08;
+	2B1  :   19;
+	2B2  :   28;
+	2B3  :   36;
+	2B4  :   42;
+	2B5  :   4C;
+	2B6  :   52;
+	2B7  :   56;
+	2B8  :   08;
+	2B9  :   19;
+	2BA  :   29;
+	2BB  :   37;
+	2BC  :   43;
+	2BD  :   4D;
+	2BE  :   53;
+	2BF  :   57;
+	2C0  :   08;
+	2C1  :   19;
+	2C2  :   29;
+	2C3  :   38;
+	2C4  :   44;
+	2C5  :   4D;
+	2C6  :   54;
+	2C7  :   58;
+	2C8  :   08;
+	2C9  :   19;
+	2CA  :   2A;
+	2CB  :   38;
+	2CC  :   45;
+	2CD  :   4E;
+	2CE  :   55;
+	2CF  :   59;
+	2D0  :   08;
+	2D1  :   1A;
+	2D2  :   2A;
+	2D3  :   39;
+	2D4  :   45;
+	2D5  :   4F;
+	2D6  :   56;
+	2D7  :   5A;
+	2D8  :   08;
+	2D9  :   1A;
+	2DA  :   2B;
+	2DB  :   3A;
+	2DC  :   46;
+	2DD  :   50;
+	2DE  :   57;
+	2DF  :   5B;
+	2E0  :   09;
+	2E1  :   1A;
+	2E2  :   2B;
+	2E3  :   3A;
+	2E4  :   47;
+	2E5  :   51;
+	2E6  :   58;
+	2E7  :   5C;
+	2E8  :   09;
+	2E9  :   1B;
+	2EA  :   2C;
+	2EB  :   3B;
+	2EC  :   48;
+	2ED  :   52;
+	2EE  :   59;
+	2EF  :   5D;
+	2F0  :   09;
+	2F1  :   1B;
+	2F2  :   2C;
+	2F3  :   3B;
+	2F4  :   49;
+	2F5  :   53;
+	2F6  :   5A;
+	2F7  :   5E;
+	2F8  :   09;
+	2F9  :   1B;
+	2FA  :   2C;
+	2FB  :   3C;
+	2FC  :   49;
+	2FD  :   54;
+	2FE  :   5B;
+	2FF  :   5F;
+	300  :   09;
+	301  :   1C;
+	302  :   2D;
+	303  :   3D;
+	304  :   4A;
+	305  :   55;
+	306  :   5C;
+	307  :   60;
+	308  :   09;
+	309  :   1C;
+	30A  :   2D;
+	30B  :   3D;
+	30C  :   4B;
+	30D  :   55;
+	30E  :   5D;
+	30F  :   61;
+	310  :   09;
+	311  :   1C;
+	312  :   2E;
+	313  :   3E;
+	314  :   4C;
+	315  :   56;
+	316  :   5E;
+	317  :   62;
+	318  :   09;
+	319  :   1C;
+	31A  :   2E;
+	31B  :   3F;
+	31C  :   4C;
+	31D  :   57;
+	31E  :   5F;
+	31F  :   63;
+	320  :   09;
+	321  :   1D;
+	322  :   2F;
+	323  :   3F;
+	324  :   4D;
+	325  :   58;
+	326  :   60;
+	327  :   64;
+	328  :   09;
+	329  :   1D;
+	32A  :   2F;
+	32B  :   40;
+	32C  :   4E;
+	32D  :   59;
+	32E  :   61;
+	32F  :   65;
+	330  :   0A;
+	331  :   1D;
+	332  :   30;
+	333  :   41;
+	334  :   4F;
+	335  :   5A;
+	336  :   62;
+	337  :   66;
+	338  :   0A;
+	339  :   1E;
+	33A  :   30;
+	33B  :   41;
+	33C  :   50;
+	33D  :   5B;
+	33E  :   63;
+	33F  :   67;
+	340  :   0A;
+	341  :   1E;
+	342  :   31;
+	343  :   42;
+	344  :   50;
+	345  :   5C;
+	346  :   64;
+	347  :   68;
+	348  :   0A;
+	349  :   1E;
+	34A  :   31;
+	34B  :   42;
+	34C  :   51;
+	34D  :   5D;
+	34E  :   64;
+	34F  :   69;
+	350  :   0A;
+	351  :   1E;
+	352  :   32;
+	353  :   43;
+	354  :   52;
+	355  :   5D;
+	356  :   65;
+	357  :   6A;
+	358  :   0A;
+	359  :   1F;
+	35A  :   32;
+	35B  :   44;
+	35C  :   53;
+	35D  :   5E;
+	35E  :   66;
+	35F  :   6B;
+	360  :   0A;
+	361  :   1F;
+	362  :   33;
+	363  :   44;
+	364  :   53;
+	365  :   5F;
+	366  :   67;
+	367  :   6C;
+	368  :   0A;
+	369  :   1F;
+	36A  :   33;
+	36B  :   45;
+	36C  :   54;
+	36D  :   60;
+	36E  :   68;
+	36F  :   6D;
+	370  :   0A;
+	371  :   20;
+	372  :   34;
+	373  :   46;
+	374  :   55;
+	375  :   61;
+	376  :   69;
+	377  :   6E;
+	378  :   0A;
+	379  :   20;
+	37A  :   34;
+	37B  :   46;
+	37C  :   56;
+	37D  :   62;
+	37E  :   6A;
+	37F  :   6F;
+	380  :   0B;
+	381  :   20;
+	382  :   35;
+	383  :   47;
+	384  :   56;
+	385  :   63;
+	386  :   6B;
+	387  :   70;
+	388  :   0B;
+	389  :   20;
+	38A  :   35;
+	38B  :   48;
+	38C  :   57;
+	38D  :   64;
+	38E  :   6C;
+	38F  :   71;
+	390  :   0B;
+	391  :   21;
+	392  :   35;
+	393  :   48;
+	394  :   58;
+	395  :   65;
+	396  :   6D;
+	397  :   72;
+	398  :   0B;
+	399  :   21;
+	39A  :   36;
+	39B  :   49;
+	39C  :   59;
+	39D  :   65;
+	39E  :   6E;
+	39F  :   73;
+	3A0  :   0B;
+	3A1  :   21;
+	3A2  :   36;
+	3A3  :   49;
+	3A4  :   5A;
+	3A5  :   66;
+	3A6  :   6F;
+	3A7  :   74;
+	3A8  :   0B;
+	3A9  :   22;
+	3AA  :   37;
+	3AB  :   4A;
+	3AC  :   5A;
+	3AD  :   67;
+	3AE  :   70;
+	3AF  :   75;
+	3B0  :   0B;
+	3B1  :   22;
+	3B2  :   37;
+	3B3  :   4B;
+	3B4  :   5B;
+	3B5  :   68;
+	3B6  :   71;
+	3B7  :   76;
+	3B8  :   0B;
+	3B9  :   22;
+	3BA  :   38;
+	3BB  :   4B;
+	3BC  :   5C;
+	3BD  :   69;
+	3BE  :   72;
+	3BF  :   77;
+	3C0  :   0B;
+	3C1  :   23;
+	3C2  :   38;
+	3C3  :   4C;
+	3C4  :   5D;
+	3C5  :   6A;
+	3C6  :   73;
+	3C7  :   78;
+	3C8  :   0B;
+	3C9  :   23;
+	3CA  :   39;
+	3CB  :   4D;
+	3CC  :   5D;
+	3CD  :   6B;
+	3CE  :   74;
+	3CF  :   79;
+	3D0  :   0C;
+	3D1  :   23;
+	3D2  :   39;
+	3D3  :   4D;
+	3D4  :   5E;
+	3D5  :   6C;
+	3D6  :   75;
+	3D7  :   7A;
+	3D8  :   0C;
+	3D9  :   23;
+	3DA  :   3A;
+	3DB  :   4E;
+	3DC  :   5F;
+	3DD  :   6D;
+	3DE  :   76;
+	3DF  :   7B;
+	3E0  :   0C;
+	3E1  :   24;
+	3E2  :   3A;
+	3E3  :   4F;
+	3E4  :   60;
+	3E5  :   6D;
+	3E6  :   77;
+	3E7  :   7C;
+	3E8  :   0C;
+	3E9  :   24;
+	3EA  :   3B;
+	3EB  :   4F;
+	3EC  :   61;
+	3ED  :   6E;
+	3EE  :   78;
+	3EF  :   7D;
+	3F0  :   0C;
+	3F1  :   24;
+	3F2  :   3B;
+	3F3  :   50;
+	3F4  :   61;
+	3F5  :   6F;
+	3F6  :   79;
+	3F7  :   7E;
+	3F8  :   0C;
+	3F9  :   25;
+	3FA  :   3C;
+	3FB  :   50;
+	3FC  :   62;
+	3FD  :   70;
+	3FE  :   7A;
+	3FF  :   7F;
+	400  :   0C;
+	401  :   25;
+	402  :   3C;
+	403  :   51;
+	404  :   63;
+	405  :   71;
+	406  :   7B;
+	407  :   80;
+	408  :   0C;
+	409  :   25;
+	40A  :   3D;
+	40B  :   52;
+	40C  :   64;
+	40D  :   72;
+	40E  :   7C;
+	40F  :   81;
+	410  :   0C;
+	411  :   25;
+	412  :   3D;
+	413  :   52;
+	414  :   64;
+	415  :   73;
+	416  :   7D;
+	417  :   82;
+	418  :   0C;
+	419  :   26;
+	41A  :   3E;
+	41B  :   53;
+	41C  :   65;
+	41D  :   74;
+	41E  :   7D;
+	41F  :   83;
+	420  :   0D;
+	421  :   26;
+	422  :   3E;
+	423  :   54;
+	424  :   66;
+	425  :   74;
+	426  :   7E;
+	427  :   84;
+	428  :   0D;
+	429  :   26;
+	42A  :   3E;
+	42B  :   54;
+	42C  :   67;
+	42D  :   75;
+	42E  :   7F;
+	42F  :   85;
+	430  :   0D;
+	431  :   27;
+	432  :   3F;
+	433  :   55;
+	434  :   68;
+	435  :   76;
+	436  :   80;
+	437  :   86;
+	438  :   0D;
+	439  :   27;
+	43A  :   3F;
+	43B  :   56;
+	43C  :   68;
+	43D  :   77;
+	43E  :   81;
+	43F  :   87;
+	440  :   0D;
+	441  :   27;
+	442  :   40;
+	443  :   56;
+	444  :   69;
+	445  :   78;
+	446  :   82;
+	447  :   88;
+	448  :   0D;
+	449  :   27;
+	44A  :   40;
+	44B  :   57;
+	44C  :   6A;
+	44D  :   79;
+	44E  :   83;
+	44F  :   89;
+	450  :   0D;
+	451  :   28;
+	452  :   41;
+	453  :   57;
+	454  :   6B;
+	455  :   7A;
+	456  :   84;
+	457  :   8A;
+	458  :   0D;
+	459  :   28;
+	45A  :   41;
+	45B  :   58;
+	45C  :   6B;
+	45D  :   7B;
+	45E  :   85;
+	45F  :   8B;
+	460  :   0D;
+	461  :   28;
+	462  :   42;
+	463  :   59;
+	464  :   6C;
+	465  :   7C;
+	466  :   86;
+	467  :   8C;
+	468  :   0D;
+	469  :   29;
+	46A  :   42;
+	46B  :   59;
+	46C  :   6D;
+	46D  :   7C;
+	46E  :   87;
+	46F  :   8D;
+	470  :   0D;
+	471  :   29;
+	472  :   43;
+	473  :   5A;
+	474  :   6E;
+	475  :   7D;
+	476  :   88;
+	477  :   8E;
+	478  :   0E;
+	479  :   29;
+	47A  :   43;
+	47B  :   5B;
+	47C  :   6F;
+	47D  :   7E;
+	47E  :   89;
+	47F  :   8F;
+	480  :   0E;
+	481  :   2A;
+	482  :   44;
+	483  :   5B;
+	484  :   6F;
+	485  :   7F;
+	486  :   8A;
+	487  :   90;
+	488  :   0E;
+	489  :   2A;
+	48A  :   44;
+	48B  :   5C;
+	48C  :   70;
+	48D  :   80;
+	48E  :   8B;
+	48F  :   91;
+	490  :   0E;
+	491  :   2A;
+	492  :   45;
+	493  :   5D;
+	494  :   71;
+	495  :   81;
+	496  :   8C;
+	497  :   92;
+	498  :   0E;
+	499  :   2A;
+	49A  :   45;
+	49B  :   5D;
+	49C  :   72;
+	49D  :   82;
+	49E  :   8D;
+	49F  :   93;
+	4A0  :   0E;
+	4A1  :   2B;
+	4A2  :   46;
+	4A3  :   5E;
+	4A4  :   72;
+	4A5  :   83;
+	4A6  :   8E;
+	4A7  :   94;
+	4A8  :   0E;
+	4A9  :   2B;
+	4AA  :   46;
+	4AB  :   5E;
+	4AC  :   73;
+	4AD  :   84;
+	4AE  :   8F;
+	4AF  :   95;
+	4B0  :   0E;
+	4B1  :   2B;
+	4B2  :   47;
+	4B3  :   5F;
+	4B4  :   74;
+	4B5  :   84;
+	4B6  :   90;
+	4B7  :   96;
+	4B8  :   0E;
+	4B9  :   2C;
+	4BA  :   47;
+	4BB  :   60;
+	4BC  :   75;
+	4BD  :   85;
+	4BE  :   91;
+	4BF  :   97;
+	4C0  :   0E;
+	4C1  :   2C;
+	4C2  :   47;
+	4C3  :   60;
+	4C4  :   76;
+	4C5  :   86;
+	4C6  :   92;
+	4C7  :   98;
+	4C8  :   0F;
+	4C9  :   2C;
+	4CA  :   48;
+	4CB  :   61;
+	4CC  :   76;
+	4CD  :   87;
+	4CE  :   93;
+	4CF  :   99;
+	4D0  :   0F;
+	4D1  :   2C;
+	4D2  :   48;
+	4D3  :   62;
+	4D4  :   77;
+	4D5  :   88;
+	4D6  :   94;
+	4D7  :   9A;
+	4D8  :   0F;
+	4D9  :   2D;
+	4DA  :   49;
+	4DB  :   62;
+	4DC  :   78;
+	4DD  :   89;
+	4DE  :   95;
+	4DF  :   9B;
+	4E0  :   0F;
+	4E1  :   2D;
+	4E2  :   49;
+	4E3  :   63;
+	4E4  :   79;
+	4E5  :   8A;
+	4E6  :   96;
+	4E7  :   9C;
+	4E8  :   0F;
+	4E9  :   2D;
+	4EA  :   4A;
+	4EB  :   64;
+	4EC  :   79;
+	4ED  :   8B;
+	4EE  :   96;
+	4EF  :   9D;
+	4F0  :   0F;
+	4F1  :   2E;
+	4F2  :   4A;
+	4F3  :   64;
+	4F4  :   7A;
+	4F5  :   8C;
+	4F6  :   97;
+	4F7  :   9E;
+	4F8  :   0F;
+	4F9  :   2E;
+	4FA  :   4B;
+	4FB  :   65;
+	4FC  :   7B;
+	4FD  :   8C;
+	4FE  :   98;
+	4FF  :   9F;
+	500  :   0F;
+	501  :   2E;
+	502  :   4B;
+	503  :   65;
+	504  :   7C;
+	505  :   8D;
+	506  :   99;
+	507  :   A0;
+	508  :   0F;
+	509  :   2E;
+	50A  :   4C;
+	50B  :   66;
+	50C  :   7D;
+	50D  :   8E;
+	50E  :   9A;
+	50F  :   A1;
+	510  :   0F;
+	511  :   2F;
+	512  :   4C;
+	513  :   67;
+	514  :   7D;
+	515  :   8F;
+	516  :   9B;
+	517  :   A2;
+	518  :   10;
+	519  :   2F;
+	51A  :   4D;
+	51B  :   67;
+	51C  :   7E;
+	51D  :   90;
+	51E  :   9C;
+	51F  :   A3;
+	520  :   10;
+	521  :   2F;
+	522  :   4D;
+	523  :   68;
+	524  :   7F;
+	525  :   91;
+	526  :   9D;
+	527  :   A4;
+	528  :   10;
+	529  :   30;
+	52A  :   4E;
+	52B  :   69;
+	52C  :   80;
+	52D  :   92;
+	52E  :   9E;
+	52F  :   A5;
+	530  :   10;
+	531  :   30;
+	532  :   4E;
+	533  :   69;
+	534  :   80;
+	535  :   93;
+	536  :   9F;
+	537  :   A6;
+	538  :   10;
+	539  :   30;
+	53A  :   4F;
+	53B  :   6A;
+	53C  :   81;
+	53D  :   93;
+	53E  :   A0;
+	53F  :   A7;
+	540  :   10;
+	541  :   31;
+	542  :   4F;
+	543  :   6B;
+	544  :   82;
+	545  :   94;
+	546  :   A1;
+	547  :   A8;
+	548  :   10;
+	549  :   31;
+	54A  :   50;
+	54B  :   6B;
+	54C  :   83;
+	54D  :   95;
+	54E  :   A2;
+	54F  :   A9;
+	550  :   10;
+	551  :   31;
+	552  :   50;
+	553  :   6C;
+	554  :   84;
+	555  :   96;
+	556  :   A3;
+	557  :   AA;
+	558  :   10;
+	559  :   31;
+	55A  :   50;
+	55B  :   6D;
+	55C  :   84;
+	55D  :   97;
+	55E  :   A4;
+	55F  :   AB;
+	560  :   10;
+	561  :   32;
+	562  :   51;
+	563  :   6D;
+	564  :   85;
+	565  :   98;
+	566  :   A5;
+	567  :   AC;
+	568  :   11;
+	569  :   32;
+	56A  :   51;
+	56B  :   6E;
+	56C  :   86;
+	56D  :   99;
+	56E  :   A6;
+	56F  :   AD;
+	570  :   11;
+	571  :   32;
+	572  :   52;
+	573  :   6E;
+	574  :   87;
+	575  :   9A;
+	576  :   A7;
+	577  :   AE;
+	578  :   11;
+	579  :   33;
+	57A  :   52;
+	57B  :   6F;
+	57C  :   87;
+	57D  :   9B;
+	57E  :   A8;
+	57F  :   AF;
+	580  :   11;
+	581  :   33;
+	582  :   53;
+	583  :   70;
+	584  :   88;
+	585  :   9B;
+	586  :   A9;
+	587  :   B0;
+	588  :   11;
+	589  :   33;
+	58A  :   53;
+	58B  :   70;
+	58C  :   89;
+	58D  :   9C;
+	58E  :   AA;
+	58F  :   B1;
+	590  :   11;
+	591  :   33;
+	592  :   54;
+	593  :   71;
+	594  :   8A;
+	595  :   9D;
+	596  :   AB;
+	597  :   B2;
+	598  :   11;
+	599  :   34;
+	59A  :   54;
+	59B  :   72;
+	59C  :   8B;
+	59D  :   9E;
+	59E  :   AC;
+	59F  :   B3;
+	5A0  :   11;
+	5A1  :   34;
+	5A2  :   55;
+	5A3  :   72;
+	5A4  :   8B;
+	5A5  :   9F;
+	5A6  :   AD;
+	5A7  :   B4;
+	5A8  :   11;
+	5A9  :   34;
+	5AA  :   55;
+	5AB  :   73;
+	5AC  :   8C;
+	5AD  :   A0;
+	5AE  :   AE;
+	5AF  :   B5;
+	5B0  :   11;
+	5B1  :   35;
+	5B2  :   56;
+	5B3  :   74;
+	5B4  :   8D;
+	5B5  :   A1;
+	5B6  :   AF;
+	5B7  :   B6;
+	5B8  :   12;
+	5B9  :   35;
+	5BA  :   56;
+	5BB  :   74;
+	5BC  :   8E;
+	5BD  :   A2;
+	5BE  :   AF;
+	5BF  :   B7;
+	5C0  :   12;
+	5C1  :   35;
+	5C2  :   57;
+	5C3  :   75;
+	5C4  :   8E;
+	5C5  :   A3;
+	5C6  :   B0;
+	5C7  :   B8;
+	5C8  :   12;
+	5C9  :   35;
+	5CA  :   57;
+	5CB  :   75;
+	5CC  :   8F;
+	5CD  :   A3;
+	5CE  :   B1;
+	5CF  :   B9;
+	5D0  :   12;
+	5D1  :   36;
+	5D2  :   58;
+	5D3  :   76;
+	5D4  :   90;
+	5D5  :   A4;
+	5D6  :   B2;
+	5D7  :   BA;
+	5D8  :   12;
+	5D9  :   36;
+	5DA  :   58;
+	5DB  :   77;
+	5DC  :   91;
+	5DD  :   A5;
+	5DE  :   B3;
+	5DF  :   BB;
+	5E0  :   12;
+	5E1  :   36;
+	5E2  :   59;
+	5E3  :   77;
+	5E4  :   92;
+	5E5  :   A6;
+	5E6  :   B4;
+	5E7  :   BC;
+	5E8  :   12;
+	5E9  :   37;
+	5EA  :   59;
+	5EB  :   78;
+	5EC  :   92;
+	5ED  :   A7;
+	5EE  :   B5;
+	5EF  :   BD;
+	5F0  :   12;
+	5F1  :   37;
+	5F2  :   59;
+	5F3  :   79;
+	5F4  :   93;
+	5F5  :   A8;
+	5F6  :   B6;
+	5F7  :   BE;
+	5F8  :   12;
+	5F9  :   37;
+	5FA  :   5A;
+	5FB  :   79;
+	5FC  :   94;
+	5FD  :   A9;
+	5FE  :   B7;
+	5FF  :   BF;
+	600  :   12;
+	601  :   38;
+	602  :   5A;
+	603  :   7A;
+	604  :   95;
+	605  :   AA;
+	606  :   B8;
+	607  :   C0;
+	608  :   13;
+	609  :   38;
+	60A  :   5B;
+	60B  :   7B;
+	60C  :   95;
+	60D  :   AB;
+	60E  :   B9;
+	60F  :   C1;
+	610  :   13;
+	611  :   38;
+	612  :   5B;
+	613  :   7B;
+	614  :   96;
+	615  :   AB;
+	616  :   BA;
+	617  :   C2;
+	618  :   13;
+	619  :   38;
+	61A  :   5C;
+	61B  :   7C;
+	61C  :   97;
+	61D  :   AC;
+	61E  :   BB;
+	61F  :   C3;
+	620  :   13;
+	621  :   39;
+	622  :   5C;
+	623  :   7C;
+	624  :   98;
+	625  :   AD;
+	626  :   BC;
+	627  :   C4;
+	628  :   13;
+	629  :   39;
+	62A  :   5D;
+	62B  :   7D;
+	62C  :   99;
+	62D  :   AE;
+	62E  :   BD;
+	62F  :   C5;
+	630  :   13;
+	631  :   39;
+	632  :   5D;
+	633  :   7E;
+	634  :   99;
+	635  :   AF;
+	636  :   BE;
+	637  :   C6;
+	638  :   13;
+	639  :   3A;
+	63A  :   5E;
+	63B  :   7E;
+	63C  :   9A;
+	63D  :   B0;
+	63E  :   BF;
+	63F  :   C7;
+	640  :   13;
+	641  :   3A;
+	642  :   5E;
+	643  :   7F;
+	644  :   9B;
+	645  :   B1;
+	646  :   C0;
+	647  :   C8;
+	648  :   13;
+	649  :   3A;
+	64A  :   5F;
+	64B  :   80;
+	64C  :   9C;
+	64D  :   B2;
+	64E  :   C1;
+	64F  :   C9;
+	650  :   13;
+	651  :   3A;
+	652  :   5F;
+	653  :   80;
+	654  :   9C;
+	655  :   B3;
+	656  :   C2;
+	657  :   CA;
+	658  :   13;
+	659  :   3B;
+	65A  :   60;
+	65B  :   81;
+	65C  :   9D;
+	65D  :   B3;
+	65E  :   C3;
+	65F  :   CB;
+	660  :   14;
+	661  :   3B;
+	662  :   60;
+	663  :   82;
+	664  :   9E;
+	665  :   B4;
+	666  :   C4;
+	667  :   CC;
+	668  :   14;
+	669  :   3B;
+	66A  :   61;
+	66B  :   82;
+	66C  :   9F;
+	66D  :   B5;
+	66E  :   C5;
+	66F  :   CD;
+	670  :   14;
+	671  :   3C;
+	672  :   61;
+	673  :   83;
+	674  :   A0;
+	675  :   B6;
+	676  :   C6;
+	677  :   CE;
+	678  :   14;
+	679  :   3C;
+	67A  :   62;
+	67B  :   83;
+	67C  :   A0;
+	67D  :   B7;
+	67E  :   C7;
+	67F  :   CF;
+	680  :   14;
+	681  :   3C;
+	682  :   62;
+	683  :   84;
+	684  :   A1;
+	685  :   B8;
+	686  :   C8;
+	687  :   D0;
+	688  :   14;
+	689  :   3C;
+	68A  :   62;
+	68B  :   85;
+	68C  :   A2;
+	68D  :   B9;
+	68E  :   C8;
+	68F  :   D1;
+	690  :   14;
+	691  :   3D;
+	692  :   63;
+	693  :   85;
+	694  :   A3;
+	695  :   BA;
+	696  :   C9;
+	697  :   D2;
+	698  :   14;
+	699  :   3D;
+	69A  :   63;
+	69B  :   86;
+	69C  :   A3;
+	69D  :   BA;
+	69E  :   CA;
+	69F  :   D3;
+	6A0  :   14;
+	6A1  :   3D;
+	6A2  :   64;
+	6A3  :   87;
+	6A4  :   A4;
+	6A5  :   BB;
+	6A6  :   CB;
+	6A7  :   D4;
+	6A8  :   14;
+	6A9  :   3E;
+	6AA  :   64;
+	6AB  :   87;
+	6AC  :   A5;
+	6AD  :   BC;
+	6AE  :   CC;
+	6AF  :   D5;
+	6B0  :   15;
+	6B1  :   3E;
+	6B2  :   65;
+	6B3  :   88;
+	6B4  :   A6;
+	6B5  :   BD;
+	6B6  :   CD;
+	6B7  :   D6;
+	6B8  :   15;
+	6B9  :   3E;
+	6BA  :   65;
+	6BB  :   89;
+	6BC  :   A7;
+	6BD  :   BE;
+	6BE  :   CE;
+	6BF  :   D7;
+	6C0  :   15;
+	6C1  :   3F;
+	6C2  :   66;
+	6C3  :   89;
+	6C4  :   A7;
+	6C5  :   BF;
+	6C6  :   CF;
+	6C7  :   D8;
+	6C8  :   15;
+	6C9  :   3F;
+	6CA  :   66;
+	6CB  :   8A;
+	6CC  :   A8;
+	6CD  :   C0;
+	6CE  :   D0;
+	6CF  :   D9;
+	6D0  :   15;
+	6D1  :   3F;
+	6D2  :   67;
+	6D3  :   8A;
+	6D4  :   A9;
+	6D5  :   C1;
+	6D6  :   D1;
+	6D7  :   DA;
+	6D8  :   15;
+	6D9  :   3F;
+	6DA  :   67;
+	6DB  :   8B;
+	6DC  :   AA;
+	6DD  :   C2;
+	6DE  :   D2;
+	6DF  :   DB;
+	6E0  :   15;
+	6E1  :   40;
+	6E2  :   68;
+	6E3  :   8C;
+	6E4  :   AA;
+	6E5  :   C2;
+	6E6  :   D3;
+	6E7  :   DC;
+	6E8  :   15;
+	6E9  :   40;
+	6EA  :   68;
+	6EB  :   8C;
+	6EC  :   AB;
+	6ED  :   C3;
+	6EE  :   D4;
+	6EF  :   DD;
+	6F0  :   15;
+	6F1  :   40;
+	6F2  :   69;
+	6F3  :   8D;
+	6F4  :   AC;
+	6F5  :   C4;
+	6F6  :   D5;
+	6F7  :   DE;
+	6F8  :   15;
+	6F9  :   41;
+	6FA  :   69;
+	6FB  :   8E;
+	6FC  :   AD;
+	6FD  :   C5;
+	6FE  :   D6;
+	6FF  :   DF;
+	700  :   16;
+	701  :   41;
+	702  :   6A;
+	703  :   8E;
+	704  :   AD;
+	705  :   C6;
+	706  :   D7;
+	707  :   E0;
+	708  :   16;
+	709  :   41;
+	70A  :   6A;
+	70B  :   8F;
+	70C  :   AE;
+	70D  :   C7;
+	70E  :   D8;
+	70F  :   E1;
+	710  :   16;
+	711  :   41;
+	712  :   6B;
+	713  :   90;
+	714  :   AF;
+	715  :   C8;
+	716  :   D9;
+	717  :   E2;
+	718  :   16;
+	719  :   42;
+	71A  :   6B;
+	71B  :   90;
+	71C  :   B0;
+	71D  :   C9;
+	71E  :   DA;
+	71F  :   E3;
+	720  :   16;
+	721  :   42;
+	722  :   6B;
+	723  :   91;
+	724  :   B1;
+	725  :   CA;
+	726  :   DB;
+	727  :   E4;
+	728  :   16;
+	729  :   42;
+	72A  :   6C;
+	72B  :   91;
+	72C  :   B1;
+	72D  :   CA;
+	72E  :   DC;
+	72F  :   E5;
+	730  :   16;
+	731  :   43;
+	732  :   6C;
+	733  :   92;
+	734  :   B2;
+	735  :   CB;
+	736  :   DD;
+	737  :   E6;
+	738  :   16;
+	739  :   43;
+	73A  :   6D;
+	73B  :   93;
+	73C  :   B3;
+	73D  :   CC;
+	73E  :   DE;
+	73F  :   E7;
+	740  :   16;
+	741  :   43;
+	742  :   6D;
+	743  :   93;
+	744  :   B4;
+	745  :   CD;
+	746  :   DF;
+	747  :   E8;
+	748  :   16;
+	749  :   43;
+	74A  :   6E;
+	74B  :   94;
+	74C  :   B4;
+	74D  :   CE;
+	74E  :   E0;
+	74F  :   E9;
+	750  :   17;
+	751  :   44;
+	752  :   6E;
+	753  :   95;
+	754  :   B5;
+	755  :   CF;
+	756  :   E1;
+	757  :   EA;
+	758  :   17;
+	759  :   44;
+	75A  :   6F;
+	75B  :   95;
+	75C  :   B6;
+	75D  :   D0;
+	75E  :   E1;
+	75F  :   EB;
+	760  :   17;
+	761  :   44;
+	762  :   6F;
+	763  :   96;
+	764  :   B7;
+	765  :   D1;
+	766  :   E2;
+	767  :   EC;
+	768  :   17;
+	769  :   45;
+	76A  :   70;
+	76B  :   97;
+	76C  :   B8;
+	76D  :   D2;
+	76E  :   E3;
+	76F  :   ED;
+	770  :   17;
+	771  :   45;
+	772  :   70;
+	773  :   97;
+	774  :   B8;
+	775  :   D2;
+	776  :   E4;
+	777  :   EE;
+	778  :   17;
+	779  :   45;
+	77A  :   71;
+	77B  :   98;
+	77C  :   B9;
+	77D  :   D3;
+	77E  :   E5;
+	77F  :   EF;
+	780  :   17;
+	781  :   46;
+	782  :   71;
+	783  :   98;
+	784  :   BA;
+	785  :   D4;
+	786  :   E6;
+	787  :   F0;
+	788  :   17;
+	789  :   46;
+	78A  :   72;
+	78B  :   99;
+	78C  :   BB;
+	78D  :   D5;
+	78E  :   E7;
+	78F  :   F1;
+	790  :   17;
+	791  :   46;
+	792  :   72;
+	793  :   9A;
+	794  :   BB;
+	795  :   D6;
+	796  :   E8;
+	797  :   F2;
+	798  :   17;
+	799  :   46;
+	79A  :   73;
+	79B  :   9A;
+	79C  :   BC;
+	79D  :   D7;
+	79E  :   E9;
+	79F  :   F3;
+	7A0  :   18;
+	7A1  :   47;
+	7A2  :   73;
+	7A3  :   9B;
+	7A4  :   BD;
+	7A5  :   D8;
+	7A6  :   EA;
+	7A7  :   F4;
+	7A8  :   18;
+	7A9  :   47;
+	7AA  :   74;
+	7AB  :   9C;
+	7AC  :   BE;
+	7AD  :   D9;
+	7AE  :   EB;
+	7AF  :   F5;
+	7B0  :   18;
+	7B1  :   47;
+	7B2  :   74;
+	7B3  :   9C;
+	7B4  :   BF;
+	7B5  :   DA;
+	7B6  :   EC;
+	7B7  :   F6;
+	7B8  :   18;
+	7B9  :   48;
+	7BA  :   74;
+	7BB  :   9D;
+	7BC  :   BF;
+	7BD  :   DA;
+	7BE  :   ED;
+	7BF  :   F7;
+	7C0  :   18;
+	7C1  :   48;
+	7C2  :   75;
+	7C3  :   9E;
+	7C4  :   C0;
+	7C5  :   DB;
+	7C6  :   EE;
+	7C7  :   F8;
+	7C8  :   18;
+	7C9  :   48;
+	7CA  :   75;
+	7CB  :   9E;
+	7CC  :   C1;
+	7CD  :   DC;
+	7CE  :   EF;
+	7CF  :   F9;
+	7D0  :   18;
+	7D1  :   48;
+	7D2  :   76;
+	7D3  :   9F;
+	7D4  :   C2;
+	7D5  :   DD;
+	7D6  :   F0;
+	7D7  :   FA;
+	7D8  :   18;
+	7D9  :   49;
+	7DA  :   76;
+	7DB  :   A0;
+	7DC  :   C2;
+	7DD  :   DE;
+	7DE  :   F1;
+	7DF  :   FB;
+	7E0  :   18;
+	7E1  :   49;
+	7E2  :   77;
+	7E3  :   A0;
+	7E4  :   C3;
+	7E5  :   DF;
+	7E6  :   F2;
+	7E7  :   FC;
+	7E8  :   18;
+	7E9  :   49;
+	7EA  :   77;
+	7EB  :   A1;
+	7EC  :   C4;
+	7ED  :   E0;
+	7EE  :   F3;
+	7EF  :   FD;
+	7F0  :   19;
+	7F1  :   4A;
+	7F2  :   78;
+	7F3  :   A1;
+	7F4  :   C5;
+	7F5  :   E1;
+	7F6  :   F4;
+	7F7  :   FE;
+	7F8  :   19;
+	7F9  :   4A;
+	7FA  :   78;
+	7FB  :   A2;
+	7FC  :   C6;
+	7FD  :   E1;
+	7FE  :   F5;
+	7FF  :   FF;
+END;
Index: mcctv/usb/rom_com1.qip
===================================================================
--- mcctv/usb/rom_com1.qip	(nonexistent)
+++ mcctv/usb/rom_com1.qip	(revision 181)
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "10.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rom_com1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rom_com1.cmp"]
Index: mcctv/usb/rom_com2.vhd
===================================================================
--- mcctv/usb/rom_com2.vhd	(nonexistent)
+++ mcctv/usb/rom_com2.vhd	(revision 181)
@@ -0,0 +1,178 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: rom_com2.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY rom_com2 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END rom_com2;
+
+
+ARCHITECTURE SYN OF rom_com2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rden_a	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./usb/rom_com.mif",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=NONE",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 9,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		rden_a => rden,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./usb/rom_com.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./usb/rom_com.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=NONE"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com_inst.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com2.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_com2_inst.vhd FALSE
Index: mcctv/zpu_rom.vhdl
===================================================================
--- mcctv/zpu_rom.vhdl	(nonexistent)
+++ mcctv/zpu_rom.vhdl	(revision 181)
@@ -0,0 +1,4130 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(11 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ad040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
+X"81ff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"0b0b80f8",
+X"bc738306",
+X"10100508",
+X"060b0b0b",
+X"88a20400",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"ff040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"d8040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097081",
+X"0509060a",
+X"8106ff05",
+X"70547106",
+X"73097274",
+X"05ff0506",
+X"07515151",
+X"04000000",
+X"72097081",
+X"0509060a",
+X"098106ff",
+X"05705471",
+X"06730972",
+X"7405ff05",
+X"06075151",
+X"51040000",
+X"05ff0504",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"810b80fb",
+X"900c5104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007181",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000284",
+X"05721010",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007171",
+X"05ff0571",
+X"5351020d",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101053",
+X"51047381",
+X"ff067383",
+X"06098105",
+X"83051010",
+X"102b0772",
+X"fc060c51",
+X"51043c04",
+X"72728072",
+X"8106ff05",
+X"09720605",
+X"71105272",
+X"0a100a53",
+X"72ed3851",
+X"51535104",
+X"83e08008",
+X"83e08408",
+X"83e08808",
+X"757580f2",
+X"ea2d5050",
+X"83e08008",
+X"5683e088",
+X"0c83e084",
+X"0c83e080",
+X"0c510483",
+X"e0800883",
+X"e0840883",
+X"e0880875",
+X"7580f0fe",
+X"2d505083",
+X"e0800856",
+X"83e0880c",
+X"83e0840c",
+X"83e0800c",
+X"51040000",
+X"800489aa",
+X"0489aa0b",
+X"96ea0480",
+X"3d0d80fc",
+X"d4087008",
+X"810683e0",
+X"800c5182",
+X"3d0d04ff",
+X"3d0d80fc",
+X"d4087008",
+X"70fe0676",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80fcd408",
+X"70087081",
+X"2c810683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80fcd408",
+X"700870fd",
+X"06761007",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"fcd40870",
+X"0870822c",
+X"bf0683e0",
+X"800c5151",
+X"823d0d04",
+X"ff3d0d80",
+X"fcd40870",
+X"0870fe83",
+X"0676822b",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80fcd408",
+X"70087088",
+X"2c870683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80fcd408",
+X"700870f1",
+X"ff067688",
+X"2b07720c",
+X"5252833d",
+X"0d04803d",
+X"0d80fcd4",
+X"08700870",
+X"8b2cbf06",
+X"83e0800c",
+X"5151823d",
+X"0d04ff3d",
+X"0d80fcd4",
+X"08700870",
+X"f88fff06",
+X"768b2b07",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"fce40870",
+X"0870882c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"fce40870",
+X"0870892c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"fce40870",
+X"08708a2c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"fce40870",
+X"08708b2c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"fd3d0d75",
+X"81e62987",
+X"2a80fcc4",
+X"0854730c",
+X"853d0d04",
+X"fe3d0d75",
+X"75ff1953",
+X"535370ff",
+X"2e8d3872",
+X"72708105",
+X"5434ff11",
+X"51f03984",
+X"3d0d04fe",
+X"3d0d7575",
+X"ff195353",
+X"5370ff2e",
+X"8d387272",
+X"70840554",
+X"0cff1151",
+X"f039843d",
+X"0d04fe3d",
+X"0d848080",
+X"53805288",
+X"800a51ff",
+X"b33f8180",
+X"80538052",
+X"82800a51",
+X"c63f843d",
+X"0d04803d",
+X"0d8151fc",
+X"ce3f7280",
+X"2e8338d2",
+X"3f8151fc",
+X"f03f8051",
+X"fceb3f80",
+X"51fcb83f",
+X"823d0d04",
+X"fd3d0d75",
+X"52805480",
+X"ff722588",
+X"38810bff",
+X"80135354",
+X"ffbf1251",
+X"70992686",
+X"38e01252",
+X"9e39ff9f",
+X"12519971",
+X"279538d0",
+X"12e01370",
+X"54545189",
+X"71278838",
+X"8f732783",
+X"38805273",
+X"802e8538",
+X"81801252",
+X"7181ff06",
+X"83e0800c",
+X"853d0d04",
+X"803d0d86",
+X"b8c05180",
+X"71708105",
+X"53347086",
+X"c0c02e09",
+X"8106f038",
+X"823d0d04",
+X"fe3d0d02",
+X"97053351",
+X"ff863f83",
+X"e0800881",
+X"ff0683e0",
+X"9c085452",
+X"8073249b",
+X"3883e0b8",
+X"08137283",
+X"e0bc0807",
+X"53537173",
+X"3483e09c",
+X"08810583",
+X"e09c0c84",
+X"3d0d04fa",
+X"3d0d8280",
+X"0a1b5580",
+X"57883dfc",
+X"05547953",
+X"74527851",
+X"b4f93f88",
+X"3d0d04fe",
+X"3d0d83e0",
+X"b0085274",
+X"51bbdb3f",
+X"83e08008",
+X"8c387653",
+X"755283e0",
+X"b00851c7",
+X"3f843d0d",
+X"04fe3d0d",
+X"83e0b008",
+X"53755274",
+X"51b69b3f",
+X"83e08008",
+X"8d387753",
+X"765283e0",
+X"b00851ff",
+X"a23f843d",
+X"0d04fe3d",
+X"0d83e0b4",
+X"0851b58f",
+X"3f83e080",
+X"08818080",
+X"2e098106",
+X"883883c1",
+X"8080539b",
+X"3983e0b4",
+X"0851b4f3",
+X"3f83e080",
+X"0880d080",
+X"2e098106",
+X"933883c1",
+X"b0805383",
+X"e0800852",
+X"83e0b408",
+X"51fed83f",
+X"843d0d04",
+X"803d0dfa",
+X"cc3f83e0",
+X"80088429",
+X"80fb9805",
+X"700883e0",
+X"800c5182",
+X"3d0d04ee",
+X"3d0d8043",
+X"80428041",
+X"80705a5b",
+X"fdd23f80",
+X"0b83e09c",
+X"0c800b83",
+X"e0bc0c0b",
+X"0b80f9d8",
+X"51afdd3f",
+X"81800b83",
+X"e0bc0c0b",
+X"0b80f9dc",
+X"51afcd3f",
+X"80d00b83",
+X"e09c0c78",
+X"30707a07",
+X"80257087",
+X"2b83e0bc",
+X"0c5155f9",
+X"b73f83e0",
+X"8008520b",
+X"0b80f9e4",
+X"51afa53f",
+X"80f80b83",
+X"e09c0c78",
+X"81327030",
+X"70720780",
+X"2570872b",
+X"83e0bc0c",
+X"515656fe",
+X"eb3f83e0",
+X"8008520b",
+X"0b80f9f0",
+X"51aef93f",
+X"81a00b83",
+X"e09c0c78",
+X"82327030",
+X"70720780",
+X"2570872b",
+X"83e0bc0c",
+X"515683e0",
+X"b4085256",
+X"b0943f83",
+X"e0800852",
+X"0b0b80f9",
+X"f851aec8",
+X"3f81f00b",
+X"83e09c0c",
+X"810b83e0",
+X"a05b5883",
+X"e09c0882",
+X"197a3270",
+X"30707207",
+X"80257087",
+X"2b83e0bc",
+X"0c51578e",
+X"3d7055ff",
+X"1b545757",
+X"57a4a63f",
+X"79708405",
+X"5b0851af",
+X"c93f7454",
+X"83e08008",
+X"5377520b",
+X"0b80fa80",
+X"51adf93f",
+X"a81783e0",
+X"9c0c8118",
+X"5877852e",
+X"098106ff",
+X"ae388390",
+X"0b83e09c",
+X"0c788732",
+X"70307072",
+X"07802570",
+X"872b83e0",
+X"bc0c5156",
+X"0b0b80fa",
+X"905256ad",
+X"c33f83e0",
+X"0b83e09c",
+X"0c788832",
+X"70307072",
+X"07802570",
+X"872b83e0",
+X"bc0c5156",
+X"0b0b80fa",
+X"a45256ad",
+X"9f3f868d",
+X"a051f990",
+X"3f805291",
+X"3d705255",
+X"8ba53f83",
+X"5274518b",
+X"9e3f6119",
+X"59788025",
+X"85388059",
+X"90398879",
+X"25853888",
+X"59873978",
+X"882682ae",
+X"3878822b",
+X"5580f8cc",
+X"150804f6",
+X"e33f83e0",
+X"80086157",
+X"5575812e",
+X"09810689",
+X"3883e080",
+X"08105590",
+X"3975ff2e",
+X"09810688",
+X"3883e080",
+X"08812c55",
+X"90752585",
+X"38905588",
+X"39748024",
+X"83388155",
+X"7451f6c0",
+X"3f81e339",
+X"f6d33f83",
+X"e0800861",
+X"05557480",
+X"25853880",
+X"55883987",
+X"75258338",
+X"87557451",
+X"f6cf3f81",
+X"c1396087",
+X"3862802e",
+X"81b838a0",
+X"990b83e0",
+X"d00c83e0",
+X"b408518c",
+X"a93ffafe",
+X"3f81a339",
+X"60568076",
+X"2598389f",
+X"b80b83e0",
+X"d00c83e0",
+X"94157008",
+X"52558c8a",
+X"3f740852",
+X"91397580",
+X"25913883",
+X"e0941508",
+X"51ad853f",
+X"8052fd19",
+X"51b83962",
+X"802e80ea",
+X"3883e094",
+X"15700883",
+X"e0a00872",
+X"0c83e0a0",
+X"0cfd1a70",
+X"53515596",
+X"dc3f83e0",
+X"80085680",
+X"5196d23f",
+X"83e08008",
+X"52745192",
+X"f13f7552",
+X"805192ea",
+X"3fb43962",
+X"802eaf38",
+X"a0990b83",
+X"e0d00c83",
+X"e0b00851",
+X"8ba03f83",
+X"e0b00851",
+X"ac943f9c",
+X"800a5380",
+X"c0805283",
+X"e0800851",
+X"f9993f81",
+X"558c3962",
+X"87387a80",
+X"2efac538",
+X"80557483",
+X"e0800c94",
+X"3d0d04fe",
+X"3d0df5c0",
+X"3f83e080",
+X"08802e86",
+X"38805180",
+X"f639f5c8",
+X"3f83e080",
+X"0880ea38",
+X"f5ee3f83",
+X"e0800880",
+X"2eaa3881",
+X"51f3c03f",
+X"839b3f80",
+X"0b83e09c",
+X"0cf9f43f",
+X"83e08008",
+X"53ff0b83",
+X"e09c0c85",
+X"ee3f72bd",
+X"387251f3",
+X"9e3fbb39",
+X"f5a23f83",
+X"e0800880",
+X"2eb03881",
+X"51f38c3f",
+X"82e73f9f",
+X"b80b83e0",
+X"d00c83e0",
+X"a0085189",
+X"fd3fff0b",
+X"83e09c0c",
+X"85b93f83",
+X"e0a00852",
+X"8051919e",
+X"3f8151f6",
+X"8d3f843d",
+X"0d0483e0",
+X"8c080283",
+X"e08c0cfa",
+X"3d0d800b",
+X"83e0a00b",
+X"83e08c08",
+X"fc050c83",
+X"e08c08f8",
+X"050cadd0",
+X"3f83e080",
+X"088605fc",
+X"0683e08c",
+X"08f4050c",
+X"0283e08c",
+X"08f40508",
+X"310d853d",
+X"7083e08c",
+X"08fc0508",
+X"70840583",
+X"e08c08fc",
+X"050c0c51",
+X"aa9a3f83",
+X"e08c08f8",
+X"05088105",
+X"83e08c08",
+X"f8050c83",
+X"e08c08f8",
+X"0508862e",
+X"098106ff",
+X"ad388694",
+X"80805181",
+X"aa3fff0b",
+X"83e09c0c",
+X"800b83e0",
+X"bc0c86b8",
+X"c00b83e0",
+X"b80c8151",
+X"f1c93f81",
+X"51f1f23f",
+X"8051f1ed",
+X"3f8151f2",
+X"973f8151",
+X"f2f43f82",
+X"51f2be3f",
+X"8e845280",
+X"51a7de3f",
+X"90808052",
+X"86848080",
+X"51adb93f",
+X"83e08008",
+X"80d33893",
+X"b53f80fe",
+X"9c51b1f8",
+X"3f83e080",
+X"0883e0b4",
+X"08540b0b",
+X"80faac53",
+X"83e08008",
+X"5283e08c",
+X"08f4050c",
+X"accc3f83",
+X"e0800884",
+X"38f6bf3f",
+X"9c800a54",
+X"80c08053",
+X"0b0b80fa",
+X"b85283e0",
+X"8c08f405",
+X"0851f681",
+X"3f8151f3",
+X"f13f9d8d",
+X"3f8151f3",
+X"e93ffccf",
+X"3ffc3971",
+X"83e0c40c",
+X"8880800b",
+X"83e0c00c",
+X"8480800b",
+X"83e0c80c",
+X"04f03d0d",
+X"80fbcc08",
+X"54733383",
+X"e0cc3483",
+X"a0805683",
+X"e0c40816",
+X"83e0c008",
+X"17565474",
+X"33743483",
+X"e0c80816",
+X"54807434",
+X"81165675",
+X"83a0a02e",
+X"098106db",
+X"3883a480",
+X"5683e0c4",
+X"081683e0",
+X"c0081756",
+X"54743374",
+X"3483e0c8",
+X"08165480",
+X"74348116",
+X"567583a4",
+X"a02e0981",
+X"06db3883",
+X"a8805683",
+X"e0c40816",
+X"83e0c008",
+X"17565474",
+X"33743483",
+X"e0c80816",
+X"54807434",
+X"81165675",
+X"83a8902e",
+X"098106db",
+X"3880fbcc",
+X"0854ff74",
+X"34805683",
+X"e0c40816",
+X"83e0c808",
+X"17555573",
+X"33753481",
+X"16567583",
+X"a0802e09",
+X"8106e438",
+X"83b08056",
+X"83e0c408",
+X"1683e0c8",
+X"08175555",
+X"73337534",
+X"81165675",
+X"8480802e",
+X"098106e4",
+X"38f2ed3f",
+X"893d58a2",
+X"5380f8f0",
+X"52775180",
+X"dc953f80",
+X"578c8056",
+X"83e0c808",
+X"16771955",
+X"55733375",
+X"34811681",
+X"18585676",
+X"a22e0981",
+X"06e63880",
+X"fbf00854",
+X"86743480",
+X"fbf40854",
+X"80743480",
+X"fbec0854",
+X"80743480",
+X"fbdc0854",
+X"af743480",
+X"fbe80854",
+X"bf743480",
+X"fbe40854",
+X"80743480",
+X"fbe00854",
+X"9f743480",
+X"fbd80854",
+X"80743480",
+X"fbc40854",
+X"e0743480",
+X"fbbc0854",
+X"76743480",
+X"fbb80854",
+X"83743480",
+X"fbc00854",
+X"82743492",
+X"3d0d04fe",
+X"3d0d8053",
+X"83e0c808",
+X"1383e0c4",
+X"08145252",
+X"70337234",
+X"81135372",
+X"83a0802e",
+X"098106e4",
+X"3883b080",
+X"5383e0c8",
+X"081383e0",
+X"c4081452",
+X"52703372",
+X"34811353",
+X"72848080",
+X"2e098106",
+X"e43883a0",
+X"805383e0",
+X"c8081383",
+X"e0c40814",
+X"52527033",
+X"72348113",
+X"537283a0",
+X"a02e0981",
+X"06e43883",
+X"a4805383",
+X"e0c80813",
+X"83e0c408",
+X"14525270",
+X"33723481",
+X"13537283",
+X"a4a02e09",
+X"8106e438",
+X"83a88053",
+X"83e0c808",
+X"1383e0c4",
+X"08145252",
+X"70337234",
+X"81135372",
+X"83a8902e",
+X"098106e4",
+X"3880fbcc",
+X"085183e0",
+X"cc337134",
+X"843d0d04",
+X"fd3d0d75",
+X"5480740c",
+X"800b8415",
+X"0c800b88",
+X"150c80fb",
+X"d0087033",
+X"7081ff06",
+X"70812a81",
+X"32718132",
+X"71810671",
+X"81063184",
+X"1a0c5656",
+X"70832a81",
+X"3271822a",
+X"81327181",
+X"06718106",
+X"31790c52",
+X"55515151",
+X"80fbc808",
+X"70337009",
+X"81068817",
+X"0c515185",
+X"3d0d04fe",
+X"3d0d7476",
+X"54527151",
+X"ff9a3f72",
+X"812ea238",
+X"8173268d",
+X"3872822e",
+X"ab387283",
+X"2e9f38e6",
+X"397108e2",
+X"38841208",
+X"dd388812",
+X"08d838a0",
+X"39881208",
+X"812e0981",
+X"06cc3894",
+X"39881208",
+X"812e8d38",
+X"71088938",
+X"84120880",
+X"2effb738",
+X"843d0d04",
+X"fc3d0d76",
+X"70525580",
+X"c6ec3f83",
+X"e0800815",
+X"ff055473",
+X"752e8e38",
+X"73335372",
+X"ae2e8638",
+X"ff1454ef",
+X"39775281",
+X"145180c6",
+X"833f83e0",
+X"80083070",
+X"83e08008",
+X"07802583",
+X"e0800c53",
+X"863d0d04",
+X"fc3d0d76",
+X"705255ab",
+X"e13f83e0",
+X"80085481",
+X"5383e080",
+X"0880c138",
+X"7451aba4",
+X"3f83e080",
+X"0880fad4",
+X"5383e080",
+X"085253ff",
+X"8f3f83e0",
+X"8008a138",
+X"80fad852",
+X"7251ff80",
+X"3f83e080",
+X"08923880",
+X"fadc5272",
+X"51fef13f",
+X"83e08008",
+X"802e8338",
+X"81547353",
+X"7283e080",
+X"0c863d0d",
+X"04fd3d0d",
+X"75705254",
+X"ab803f81",
+X"5383e080",
+X"08973873",
+X"51aac93f",
+X"80fae052",
+X"83e08008",
+X"51feb93f",
+X"83e08008",
+X"537283e0",
+X"800c853d",
+X"0d04e03d",
+X"0da33d08",
+X"70525ea0",
+X"f13f83e0",
+X"80083394",
+X"3d565473",
+X"943880fe",
+X"b4527451",
+X"84b3397d",
+X"527851a3",
+X"f33f84be",
+X"397d51a0",
+X"d93f83e0",
+X"80085274",
+X"51a0893f",
+X"83e0d008",
+X"52933d70",
+X"525da6e3",
+X"3f83e080",
+X"0859800b",
+X"83e08008",
+X"555b83e0",
+X"80087b2e",
+X"9438811b",
+X"74525ba9",
+X"e43f83e0",
+X"80085483",
+X"e08008ee",
+X"38805aff",
+X"7a437a42",
+X"7a415f79",
+X"09709f2c",
+X"7b065b54",
+X"7a7a2484",
+X"38ff1b5a",
+X"f61a7009",
+X"709f2c72",
+X"067bff12",
+X"5a5a5255",
+X"55807525",
+X"95387651",
+X"a9a33f83",
+X"e0800876",
+X"ff185855",
+X"57738024",
+X"ed38747f",
+X"2e8638eb",
+X"e33f745f",
+X"78ff1b70",
+X"585d5880",
+X"7a259538",
+X"7751a8f9",
+X"3f83e080",
+X"0876ff18",
+X"58555873",
+X"8024ed38",
+X"800b83e0",
+X"9c0c800b",
+X"83e0bc0c",
+X"80fae451",
+X"9dce3f81",
+X"800b83e0",
+X"bc0c80fa",
+X"ec519dc0",
+X"3fa80b83",
+X"e09c0c76",
+X"802e80e4",
+X"3883e09c",
+X"08777932",
+X"70307072",
+X"07802570",
+X"872b83e0",
+X"bc0c5156",
+X"78535656",
+X"a8b03f83",
+X"e0800880",
+X"2e883880",
+X"faf4519d",
+X"873f7651",
+X"a7f23f83",
+X"e0800852",
+X"80fa8c51",
+X"9cf63f76",
+X"51a7fa3f",
+X"83e08008",
+X"83e09c08",
+X"55577574",
+X"258638a8",
+X"1656f739",
+X"7583e09c",
+X"0c86f076",
+X"24ff9838",
+X"87980b83",
+X"e09c0c77",
+X"802eb138",
+X"7751a7b0",
+X"3f83e080",
+X"08785255",
+X"a7d03f80",
+X"fafc5483",
+X"e080088d",
+X"38873980",
+X"7634fda0",
+X"3980faf8",
+X"54745373",
+X"5280fac8",
+X"519c953f",
+X"805480fb",
+X"84519c8c",
+X"3f811454",
+X"73a82e09",
+X"8106ef38",
+X"868da051",
+X"e7f23f80",
+X"52903d70",
+X"5254fa87",
+X"3f835273",
+X"51fa803f",
+X"61802e80",
+X"ff387b54",
+X"73ff2e96",
+X"3878802e",
+X"81803878",
+X"51a6da3f",
+X"83e08008",
+X"ff155559",
+X"e7397880",
+X"2e80eb38",
+X"7851a6d6",
+X"3f83e080",
+X"08802efc",
+X"96387851",
+X"a69e3f83",
+X"e0800852",
+X"80fad051",
+X"bfc13f83",
+X"e08008a5",
+X"387c5180",
+X"c0f83f83",
+X"e0800855",
+X"74ff1656",
+X"54807425",
+X"fc823874",
+X"1d703355",
+X"5673af2e",
+X"fed138e8",
+X"397851a5",
+X"dd3f83e0",
+X"8008527c",
+X"5180c0ae",
+X"3ffbe139",
+X"7f882960",
+X"10057a05",
+X"61055afc",
+X"9239a23d",
+X"0d04803d",
+X"0d81ff51",
+X"800b83e0",
+X"dc1234ff",
+X"115170f4",
+X"38823d0d",
+X"04ff3d0d",
+X"73703353",
+X"51811133",
+X"71347181",
+X"1234833d",
+X"0d04fb3d",
+X"0d777956",
+X"56807071",
+X"55555271",
+X"7525ac38",
+X"72167033",
+X"70147081",
+X"ff065551",
+X"51517174",
+X"27893881",
+X"127081ff",
+X"06535171",
+X"81147083",
+X"ffff0655",
+X"52547473",
+X"24d63871",
+X"83e0800c",
+X"873d0d04",
+X"fd3d0d75",
+X"54948f3f",
+X"83e08008",
+X"802ef638",
+X"83e2f808",
+X"86057081",
+X"ff065253",
+X"91e83f84",
+X"39ef903f",
+X"93f03f83",
+X"e0800881",
+X"2ef33892",
+X"cb3f83e0",
+X"80087434",
+X"92c23f83",
+X"e0800881",
+X"153492b8",
+X"3f83e080",
+X"08821534",
+X"92ae3f83",
+X"e0800883",
+X"153492a4",
+X"3f83e080",
+X"08841534",
+X"8439eecf",
+X"3f93af3f",
+X"83e08008",
+X"802ef338",
+X"733383e0",
+X"dc348114",
+X"3383e0dd",
+X"34821433",
+X"83e0de34",
+X"83143383",
+X"e0df3484",
+X"5283e0dc",
+X"51fea73f",
+X"83e08008",
+X"81ff0684",
+X"15335553",
+X"72742e09",
+X"81068c38",
+X"92a03f83",
+X"e0800880",
+X"2e9a3883",
+X"e2f808a8",
+X"2e098106",
+X"8938860b",
+X"83e2f80c",
+X"8739a80b",
+X"83e2f80c",
+X"80e451e4",
+X"873f853d",
+X"0d04f43d",
+X"0d7e6059",
+X"55805d80",
+X"75822b71",
+X"83e2fc12",
+X"0c83e390",
+X"175b5b57",
+X"76793477",
+X"772e83b1",
+X"38765277",
+X"519be13f",
+X"8e3dfc05",
+X"54905383",
+X"e2e45277",
+X"519b983f",
+X"7c567590",
+X"2e098106",
+X"838f3883",
+X"e2e451fd",
+X"843f83e2",
+X"e651fcfd",
+X"3f83e2e8",
+X"51fcf63f",
+X"7683e2f4",
+X"0c775198",
+X"e53f80fa",
+X"d85283e0",
+X"800851f6",
+X"873f83e0",
+X"8008812e",
+X"09810680",
+X"d3387683",
+X"e38c0c82",
+X"0b83e2e4",
+X"34ff960b",
+X"83e2e534",
+X"77519bab",
+X"3f83e080",
+X"085583e0",
+X"80087725",
+X"883883e0",
+X"80088f05",
+X"5574842c",
+X"7083ffff",
+X"0670882a",
+X"58515575",
+X"83e2e634",
+X"7483e2e7",
+X"347683e2",
+X"e834ff80",
+X"0b83e2e9",
+X"34818f39",
+X"83e2e433",
+X"83e2e533",
+X"71882b07",
+X"565b7483",
+X"ffff2e09",
+X"810680e7",
+X"38fe800b",
+X"83e38c0c",
+X"810b83e2",
+X"f40cff0b",
+X"83e2e434",
+X"ff0b83e2",
+X"e5347751",
+X"9ab93f83",
+X"e0800883",
+X"e3940c83",
+X"e0800855",
+X"83e08008",
+X"80258838",
+X"83e08008",
+X"8f055574",
+X"842c7083",
+X"ffff0670",
+X"882a5851",
+X"557583e2",
+X"e6347483",
+X"e2e73476",
+X"83e2e834",
+X"ff800b83",
+X"e2e93481",
+X"0b83e2f3",
+X"34a43974",
+X"85962e09",
+X"810680fd",
+X"387583e3",
+X"8c0c7751",
+X"99ee3f83",
+X"e2f33383",
+X"e0800807",
+X"557483e2",
+X"f33483e2",
+X"f3338106",
+X"5574802e",
+X"83388457",
+X"83e2e833",
+X"83e2e933",
+X"71882b07",
+X"565c7481",
+X"802e0981",
+X"06a13883",
+X"e2e63383",
+X"e2e73371",
+X"882b0756",
+X"5bad8075",
+X"27873876",
+X"8207579c",
+X"39768107",
+X"57963974",
+X"82802e09",
+X"81068738",
+X"76830757",
+X"87397481",
+X"ff268a38",
+X"7783e2fc",
+X"1b0c7679",
+X"348e3d0d",
+X"04803d0d",
+X"72842983",
+X"e2fc0570",
+X"0883e080",
+X"0c51823d",
+X"0d04fe3d",
+X"0d800b83",
+X"e2e00c80",
+X"0b83e2dc",
+X"0cff0b83",
+X"e0d80ca8",
+X"0b83e2f8",
+X"0cae518c",
+X"a53f800b",
+X"83e2fc54",
+X"52807370",
+X"8405550c",
+X"81125271",
+X"842e0981",
+X"06ef3884",
+X"3d0d04fe",
+X"3d0d7402",
+X"84059605",
+X"22535371",
+X"802e9638",
+X"72708105",
+X"5433518c",
+X"c43fff12",
+X"7083ffff",
+X"065152e7",
+X"39843d0d",
+X"04fe3d0d",
+X"02920522",
+X"5382ac51",
+X"dfa23f80",
+X"c3518ca1",
+X"3f819651",
+X"df963f72",
+X"5283e0dc",
+X"51ffb43f",
+X"725283e0",
+X"dc51f8e6",
+X"3f83e080",
+X"0881ff06",
+X"518bfe3f",
+X"843d0d04",
+X"ffb13d0d",
+X"80d13df8",
+X"0551f990",
+X"3f83e2e0",
+X"08810583",
+X"e2e00c80",
+X"cf3d33cf",
+X"117081ff",
+X"06515656",
+X"74832688",
+X"cd38758f",
+X"06ff0556",
+X"7583e0d8",
+X"082e9b38",
+X"75832696",
+X"387583e0",
+X"d80c7584",
+X"2983e2fc",
+X"05700853",
+X"557551fa",
+X"a13f8076",
+X"2488a938",
+X"75842983",
+X"e2fc0555",
+X"7408802e",
+X"889a3883",
+X"e0d80884",
+X"2983e2fc",
+X"05700802",
+X"880582b9",
+X"0533525b",
+X"557480d2",
+X"2e849a38",
+X"7480d224",
+X"903874bf",
+X"2e9c3874",
+X"80d02e81",
+X"d13887d9",
+X"397480d3",
+X"2e80cf38",
+X"7480d72e",
+X"81c03887",
+X"c8390282",
+X"bb053302",
+X"840582ba",
+X"05337182",
+X"80290556",
+X"568b803f",
+X"80c1518a",
+X"b43ff6e2",
+X"3f860b83",
+X"e0dc3481",
+X"5283e0dc",
+X"518bef3f",
+X"8151fde9",
+X"3f748938",
+X"860b83e2",
+X"f80c8739",
+X"a80b83e2",
+X"f80c8acf",
+X"3f80c151",
+X"8a833ff6",
+X"b13f900b",
+X"83e2f333",
+X"81065656",
+X"74802e83",
+X"38985683",
+X"e2e83383",
+X"e2e93371",
+X"882b0756",
+X"59748180",
+X"2e098106",
+X"9c3883e2",
+X"e63383e2",
+X"e7337188",
+X"2b075657",
+X"ad807527",
+X"8c387581",
+X"80075685",
+X"3975a007",
+X"567583e0",
+X"dc34ff0b",
+X"83e0dd34",
+X"e00b83e0",
+X"de34800b",
+X"83e0df34",
+X"845283e0",
+X"dc518ae6",
+X"3f845186",
+X"86390282",
+X"bb053302",
+X"840582ba",
+X"05337182",
+X"80290556",
+X"5989c43f",
+X"795194c0",
+X"3f83e080",
+X"08802e8a",
+X"3880ce51",
+X"88eb3f85",
+X"dd3980c1",
+X"5188e23f",
+X"89ea3f87",
+X"ee3f83e3",
+X"8c085883",
+X"75259b38",
+X"83e2e833",
+X"83e2e933",
+X"71882b07",
+X"fc177129",
+X"7a058380",
+X"055a5157",
+X"8d397481",
+X"802918ff",
+X"80055881",
+X"80578056",
+X"76762e92",
+X"3888c13f",
+X"83e08008",
+X"83e0dc17",
+X"34811656",
+X"eb3988b0",
+X"3f83e080",
+X"0881ff06",
+X"775383e0",
+X"dc5256f4",
+X"dd3f83e0",
+X"800881ff",
+X"06557575",
+X"2e098106",
+X"81843888",
+X"b23f80c1",
+X"5187e63f",
+X"88ee3f77",
+X"52795192",
+X"df3f805e",
+X"80d13dfd",
+X"f4055476",
+X"5383e0dc",
+X"52795190",
+X"e83f0282",
+X"b9053355",
+X"81587480",
+X"d72e0981",
+X"06bc3880",
+X"d13dfdf0",
+X"05547653",
+X"8f3d7053",
+X"7a525991",
+X"ee3f8056",
+X"76762ea2",
+X"38751983",
+X"e0dc1733",
+X"71337072",
+X"32703070",
+X"80257030",
+X"7e06811d",
+X"5d5e5151",
+X"51525b55",
+X"db3982ac",
+X"51d9f13f",
+X"77802e86",
+X"3880c351",
+X"843980ce",
+X"5186e63f",
+X"87ee3f85",
+X"f23f83d5",
+X"390282bb",
+X"05330284",
+X"0582ba05",
+X"33718280",
+X"29055955",
+X"80705d59",
+X"87893f80",
+X"c15186bd",
+X"3f83e2f4",
+X"08792e82",
+X"db3883e3",
+X"940880fc",
+X"055580fd",
+X"527451bd",
+X"b73f83e0",
+X"80085b77",
+X"8224b238",
+X"ff187087",
+X"2b83ffff",
+X"800680fc",
+X"e80583e0",
+X"dc595755",
+X"81805575",
+X"70810557",
+X"33777081",
+X"055934ff",
+X"157081ff",
+X"06515574",
+X"ea38828a",
+X"397782e8",
+X"2e81aa38",
+X"7782e92e",
+X"09810681",
+X"b13880fb",
+X"80518cd4",
+X"3f785877",
+X"87327030",
+X"70720780",
+X"257a8a32",
+X"70307072",
+X"07802573",
+X"0753545a",
+X"51575575",
+X"802e9738",
+X"78782692",
+X"38a00b83",
+X"e0dc1a34",
+X"81197081",
+X"ff065a55",
+X"eb398118",
+X"7081ff06",
+X"59558a78",
+X"27ffbc38",
+X"8f5883e0",
+X"d7183383",
+X"e0dc1934",
+X"ff187081",
+X"ff065955",
+X"778426ea",
+X"38905880",
+X"0b83e0dc",
+X"19348118",
+X"7081ff06",
+X"70982b52",
+X"59557480",
+X"25e93880",
+X"c6557a85",
+X"8f248438",
+X"80c25574",
+X"83e0dc34",
+X"80f10b83",
+X"e0df3481",
+X"0b83e0e0",
+X"347a83e0",
+X"dd347a88",
+X"2c557483",
+X"e0de3480",
+X"c93982f0",
+X"782580c2",
+X"387780fd",
+X"29fd97d3",
+X"05527951",
+X"8f963f80",
+X"d13dfdec",
+X"055480fd",
+X"5383e0dc",
+X"5279518e",
+X"ca3f7b81",
+X"19595675",
+X"80fc2483",
+X"38785877",
+X"882c5574",
+X"83e1d934",
+X"7783e1da",
+X"347583e1",
+X"db348180",
+X"5980ca39",
+X"83e38c08",
+X"57837825",
+X"9b3883e2",
+X"e83383e2",
+X"e9337188",
+X"2b07fc1a",
+X"71297905",
+X"83800559",
+X"51598d39",
+X"77818029",
+X"17ff8005",
+X"57818059",
+X"76527951",
+X"8ea63f80",
+X"d13dfdec",
+X"05547853",
+X"83e0dc52",
+X"79518ddb",
+X"3f7851f6",
+X"d83f8494",
+X"3f82983f",
+X"8b3983e2",
+X"dc088105",
+X"83e2dc0c",
+X"80d13d0d",
+X"04f6f93f",
+X"dfc53ff9",
+X"39fc3d0d",
+X"76787184",
+X"2983e2fc",
+X"05700851",
+X"53535370",
+X"9e3880ce",
+X"723480cf",
+X"0b811334",
+X"80ce0b82",
+X"133480c5",
+X"0b831334",
+X"70841334",
+X"80e73983",
+X"e3901333",
+X"5480d272",
+X"3473822a",
+X"70810651",
+X"5180cf53",
+X"70843880",
+X"d7537281",
+X"1334a00b",
+X"82133473",
+X"83065170",
+X"812e9e38",
+X"70812488",
+X"3870802e",
+X"8f389f39",
+X"70822e92",
+X"3870832e",
+X"92389339",
+X"80d8558e",
+X"3980d355",
+X"893980cd",
+X"55843980",
+X"c4557483",
+X"133480c4",
+X"0b841334",
+X"800b8513",
+X"34863d0d",
+X"04fe3d0d",
+X"80fc8008",
+X"70337081",
+X"ff067084",
+X"2a813281",
+X"06555152",
+X"5371802e",
+X"8c38a873",
+X"3480fc80",
+X"0851b871",
+X"347183e0",
+X"800c843d",
+X"0d04fe3d",
+X"0d80fc80",
+X"08703370",
+X"81ff0670",
+X"852a8132",
+X"81065551",
+X"52537180",
+X"2e8c3898",
+X"733480fc",
+X"800851b8",
+X"71347183",
+X"e0800c84",
+X"3d0d0480",
+X"3d0d80fb",
+X"fc085193",
+X"713480fc",
+X"880851ff",
+X"7134823d",
+X"0d04fe3d",
+X"0d029305",
+X"3380fbfc",
+X"08535380",
+X"72348a51",
+X"d3be3fd3",
+X"3f80fc8c",
+X"085280f8",
+X"723480fc",
+X"a4085280",
+X"7234fa13",
+X"80fcac08",
+X"53537272",
+X"3480fc94",
+X"08528072",
+X"3480fc9c",
+X"08527272",
+X"3480fc80",
+X"08528072",
+X"3480fc80",
+X"0852b872",
+X"34843d0d",
+X"04ff3d0d",
+X"028f0533",
+X"80fc8408",
+X"52527171",
+X"34fe9e3f",
+X"83e08008",
+X"802ef638",
+X"833d0d04",
+X"803d0d84",
+X"39dcb03f",
+X"feb83f83",
+X"e0800880",
+X"2ef33880",
+X"fc840870",
+X"337081ff",
+X"0683e080",
+X"0c515182",
+X"3d0d0480",
+X"3d0d80fb",
+X"fc0851a3",
+X"713480fc",
+X"880851ff",
+X"713480fc",
+X"800851a8",
+X"713480fc",
+X"800851b8",
+X"7134823d",
+X"0d04803d",
+X"0d80fbfc",
+X"08703370",
+X"81c00670",
+X"30708025",
+X"83e0800c",
+X"51515151",
+X"823d0d04",
+X"ff3d0d80",
+X"fc800870",
+X"337081ff",
+X"0670832a",
+X"81327081",
+X"06515151",
+X"52527080",
+X"2ee538b0",
+X"723480fc",
+X"800851b8",
+X"7134833d",
+X"0d04803d",
+X"0d80fcb8",
+X"08700881",
+X"0683e080",
+X"0c51823d",
+X"0d04fd3d",
+X"0d757754",
+X"54807325",
+X"94387370",
+X"81055533",
+X"5280fb88",
+X"51859d3f",
+X"ff1353e9",
+X"39853d0d",
+X"04f63d0d",
+X"7c7e6062",
+X"5a5d5b56",
+X"80598155",
+X"8539747a",
+X"29557452",
+X"7551b588",
+X"3f83e080",
+X"087a27ee",
+X"3874802e",
+X"80dd3874",
+X"527551b4",
+X"f33f83e0",
+X"80087553",
+X"765254b5",
+X"9a3f83e0",
+X"80087a53",
+X"755256b4",
+X"db3f83e0",
+X"80087930",
+X"707b079f",
+X"2a707780",
+X"24075151",
+X"54557287",
+X"3883e080",
+X"08c53876",
+X"8118b016",
+X"55585889",
+X"74258b38",
+X"b714537a",
+X"853880d7",
+X"14537278",
+X"34811959",
+X"ff9f3980",
+X"77348c3d",
+X"0d04f73d",
+X"0d7b7d7f",
+X"62029005",
+X"bb053357",
+X"59565a5a",
+X"b0587283",
+X"38a05875",
+X"70708105",
+X"52337159",
+X"54559039",
+X"8074258e",
+X"38ff1477",
+X"70810559",
+X"33545472",
+X"ef3873ff",
+X"15555380",
+X"73258938",
+X"77527951",
+X"782def39",
+X"75337557",
+X"5372802e",
+X"90387252",
+X"7951782d",
+X"75708105",
+X"573353ed",
+X"398b3d0d",
+X"04ee3d0d",
+X"64666969",
+X"70708105",
+X"52335b4a",
+X"5c5e5e76",
+X"802e82f9",
+X"3876a52e",
+X"09810682",
+X"e0388070",
+X"41677070",
+X"81055233",
+X"714a5957",
+X"5f76b02e",
+X"0981068c",
+X"38757081",
+X"05573376",
+X"4857815f",
+X"d0175675",
+X"892680da",
+X"3876675c",
+X"59805c93",
+X"39778a24",
+X"80c3387b",
+X"8a29187b",
+X"7081055d",
+X"335a5cd0",
+X"197081ff",
+X"06585889",
+X"7727a438",
+X"ff9f1970",
+X"81ff06ff",
+X"a91b5a51",
+X"56857627",
+X"9238ffbf",
+X"197081ff",
+X"06515675",
+X"85268a38",
+X"c9195877",
+X"8025ffb9",
+X"387a477b",
+X"407881ff",
+X"06577680",
+X"e42e80e5",
+X"387680e4",
+X"24a73876",
+X"80d82e81",
+X"86387680",
+X"d8249038",
+X"76802e81",
+X"cc3876a5",
+X"2e81b638",
+X"81b93976",
+X"80e32e81",
+X"8c3881af",
+X"397680f5",
+X"2e9b3876",
+X"80f5248b",
+X"387680f3",
+X"2e818138",
+X"81993976",
+X"80f82e80",
+X"ca38818f",
+X"39913d70",
+X"55578053",
+X"8a527984",
+X"1b710853",
+X"5b56fc81",
+X"3f7655ab",
+X"3979841b",
+X"7108943d",
+X"705b5b52",
+X"5b567580",
+X"258c3875",
+X"3056ad78",
+X"340280c1",
+X"05577654",
+X"80538a52",
+X"7551fbd5",
+X"3f77557e",
+X"54b83991",
+X"3d705577",
+X"80d83270",
+X"30708025",
+X"56515856",
+X"90527984",
+X"1b710853",
+X"5b57fbb1",
+X"3f7555db",
+X"3979841b",
+X"83123354",
+X"5b569839",
+X"79841b71",
+X"08575b56",
+X"80547f53",
+X"7c527d51",
+X"fc9c3f87",
+X"3976527d",
+X"517c2d66",
+X"70335881",
+X"0547fd83",
+X"39943d0d",
+X"047283e0",
+X"900c7183",
+X"e0940c04",
+X"fb3d0d88",
+X"3d707084",
+X"05520857",
+X"54755383",
+X"e0900852",
+X"83e09408",
+X"51fcc63f",
+X"873d0d04",
+X"ff3d0d73",
+X"70085351",
+X"02930533",
+X"72347008",
+X"8105710c",
+X"833d0d04",
+X"fc3d0d87",
+X"3d881155",
+X"785480c0",
+X"a85351fc",
+X"983f8052",
+X"873d51d0",
+X"3f863d0d",
+X"04fd3d0d",
+X"75705254",
+X"a5843f83",
+X"e0800814",
+X"5372742e",
+X"9238ff13",
+X"70335353",
+X"71af2e09",
+X"8106ee38",
+X"81135372",
+X"83e0800c",
+X"853d0d04",
+X"fd3d0d75",
+X"77705354",
+X"54c73f83",
+X"e0800873",
+X"2ea13883",
+X"e0800873",
+X"3152ff12",
+X"5271ff2e",
+X"8f387270",
+X"81055433",
+X"74708105",
+X"5634eb39",
+X"ff145480",
+X"7434853d",
+X"0d04803d",
+X"0d7251ff",
+X"903f823d",
+X"0d047183",
+X"e0800c04",
+X"803d0d72",
+X"51807134",
+X"810bbc12",
+X"0c800b80",
+X"c0120c82",
+X"3d0d0480",
+X"0b83e5bc",
+X"08248a38",
+X"a5ee3fff",
+X"0b83e5bc",
+X"0c800b83",
+X"e0800c04",
+X"ff3d0d73",
+X"5283e398",
+X"08722e8d",
+X"38d93f71",
+X"5197853f",
+X"7183e398",
+X"0c833d0d",
+X"04f43d0d",
+X"7e60625c",
+X"5a558154",
+X"bc150881",
+X"91387451",
+X"cf3f7958",
+X"807a2580",
+X"f73883e5",
+X"ec087089",
+X"2a5783ff",
+X"06788480",
+X"72315656",
+X"57737825",
+X"83387355",
+X"7583e5bc",
+X"082e8438",
+X"ff893f83",
+X"e5bc0880",
+X"25a63875",
+X"892b5199",
+X"f13f83e5",
+X"ec088f3d",
+X"fc11555c",
+X"548152f8",
+X"1b5197d6",
+X"3f761483",
+X"e5ec0c75",
+X"83e5bc0c",
+X"74537652",
+X"7851a49f",
+X"3f83e080",
+X"0883e5ec",
+X"081683e5",
+X"ec0c7876",
+X"31761b5b",
+X"59567780",
+X"24ff8b38",
+X"617a710c",
+X"54755475",
+X"802e8338",
+X"81547383",
+X"e0800c8e",
+X"3d0d04fc",
+X"3d0dfe9b",
+X"3f7651fe",
+X"af3f863d",
+X"fc055302",
+X"a2052252",
+X"775196f6",
+X"3f79863d",
+X"22710c54",
+X"83e08008",
+X"5483e080",
+X"08802e83",
+X"38815473",
+X"83e0800c",
+X"863d0d04",
+X"fd3d0d76",
+X"83e5bc08",
+X"53538072",
+X"24893871",
+X"732e8438",
+X"fdd13f75",
+X"51fde53f",
+X"725198be",
+X"3f735273",
+X"802e8338",
+X"81527183",
+X"e0800c85",
+X"3d0d0480",
+X"3d0d7280",
+X"c0110883",
+X"e0800c51",
+X"823d0d04",
+X"803d0d72",
+X"bc110883",
+X"e0800c51",
+X"823d0d04",
+X"80c40b83",
+X"e0800c04",
+X"fd3d0d75",
+X"77715470",
+X"535553a0",
+X"dd3f82c8",
+X"1308bc15",
+X"0c82c013",
+X"0880c015",
+X"0cfcec3f",
+X"73519498",
+X"3f7383e3",
+X"980c83e0",
+X"80085383",
+X"e0800880",
+X"2e833881",
+X"537283e0",
+X"800c853d",
+X"0d04fd3d",
+X"0d757755",
+X"53fcc03f",
+X"72802ea5",
+X"38bc1308",
+X"5273519f",
+X"e73f83e0",
+X"80088f38",
+X"77527251",
+X"ff9a3f83",
+X"e0800853",
+X"8a3982cc",
+X"130853d8",
+X"39815372",
+X"83e0800c",
+X"853d0d04",
+X"fe3d0dff",
+X"0b83e5bc",
+X"0c7483e3",
+X"9c0c7583",
+X"e5b80ca0",
+X"d43f83e0",
+X"800881ff",
+X"06528153",
+X"71993883",
+X"e5d4518f",
+X"903f83e0",
+X"80085283",
+X"e0800880",
+X"2e833872",
+X"52715372",
+X"83e0800c",
+X"843d0d04",
+X"fa3d0d78",
+X"7a82c412",
+X"0882c412",
+X"08707224",
+X"59565657",
+X"5773732e",
+X"09810691",
+X"3880c016",
+X"5280c017",
+X"519dd83f",
+X"83e08008",
+X"557483e0",
+X"800c883d",
+X"0d04f63d",
+X"0d7c5b80",
+X"7b715c54",
+X"577a772e",
+X"8c38811a",
+X"82cc1408",
+X"545a72f6",
+X"38805980",
+X"d9397a54",
+X"81578070",
+X"7b7b315a",
+X"5755ff18",
+X"53747325",
+X"80c13882",
+X"cc140852",
+X"7351ff8c",
+X"3f800b83",
+X"e0800825",
+X"a13882cc",
+X"140882cc",
+X"110882cc",
+X"160c7482",
+X"cc120c53",
+X"75802e86",
+X"387282cc",
+X"170c7254",
+X"80577382",
+X"cc150881",
+X"17575556",
+X"ffb83981",
+X"1959800b",
+X"ff1b5454",
+X"78732583",
+X"38815476",
+X"81327075",
+X"06515372",
+X"ff90388c",
+X"3d0d04f7",
+X"3d0d7b7d",
+X"5a5a82d0",
+X"5283e5b8",
+X"0851a894",
+X"3f83e080",
+X"0857f9e3",
+X"3f795283",
+X"e5c05196",
+X"c73f83e0",
+X"80085380",
+X"5483e080",
+X"08742e09",
+X"81068283",
+X"3883e39c",
+X"080b0b80",
+X"fad05370",
+X"52559d96",
+X"3f0b0b80",
+X"fad05280",
+X"c015519d",
+X"893f74bc",
+X"160c7282",
+X"c0160c81",
+X"0b82c416",
+X"0c810b82",
+X"c8160cff",
+X"17735757",
+X"81973983",
+X"e3a83370",
+X"822a7081",
+X"06515454",
+X"72818638",
+X"73812a81",
+X"06587780",
+X"fc387680",
+X"2e819038",
+X"82d015ff",
+X"1875842a",
+X"810682c4",
+X"130c83e3",
+X"a8338106",
+X"82c8130c",
+X"7b547153",
+X"58569caa",
+X"3f75519c",
+X"c13f83e0",
+X"80081653",
+X"af737081",
+X"05553472",
+X"bc170c83",
+X"e3a95272",
+X"519c8b3f",
+X"83e3a008",
+X"82c0170c",
+X"83e3b652",
+X"83901551",
+X"9bf83f77",
+X"82cc170c",
+X"78802e8d",
+X"38755178",
+X"2d83e080",
+X"08802e8d",
+X"3874802e",
+X"86387582",
+X"cc160c75",
+X"5583e3a0",
+X"5283e5c0",
+X"5195e73f",
+X"83e08008",
+X"8a3883e3",
+X"a9335372",
+X"fed13880",
+X"0b82cc17",
+X"0c78802e",
+X"893883e3",
+X"9c0851fc",
+X"b93f83e3",
+X"9c085473",
+X"83e0800c",
+X"8b3d0d04",
+X"ff3d0d80",
+X"527351fd",
+X"b63f833d",
+X"0d04f03d",
+X"0d627052",
+X"54f6923f",
+X"83e08008",
+X"7453873d",
+X"70535555",
+X"f6b23ff7",
+X"923f7351",
+X"d33f6353",
+X"745283e0",
+X"800851fa",
+X"b93f923d",
+X"0d047183",
+X"e0800c04",
+X"80c01283",
+X"e0800c04",
+X"803d0d72",
+X"82c01108",
+X"83e0800c",
+X"51823d0d",
+X"04803d0d",
+X"7282cc11",
+X"0883e080",
+X"0c51823d",
+X"0d04803d",
+X"0d7282c4",
+X"110883e0",
+X"800c5182",
+X"3d0d04f6",
+X"3d0d7c83",
+X"e0980859",
+X"59817927",
+X"82a93878",
+X"88190827",
+X"82a13877",
+X"33567582",
+X"2e819b38",
+X"75822489",
+X"3875812e",
+X"8d38828b",
+X"3975832e",
+X"81b73882",
+X"82397883",
+X"ffff0670",
+X"812a1170",
+X"83ffff06",
+X"7083ff06",
+X"71892a90",
+X"3d5f525a",
+X"51515576",
+X"83ff2e8e",
+X"38825476",
+X"538c1808",
+X"15527951",
+X"a9397554",
+X"76538c18",
+X"08155279",
+X"519ace3f",
+X"83e08008",
+X"81bd3875",
+X"5483e080",
+X"08538c18",
+X"08158105",
+X"528c3dfd",
+X"05519ab1",
+X"3f83e080",
+X"0881a038",
+X"02a90533",
+X"8c3d3371",
+X"882b077a",
+X"81067184",
+X"2a535758",
+X"56748638",
+X"769fff06",
+X"56755581",
+X"80397554",
+X"781083fe",
+X"06537888",
+X"2a8c1908",
+X"05528c3d",
+X"fc055199",
+X"f03f83e0",
+X"800880df",
+X"3802a905",
+X"338c3d33",
+X"71882b07",
+X"565780d1",
+X"39845478",
+X"822b83fc",
+X"06537887",
+X"2a8c1908",
+X"05528c3d",
+X"fc055199",
+X"c03f83e0",
+X"8008b038",
+X"02ab0533",
+X"028405aa",
+X"05337198",
+X"2b71902b",
+X"07028c05",
+X"a9053370",
+X"882b7207",
+X"903d3371",
+X"80fffffe",
+X"80060751",
+X"52535758",
+X"56833981",
+X"557483e0",
+X"800c8c3d",
+X"0d04fb3d",
+X"0d83e098",
+X"08fe1988",
+X"1208fe05",
+X"55565480",
+X"56747327",
+X"8d388214",
+X"33757129",
+X"94160805",
+X"57537583",
+X"e0800c87",
+X"3d0d04fc",
+X"3d0d7683",
+X"e0980855",
+X"55807523",
+X"88150853",
+X"72812e88",
+X"38881408",
+X"73268538",
+X"8152b239",
+X"72903873",
+X"33527183",
+X"2e098106",
+X"85389014",
+X"0853728c",
+X"160c7280",
+X"2e8d3872",
+X"51ff933f",
+X"83e08008",
+X"52853990",
+X"14085271",
+X"90160c80",
+X"527183e0",
+X"800c863d",
+X"0d04fa3d",
+X"0d7883e0",
+X"98087122",
+X"81057083",
+X"ffff0657",
+X"54575573",
+X"802e8838",
+X"90150853",
+X"72863883",
+X"5280e739",
+X"738f0652",
+X"7180da38",
+X"81139016",
+X"0c8c1508",
+X"53729038",
+X"830b8417",
+X"22575273",
+X"762780c6",
+X"38bf3982",
+X"1633ff05",
+X"74842a06",
+X"5271b238",
+X"7251fbdb",
+X"3f815271",
+X"83e08008",
+X"27a83883",
+X"5283e080",
+X"08881708",
+X"279c3883",
+X"e080088c",
+X"160c83e0",
+X"800851fd",
+X"f93f83e0",
+X"80089016",
+X"0c737523",
+X"80527183",
+X"e0800c88",
+X"3d0d04f2",
+X"3d0d6062",
+X"64585d5b",
+X"75335574",
+X"a02e0981",
+X"06883881",
+X"16704456",
+X"ef396270",
+X"33565674",
+X"af2e0981",
+X"06843881",
+X"1643800b",
+X"881c0c62",
+X"70335155",
+X"74a02691",
+X"387a51fd",
+X"d23f83e0",
+X"80085680",
+X"7c3483a8",
+X"39933d84",
+X"1c087058",
+X"5a5f8a55",
+X"a0767081",
+X"055834ff",
+X"155574ff",
+X"2e098106",
+X"ef388070",
+X"595d887f",
+X"085f5a7c",
+X"811e7081",
+X"ff066013",
+X"703370af",
+X"327030a0",
+X"73277180",
+X"25075151",
+X"525b535f",
+X"57557480",
+X"d83876ae",
+X"2e098106",
+X"83388155",
+X"777a2775",
+X"07557480",
+X"2e9f3879",
+X"88327030",
+X"78ae3270",
+X"30707307",
+X"9f2a5351",
+X"57515675",
+X"ac388858",
+X"8b5affab",
+X"39ff9f17",
+X"55749926",
+X"8938e017",
+X"7081ff06",
+X"58557781",
+X"197081ff",
+X"06721c53",
+X"5a575576",
+X"7534ff87",
+X"397c1e7f",
+X"0c805576",
+X"a0268338",
+X"8155748b",
+X"1a347a51",
+X"fc913f83",
+X"e0800880",
+X"f538a054",
+X"7a227085",
+X"2b83e006",
+X"5455901b",
+X"08527b51",
+X"94c73f83",
+X"e0800857",
+X"83e08008",
+X"8182387b",
+X"33557480",
+X"2e80f538",
+X"8b1c3370",
+X"832a7081",
+X"06515656",
+X"74b4388b",
+X"7c841d08",
+X"83e08008",
+X"595b5b58",
+X"ff185877",
+X"ff2e9a38",
+X"79708105",
+X"5b337970",
+X"81055b33",
+X"71713152",
+X"56567580",
+X"2ee23886",
+X"3975802e",
+X"bc387a51",
+X"fbf43fff",
+X"863983e0",
+X"80085683",
+X"e0800880",
+X"2ea93883",
+X"e0800883",
+X"2e098106",
+X"80de3884",
+X"1b088b11",
+X"33515574",
+X"80d23884",
+X"5680cd39",
+X"8356ec39",
+X"815680c4",
+X"39765684",
+X"1b088b11",
+X"33515574",
+X"b7388b1c",
+X"3370842a",
+X"70810651",
+X"56577480",
+X"2ed53895",
+X"1c33941d",
+X"3371982b",
+X"71902b07",
+X"9b1f337f",
+X"9a053371",
+X"882b0772",
+X"077f8805",
+X"0c5a5856",
+X"58fcda39",
+X"7583e080",
+X"0c903d0d",
+X"04f83d0d",
+X"7a7c5957",
+X"825483fe",
+X"53775276",
+X"5192d63f",
+X"835683e0",
+X"800880ec",
+X"38811733",
+X"77337188",
+X"2b075656",
+X"82567482",
+X"d4d52e09",
+X"810680d4",
+X"387554b6",
+X"53775276",
+X"5192aa3f",
+X"83e08008",
+X"98388117",
+X"33773371",
+X"882b0783",
+X"e0800852",
+X"56567481",
+X"82c62eac",
+X"38825480",
+X"d2537752",
+X"76519281",
+X"3f83e080",
+X"08983881",
+X"17337733",
+X"71882b07",
+X"83e08008",
+X"52565674",
+X"8182c62e",
+X"83388156",
+X"7583e080",
+X"0c8a3d0d",
+X"04ec3d0d",
+X"6659800b",
+X"83e0980c",
+X"78567880",
+X"2e83e838",
+X"919b3f83",
+X"e0800881",
+X"06558256",
+X"7483d838",
+X"7475538e",
+X"3d705358",
+X"58fec23f",
+X"83e08008",
+X"81ff0656",
+X"75812e09",
+X"810680d4",
+X"38905483",
+X"be537452",
+X"7651918d",
+X"3f83e080",
+X"0880c938",
+X"8e3d3355",
+X"74802e80",
+X"c93802bb",
+X"05330284",
+X"05ba0533",
+X"71982b71",
+X"902b0702",
+X"8c05b905",
+X"3370882b",
+X"7207943d",
+X"33710770",
+X"587c5754",
+X"525d5759",
+X"56fde63f",
+X"83e08008",
+X"81ff0656",
+X"75832e09",
+X"81068638",
+X"815682db",
+X"3975802e",
+X"86388756",
+X"82d139a4",
+X"548d5377",
+X"52765190",
+X"a43f8156",
+X"83e08008",
+X"82bd3802",
+X"ba053302",
+X"8405b905",
+X"3371882b",
+X"07585c76",
+X"ab380280",
+X"ca053302",
+X"840580c9",
+X"05337198",
+X"2b71902b",
+X"07963d33",
+X"70882b72",
+X"07029405",
+X"80c70533",
+X"71075452",
+X"5d575856",
+X"02b30533",
+X"77712902",
+X"8805b205",
+X"33028c05",
+X"b1053371",
+X"882b0770",
+X"1c708c1f",
+X"0c5e5957",
+X"585c8d3d",
+X"33821a34",
+X"02b50533",
+X"8f3d3371",
+X"882b0759",
+X"5b77841a",
+X"2302b705",
+X"33028405",
+X"b6053371",
+X"882b0756",
+X"5b74ab38",
+X"0280c605",
+X"33028405",
+X"80c50533",
+X"71982b71",
+X"902b0795",
+X"3d337088",
+X"2b720702",
+X"940580c3",
+X"05337107",
+X"51525357",
+X"5d5b7476",
+X"31773178",
+X"842a8f3d",
+X"33547171",
+X"31535656",
+X"97f63f83",
+X"e0800882",
+X"0570881b",
+X"0c709ff6",
+X"26810557",
+X"5583fff6",
+X"75278338",
+X"83567579",
+X"3475832e",
+X"098106af",
+X"380280d2",
+X"05330284",
+X"0580d105",
+X"3371982b",
+X"71902b07",
+X"983d3370",
+X"882b7207",
+X"02940580",
+X"cf053371",
+X"07901f0c",
+X"525d5759",
+X"56863976",
+X"1a901a0c",
+X"8419228c",
+X"1a081871",
+X"842a0594",
+X"1b0c5c80",
+X"0b811a34",
+X"7883e098",
+X"0c805675",
+X"83e0800c",
+X"963d0d04",
+X"e93d0d83",
+X"e0980856",
+X"86547580",
+X"2e81a638",
+X"800b8117",
+X"34993de0",
+X"11466a54",
+X"c01153ec",
+X"0551f6cf",
+X"3f83e080",
+X"085483e0",
+X"80088185",
+X"38893d33",
+X"5473802e",
+X"933802ab",
+X"05337084",
+X"2a708106",
+X"51555573",
+X"802e8638",
+X"835480e5",
+X"3902b505",
+X"338f3d33",
+X"71982b71",
+X"902b0702",
+X"8c05bb05",
+X"33029005",
+X"ba053371",
+X"882b0772",
+X"07a01b0c",
+X"029005bf",
+X"05330294",
+X"05be0533",
+X"71982b71",
+X"902b0702",
+X"9c05bd05",
+X"3370882b",
+X"7207993d",
+X"3371077f",
+X"9c050c52",
+X"83e08008",
+X"981f0c56",
+X"5a525253",
+X"57595781",
+X"0b811734",
+X"83e08008",
+X"547383e0",
+X"800c993d",
+X"0d04f53d",
+X"0d7d6002",
+X"8805ba05",
+X"227283e0",
+X"98085b5d",
+X"5a5c5c80",
+X"7b238656",
+X"76802e81",
+X"e0388117",
+X"33810655",
+X"85567480",
+X"2e81d238",
+X"9c170898",
+X"18083155",
+X"74782787",
+X"387483ff",
+X"ff065877",
+X"802e81ae",
+X"38981708",
+X"7083ff06",
+X"56567480",
+X"ca388217",
+X"33ff0576",
+X"892a0670",
+X"81ff065a",
+X"5578a038",
+X"758738a0",
+X"1708558d",
+X"39a41708",
+X"51efe03f",
+X"83e08008",
+X"55817527",
+X"80f83874",
+X"a4180ca4",
+X"170851f2",
+X"8d3f83e0",
+X"8008802e",
+X"80e43883",
+X"e0800819",
+X"a8180c98",
+X"170883ff",
+X"06848071",
+X"317083ff",
+X"ff065851",
+X"55777627",
+X"83387756",
+X"75549817",
+X"0883ff06",
+X"53a81708",
+X"5279557b",
+X"83387b55",
+X"74518ac9",
+X"3f83e080",
+X"08a43898",
+X"17081698",
+X"180c751a",
+X"78773170",
+X"83ffff06",
+X"7d227905",
+X"525a565a",
+X"747b23fe",
+X"ce398056",
+X"8839800b",
+X"81183481",
+X"567583e0",
+X"800c8d3d",
+X"0d04fa3d",
+X"0d7883e0",
+X"98085556",
+X"86557380",
+X"2e81dc38",
+X"81143381",
+X"06538555",
+X"72802e81",
+X"ce389c14",
+X"08537276",
+X"27833872",
+X"56981408",
+X"57800b98",
+X"150c7580",
+X"2e81a938",
+X"82143370",
+X"892b5653",
+X"76802eb5",
+X"387452ff",
+X"165192e4",
+X"3f83e080",
+X"08ff1876",
+X"54705358",
+X"5392d53f",
+X"83e08008",
+X"73269638",
+X"74307078",
+X"06709817",
+X"0c777131",
+X"a4170852",
+X"58515389",
+X"39a01408",
+X"70a4160c",
+X"53747627",
+X"b4387251",
+X"edc13f83",
+X"e0800853",
+X"810b83e0",
+X"80082780",
+X"cb3883e0",
+X"80088815",
+X"082780c0",
+X"3883e080",
+X"08a4150c",
+X"98140815",
+X"98150c75",
+X"753156c9",
+X"39981408",
+X"16709816",
+X"0c735256",
+X"efc83f83",
+X"e0800880",
+X"2e963882",
+X"1433ff05",
+X"76892a06",
+X"83e08008",
+X"05a8150c",
+X"80558839",
+X"800b8115",
+X"34815574",
+X"83e0800c",
+X"883d0d04",
+X"ee3d0d64",
+X"56865583",
+X"e0980880",
+X"2e80f638",
+X"943df411",
+X"84180c66",
+X"54d40552",
+X"7551f197",
+X"3f83e080",
+X"085583e0",
+X"800880cf",
+X"38893d33",
+X"5473802e",
+X"bc3802ab",
+X"05337084",
+X"2a708106",
+X"51555584",
+X"5573802e",
+X"bc3802b5",
+X"05338f3d",
+X"3371982b",
+X"71902b07",
+X"028c05bb",
+X"05330290",
+X"05ba0533",
+X"71882b07",
+X"7207881b",
+X"0c535759",
+X"577551ee",
+X"d23f83e0",
+X"80085574",
+X"832e0981",
+X"06833884",
+X"557483e0",
+X"800c943d",
+X"0d04e43d",
+X"0d6ea13d",
+X"08405d86",
+X"5683e098",
+X"08802e84",
+X"91389e3d",
+X"f405841e",
+X"0c7e9838",
+X"7c51ee97",
+X"3f83e080",
+X"085683fa",
+X"39814181",
+X"f6398341",
+X"81f13993",
+X"3d7f9605",
+X"4159807f",
+X"8295055f",
+X"56756081",
+X"ff053483",
+X"41901d08",
+X"762e81d3",
+X"38a0547c",
+X"2270852b",
+X"83e00654",
+X"58901d08",
+X"52785186",
+X"a43f83e0",
+X"80084183",
+X"e08008ff",
+X"b8387833",
+X"5c7b802e",
+X"ffb4388b",
+X"193370bf",
+X"06718106",
+X"52435574",
+X"802e80de",
+X"387b81bf",
+X"0655748f",
+X"2480d338",
+X"9a193355",
+X"7480cb38",
+X"f31e7058",
+X"5e815675",
+X"8b2e0981",
+X"0685388e",
+X"568b3975",
+X"9a2e0981",
+X"0683389c",
+X"56751970",
+X"70810552",
+X"33713381",
+X"1a821a5f",
+X"5b525b55",
+X"74863879",
+X"77348539",
+X"80df7734",
+X"777b5757",
+X"7aa02e09",
+X"8106c038",
+X"81567b81",
+X"e5327030",
+X"709f2a51",
+X"51557bae",
+X"2e933874",
+X"802e8e38",
+X"61832a70",
+X"81065155",
+X"74802e97",
+X"387c51ed",
+X"813f83e0",
+X"80084183",
+X"e0800887",
+X"38901d08",
+X"feaf3880",
+X"60347580",
+X"2e88387d",
+X"527f5183",
+X"b13f6080",
+X"2e863880",
+X"0b901e0c",
+X"60566083",
+X"2e098106",
+X"8838800b",
+X"901e0c85",
+X"396081d2",
+X"38891f57",
+X"901d0880",
+X"2e81a838",
+X"80567519",
+X"70335155",
+X"74a02ea0",
+X"3874852e",
+X"09810684",
+X"3881e555",
+X"74777081",
+X"05593481",
+X"167081ff",
+X"06575587",
+X"7627d738",
+X"88193355",
+X"74a02ea9",
+X"38ae7770",
+X"81055934",
+X"88567519",
+X"70335155",
+X"74a02e95",
+X"38747770",
+X"81055934",
+X"81167081",
+X"ff065755",
+X"8a7627e2",
+X"388b1933",
+X"7f880534",
+X"9f19339e",
+X"1a337198",
+X"2b71902b",
+X"079d1c33",
+X"70882b72",
+X"079c1e33",
+X"7107640c",
+X"52991d33",
+X"981e3371",
+X"882b0753",
+X"51535759",
+X"56747f84",
+X"05239719",
+X"33961a33",
+X"71882b07",
+X"5656747f",
+X"86052380",
+X"77347c51",
+X"eb883f83",
+X"e0800856",
+X"83e08008",
+X"832e0981",
+X"06883880",
+X"0b901e0c",
+X"8056961f",
+X"3355748a",
+X"38891f52",
+X"961f5181",
+X"b13f7583",
+X"e0800c9e",
+X"3d0d04fd",
+X"3d0d7577",
+X"53547333",
+X"51708938",
+X"71335170",
+X"802ea138",
+X"73337233",
+X"52537271",
+X"278538ff",
+X"51943970",
+X"73278538",
+X"81518b39",
+X"81148113",
+X"5354d339",
+X"80517083",
+X"e0800c85",
+X"3d0d04fd",
+X"3d0d7577",
+X"54547233",
+X"7081ff06",
+X"52527080",
+X"2ea33871",
+X"81ff0681",
+X"14ffbf12",
+X"53545270",
+X"99268938",
+X"a0127081",
+X"ff065351",
+X"71747081",
+X"055634d2",
+X"39807434",
+X"853d0d04",
+X"ffbd3d0d",
+X"80c63d08",
+X"52a53d70",
+X"5254ffb3",
+X"3f80c73d",
+X"0852853d",
+X"705253ff",
+X"a63f7252",
+X"7351fedf",
+X"3f80c53d",
+X"0d04fe3d",
+X"0d747653",
+X"53717081",
+X"05533351",
+X"70737081",
+X"05553470",
+X"f038843d",
+X"0d04fe3d",
+X"0d745280",
+X"72335253",
+X"70732e8d",
+X"38811281",
+X"14713353",
+X"545270f5",
+X"387283e0",
+X"800c843d",
+X"0d04fc3d",
+X"0d765574",
+X"83e68008",
+X"2eaf3880",
+X"53745187",
+X"cd3f83e0",
+X"800881ff",
+X"06ff1470",
+X"81ff0672",
+X"30709f2a",
+X"51525553",
+X"5472802e",
+X"843871dd",
+X"3873fe38",
+X"7483e680",
+X"0c863d0d",
+X"04ff3d0d",
+X"ff0b83e6",
+X"800c84af",
+X"3f815187",
+X"913f83e0",
+X"800881ff",
+X"065271ee",
+X"3881d63f",
+X"7183e080",
+X"0c833d0d",
+X"04fc3d0d",
+X"76028405",
+X"a2052202",
+X"8805a605",
+X"227a5455",
+X"5555ff82",
+X"3f72802e",
+X"a03883e6",
+X"94143375",
+X"70810557",
+X"34811470",
+X"83ffff06",
+X"ff157083",
+X"ffff0656",
+X"525552dd",
+X"39800b83",
+X"e0800c86",
+X"3d0d04fc",
+X"3d0d7678",
+X"7a115653",
+X"55805371",
+X"742e9338",
+X"72155170",
+X"3383e694",
+X"13348112",
+X"81145452",
+X"ea39800b",
+X"83e0800c",
+X"863d0d04",
+X"fd3d0d90",
+X"5483e680",
+X"08518780",
+X"3f83e080",
+X"0881ff06",
+X"ff157130",
+X"71307073",
+X"079f2a72",
+X"9f2a0652",
+X"55525553",
+X"72db3885",
+X"3d0d04ff",
+X"3d0d83e6",
+X"8c081083",
+X"e6840807",
+X"80fcbc08",
+X"52710c83",
+X"3d0d0480",
+X"0b83e68c",
+X"0ce13f04",
+X"810b83e6",
+X"8c0cd83f",
+X"04ed3f04",
+X"7183e688",
+X"0c04803d",
+X"0d8051f4",
+X"3f810b83",
+X"e68c0c81",
+X"0b83e684",
+X"0cffb83f",
+X"823d0d04",
+X"803d0d72",
+X"30707407",
+X"802583e6",
+X"840c51ff",
+X"a23f823d",
+X"0d04fe3d",
+X"0d029305",
+X"3380fcc0",
+X"0854730c",
+X"80fcbc08",
+X"52710870",
+X"81065151",
+X"70f73872",
+X"087081ff",
+X"0683e080",
+X"0c51843d",
+X"0d04803d",
+X"0d81ff51",
+X"cd3f83e0",
+X"800881ff",
+X"0683e080",
+X"0c823d0d",
+X"04ff3d0d",
+X"74902b74",
+X"0780fcb0",
+X"0852710c",
+X"833d0d04",
+X"04fb3d0d",
+X"78028405",
+X"9f053370",
+X"982b5557",
+X"55728025",
+X"9b387580",
+X"ff065680",
+X"5280f751",
+X"e03f83e0",
+X"800881ff",
+X"06547381",
+X"2680ff38",
+X"8051fee0",
+X"3fff9f3f",
+X"8151fed8",
+X"3fff973f",
+X"7551fee6",
+X"3f74982a",
+X"51fedf3f",
+X"74902a70",
+X"81ff0652",
+X"53fed33f",
+X"74882a70",
+X"81ff0652",
+X"53fec73f",
+X"7481ff06",
+X"51febf3f",
+X"81557580",
+X"c02e0981",
+X"06863881",
+X"95558d39",
+X"7580c82e",
+X"09810684",
+X"38818755",
+X"7451fe9e",
+X"3f8a55fe",
+X"c53f83e0",
+X"800881ff",
+X"0670982b",
+X"54547280",
+X"258c38ff",
+X"157081ff",
+X"06565374",
+X"e2387383",
+X"e0800c87",
+X"3d0d04fa",
+X"3d0dfdbe",
+X"3f8051fd",
+X"d33f8a54",
+X"fe903fff",
+X"147081ff",
+X"06555373",
+X"f3387374",
+X"535580c0",
+X"51fea63f",
+X"83e08008",
+X"81ff0654",
+X"73812e09",
+X"810682a1",
+X"3883aa52",
+X"80c851fe",
+X"8c3f83e0",
+X"800881ff",
+X"06537281",
+X"2e098106",
+X"81a93874",
+X"54873d74",
+X"115456fd",
+X"c53f83e0",
+X"80087334",
+X"81147081",
+X"ff065553",
+X"837427e5",
+X"38029a05",
+X"33537281",
+X"2e098106",
+X"81db3802",
+X"9b053353",
+X"80ce9054",
+X"7281aa2e",
+X"8e3881c9",
+X"3980e451",
+X"ff9fe53f",
+X"ff145473",
+X"802e81b9",
+X"38820a52",
+X"81e951fd",
+X"a43f83e0",
+X"800881ff",
+X"065372dd",
+X"38725280",
+X"fa51fd91",
+X"3f83e080",
+X"0881ff06",
+X"53728191",
+X"38725473",
+X"1653fcd2",
+X"3f83e080",
+X"08733481",
+X"147081ff",
+X"06555383",
+X"7427e838",
+X"873d3370",
+X"862a7081",
+X"06515454",
+X"8c557280",
+X"e4388455",
+X"80df3974",
+X"5281e951",
+X"fccb3f83",
+X"e0800881",
+X"ff065382",
+X"5581e956",
+X"81732786",
+X"38735580",
+X"c15680ce",
+X"90548b39",
+X"80e451ff",
+X"9ed63fff",
+X"14547380",
+X"2ea93880",
+X"527551fc",
+X"983f83e0",
+X"800881ff",
+X"065372e0",
+X"38848052",
+X"80d051fc",
+X"843f83e0",
+X"800881ff",
+X"06537280",
+X"2e833880",
+X"557483e6",
+X"90348051",
+X"fafe3ffb",
+X"bd3f883d",
+X"0d04fb3d",
+X"0d775480",
+X"0b83e690",
+X"3370832a",
+X"70810651",
+X"55575572",
+X"752e0981",
+X"06853873",
+X"892b5473",
+X"5280d151",
+X"fbbb3f83",
+X"e0800881",
+X"ff065372",
+X"bd3882b8",
+X"c054fafe",
+X"3f83e080",
+X"0881ff06",
+X"537281ff",
+X"2e098106",
+X"8938ff14",
+X"5473e738",
+X"9f397281",
+X"fe2e0981",
+X"06963883",
+X"ea945283",
+X"e69451fa",
+X"e83fface",
+X"3ffacb3f",
+X"83398155",
+X"8051fa80",
+X"3ffabf3f",
+X"7481ff06",
+X"83e0800c",
+X"873d0d04",
+X"fb3d0d77",
+X"83e69456",
+X"548151f9",
+X"e33f83e6",
+X"90337083",
+X"2a708106",
+X"51545672",
+X"85387389",
+X"2b547352",
+X"80d851fa",
+X"b43f83e0",
+X"800881ff",
+X"06537280",
+X"e53881ff",
+X"51f9cb3f",
+X"81fe51f9",
+X"c53f8480",
+X"53747081",
+X"05563351",
+X"f9b83fff",
+X"137083ff",
+X"ff065153",
+X"72eb3872",
+X"51f9a73f",
+X"7251f9a2",
+X"3ff9cb3f",
+X"83e08008",
+X"9f0653a7",
+X"88547285",
+X"2e8d389a",
+X"3980e451",
+X"ff9c8d3f",
+X"ff1454f9",
+X"ad3f83e0",
+X"800881ff",
+X"2e843873",
+X"e8388051",
+X"f8da3ff9",
+X"993f800b",
+X"83e0800c",
+X"873d0d04",
+X"83e08c08",
+X"0283e08c",
+X"0cfd3d0d",
+X"805383e0",
+X"8c088c05",
+X"085283e0",
+X"8c088805",
+X"085183d4",
+X"3f83e080",
+X"087083e0",
+X"800c5485",
+X"3d0d83e0",
+X"8c0c0483",
+X"e08c0802",
+X"83e08c0c",
+X"fd3d0d81",
+X"5383e08c",
+X"088c0508",
+X"5283e08c",
+X"08880508",
+X"5183a13f",
+X"83e08008",
+X"7083e080",
+X"0c54853d",
+X"0d83e08c",
+X"0c0483e0",
+X"8c080283",
+X"e08c0cf9",
+X"3d0d800b",
+X"83e08c08",
+X"fc050c83",
+X"e08c0888",
+X"05088025",
+X"b93883e0",
+X"8c088805",
+X"083083e0",
+X"8c088805",
+X"0c800b83",
+X"e08c08f4",
+X"050c83e0",
+X"8c08fc05",
+X"088a3881",
+X"0b83e08c",
+X"08f4050c",
+X"83e08c08",
+X"f4050883",
+X"e08c08fc",
+X"050c83e0",
+X"8c088c05",
+X"088025b9",
+X"3883e08c",
+X"088c0508",
+X"3083e08c",
+X"088c050c",
+X"800b83e0",
+X"8c08f005",
+X"0c83e08c",
+X"08fc0508",
+X"8a38810b",
+X"83e08c08",
+X"f0050c83",
+X"e08c08f0",
+X"050883e0",
+X"8c08fc05",
+X"0c805383",
+X"e08c088c",
+X"05085283",
+X"e08c0888",
+X"05085181",
+X"df3f83e0",
+X"80087083",
+X"e08c08f8",
+X"050c5483",
+X"e08c08fc",
+X"0508802e",
+X"903883e0",
+X"8c08f805",
+X"083083e0",
+X"8c08f805",
+X"0c83e08c",
+X"08f80508",
+X"7083e080",
+X"0c54893d",
+X"0d83e08c",
+X"0c0483e0",
+X"8c080283",
+X"e08c0cfb",
+X"3d0d800b",
+X"83e08c08",
+X"fc050c83",
+X"e08c0888",
+X"05088025",
+X"993883e0",
+X"8c088805",
+X"083083e0",
+X"8c088805",
+X"0c810b83",
+X"e08c08fc",
+X"050c83e0",
+X"8c088c05",
+X"08802590",
+X"3883e08c",
+X"088c0508",
+X"3083e08c",
+X"088c050c",
+X"815383e0",
+X"8c088c05",
+X"085283e0",
+X"8c088805",
+X"0851bd3f",
+X"83e08008",
+X"7083e08c",
+X"08f8050c",
+X"5483e08c",
+X"08fc0508",
+X"802e9038",
+X"83e08c08",
+X"f8050830",
+X"83e08c08",
+X"f8050c83",
+X"e08c08f8",
+X"05087083",
+X"e0800c54",
+X"873d0d83",
+X"e08c0c04",
+X"83e08c08",
+X"0283e08c",
+X"0cfd3d0d",
+X"810b83e0",
+X"8c08fc05",
+X"0c800b83",
+X"e08c08f8",
+X"050c83e0",
+X"8c088c05",
+X"0883e08c",
+X"08880508",
+X"27b93883",
+X"e08c08fc",
+X"0508802e",
+X"ae38800b",
+X"83e08c08",
+X"8c050824",
+X"a23883e0",
+X"8c088c05",
+X"081083e0",
+X"8c088c05",
+X"0c83e08c",
+X"08fc0508",
+X"1083e08c",
+X"08fc050c",
+X"ffb83983",
+X"e08c08fc",
+X"0508802e",
+X"80e13883",
+X"e08c088c",
+X"050883e0",
+X"8c088805",
+X"0826ad38",
+X"83e08c08",
+X"88050883",
+X"e08c088c",
+X"05083183",
+X"e08c0888",
+X"050c83e0",
+X"8c08f805",
+X"0883e08c",
+X"08fc0508",
+X"0783e08c",
+X"08f8050c",
+X"83e08c08",
+X"fc050881",
+X"2a83e08c",
+X"08fc050c",
+X"83e08c08",
+X"8c050881",
+X"2a83e08c",
+X"088c050c",
+X"ff953983",
+X"e08c0890",
+X"0508802e",
+X"933883e0",
+X"8c088805",
+X"087083e0",
+X"8c08f405",
+X"0c519139",
+X"83e08c08",
+X"f8050870",
+X"83e08c08",
+X"f4050c51",
+X"83e08c08",
+X"f4050883",
+X"e0800c85",
+X"3d0d83e0",
+X"8c0c0483",
+X"e08c0802",
+X"83e08c0c",
+X"ff3d0d80",
+X"0b83e08c",
+X"08fc050c",
+X"83e08c08",
+X"88050881",
+X"06ff1170",
+X"097083e0",
+X"8c088c05",
+X"080683e0",
+X"8c08fc05",
+X"081183e0",
+X"8c08fc05",
+X"0c83e08c",
+X"08880508",
+X"812a83e0",
+X"8c088805",
+X"0c83e08c",
+X"088c0508",
+X"1083e08c",
+X"088c050c",
+X"51515151",
+X"83e08c08",
+X"88050880",
+X"2e8438ff",
+X"ab3983e0",
+X"8c08fc05",
+X"087083e0",
+X"800c5183",
+X"3d0d83e0",
+X"8c0c04fc",
+X"3d0d7670",
+X"797b5555",
+X"55558f72",
+X"278c3872",
+X"75078306",
+X"5170802e",
+X"a938ff12",
+X"5271ff2e",
+X"98387270",
+X"81055433",
+X"74708105",
+X"5634ff12",
+X"5271ff2e",
+X"098106ea",
+X"387483e0",
+X"800c863d",
+X"0d047451",
+X"72708405",
+X"54087170",
+X"8405530c",
+X"72708405",
+X"54087170",
+X"8405530c",
+X"72708405",
+X"54087170",
+X"8405530c",
+X"72708405",
+X"54087170",
+X"8405530c",
+X"f0125271",
+X"8f26c938",
+X"83722795",
+X"38727084",
+X"05540871",
+X"70840553",
+X"0cfc1252",
+X"718326ed",
+X"387054ff",
+X"81390000",
+X"00ffffff",
+X"ff00ffff",
+X"ffff00ff",
+X"ffffff00",
+X"000009a7",
+X"000009e8",
+X"00000a0a",
+X"00000a28",
+X"00000a28",
+X"00000a28",
+X"00000a28",
+X"00000a97",
+X"00000ac7",
+X"70704740",
+X"9c704268",
+X"9c020202",
+X"02020202",
+X"02020202",
+X"02020202",
+X"02020202",
+X"02020241",
+X"00060000",
+X"36344b00",
+X"3132384b",
+X"00000000",
+X"3332304b",
+X"28436f6d",
+X"70792900",
+X"3332304b",
+X"2852616d",
+X"626f2900",
+X"3537364b",
+X"28436f6d",
+X"70792900",
+X"3537364b",
+X"2852616d",
+X"626f2900",
+X"314d4200",
+X"344d4200",
+X"53650000",
+X"7474696e",
+X"67730000",
+X"54757262",
+X"6f3a2564",
+X"78000000",
+X"52616d3a",
+X"25730000",
+X"526f6d3a",
+X"25730000",
+X"44726976",
+X"65202564",
+X"3a257320",
+X"25730000",
+X"43617274",
+X"72696467",
+X"6520386b",
+X"2073696d",
+X"706c6500",
+X"45786974",
+X"00000000",
+X"61746172",
+X"69786c2e",
+X"726f6d00",
+X"61746172",
+X"69626173",
+X"2e726f6d",
+X"00000000",
+X"25732025",
+X"73000000",
+X"2e2e0000",
+X"41545200",
+X"58464400",
+X"58455800",
+X"524f4d00",
+X"43686f6f",
+X"73652000",
+X"66696c65",
+X"00000000",
+X"4449523a",
+X"00000000",
+X"44495200",
+X"6e616d65",
+X"20000000",
+X"25303278",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00003c94",
+X"00003c98",
+X"00003ca0",
+X"00003cac",
+X"00003cb8",
+X"00003cc4",
+X"00003cd0",
+X"00003cd4",
+X"0001d20f",
+X"0001d400",
+X"0001d401",
+X"0001d409",
+X"0001d010",
+X"0001d301",
+X"0001d300",
+X"0001d20a",
+X"0001d01b",
+X"0001d016",
+X"0001d019",
+X"0001d018",
+X"0001d017",
+X"0001d01a",
+X"0001d403",
+X"0001d402",
+X"0001d40e",
+X"0004007c",
+X"00040078",
+X"00040074",
+X"00040068",
+X"00040060",
+X"0004005c",
+X"00040058",
+X"00040054",
+X"00040050",
+X"0004004c",
+X"00040048",
+X"00040044",
+X"00040040",
+X"00040034",
+X"00040030",
+X"0004002c",
+X"00040028",
+X"00040024",
+X"00040020",
+X"0004001c",
+X"00040018",
+X"00040014",
+X"00040010",
+X"0004000c",
+X"00040008",
+X"00040004",
+X"00040000",
+X"72025f07",
+X"f807a900",
+X"8d04038d",
+X"4402a907",
+X"8d0503a9",
+X"708d0a03",
+X"a9018d0b",
+X"03850960",
+X"7d8a4820",
+X"53e488d0",
+X"fa68aa8c",
+X"8e07ad7d",
+X"07ee8e07",
+X"60a9938d",
+X"e202a907",
+X"8de302a2",
+X"0220da07",
+X"954320da",
+X"07954435",
+X"43c9fff0",
+X"f0caca10",
+X"ec3006e6",
+X"45d002e6",
+X"4620da07",
+X"a2018144",
+X"b545d543",
+X"d0edca10",
+X"f720d207",
+X"4c9407a9",
+X"038d0fd2",
+X"6ce202ad",
+X"8e07cd7f",
+X"07d0abee",
+X"0a03d003",
+X"ee0b03ad",
+X"7d070d7e",
+X"07d08e20",
+X"d2076ce0",
+X"0220da07",
+X"8de00220",
+X"da078de1",
+X"022de002",
+X"c9fff0ed",
+X"a9008d8e",
+X"07f08200",
+X"2f737973",
+X"74656d2f",
+X"726f6d2f",
+X"61746172",
+X"69383030",
+X"00000000",
+X"2f617461",
+X"72693830",
+X"302f7573",
+X"65720000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000"
+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
