EclaireXL

---------------------------------------------------------------------------

-- (c) 2013 mark watson

-- I am happy for anyone to use this for non-commercial use.

-- If my vhdl files are used commercially or otherwise sold,

-- please contact me for explicit permission at scrameta (gmail).

-- This applies for source and binary form and derived works.

---------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

use ieee.numeric_std.all;

ENTITY zpu_config_regs IS

PORT

(

CLK : IN STD_LOGIC;

ENABLE_179 : in std_logic;

ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);

CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

WR_EN : IN STD_LOGIC;

-- SWITCHES

SWITCH : in std_logic_vector(9 downto 0); -- already synchronized

KEY : in std_logic_vector(3 downto 0); -- already synchronized

-- LEDS

LEDG : out std_logic_vector(7 downto 0);

LEDR : out std_logic_vector(9 downto 0);

-- SDCARD

SDCARD_CLK : out std_logic;

SDCARD_CMD : out std_logic;

SDCARD_DAT : in std_logic;

SDCARD_DAT3 : out std_logic;

-- ATARI interface (in future we can also turbo load by directly hitting memory...)

SIO_DATA_IN : out std_logic;

SIO_COMMAND_OUT : in std_logic;

SIO_DATA_OUT : in std_logic;

-- CPU interface

DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

PAUSE_ZPU : out std_logic;

-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)

PAL : OUT STD_LOGIC;

USE_SDRAM : OUT STD_LOGIC;

RAM_SELECT : OUT STD_LOGIC_VECTOR(3 downto 0);

VGA : OUT STD_LOGIC;

COMPOSITE_ON_HSYNC : OUT STD_LOGIC;

GPIO_ENABLE : OUT STD_LOGIC;

ROM_SELECT : out stD_logic_vector(3 downto 0);

-- sector buffer

sector : out std_logic_vector(31 downto 0);

sector_request : out std_logic;

sector_ready : in std_logic;

-- system reset/halt

PLL_LOCKED : IN STD_LOGIC; -- pll locked

REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)

RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502

RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu

RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops

PAUSE_6502 : out std_logic;

THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);

ZPU_HEX : out std_logic_vector(15 downto 0)

-- -- synchronize async inputs

-- locked_synchronizer : synchronizer

-- port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);

);

END zpu_config_regs;

ARCHITECTURE vhdl OF zpu_config_regs IS

COMPONENT complete_address_decoder IS

generic (width : natural := 4);

PORT

(

addr_in : in std_logic_vector(width-1 downto 0);

addr_decoded : out std_logic_vector((2**width)-1 downto 0)

);

END component;

COMPONENT spi_master IS

GENERIC(

slaves : INTEGER := 4; --number of spi slaves

d_width : INTEGER := 2); --data bus width

PORT(

clock : IN STD_LOGIC; --system clock

reset_n : IN STD_LOGIC; --asynchronous reset

enable : IN STD_LOGIC; --initiate transaction

cpol : IN STD_LOGIC; --spi clock polarity

cpha : IN STD_LOGIC; --spi clock phase

cont : IN STD_LOGIC; --continuous mode command

clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk

addr : IN INTEGER; --address of slave

tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit

miso : IN STD_LOGIC; --master in, slave out

sclk : BUFFER STD_LOGIC; --spi clock

ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select

mosi : OUT STD_LOGIC; --master out, slave in

busy : OUT STD_LOGIC; --busy / data ready signal

rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received

END component;

component pokey IS

PORT

(

CLK : IN STD_LOGIC;

--ENABLE_179 :in std_logic;

CPU_MEMORY_READY :in std_logic;

ANTIC_MEMORY_READY :in std_logic;

ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

WR_EN : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

-- keyboard interface

keyboard_scan : out std_logic_vector(5 downto 0);

keyboard_response : in std_logic_vector(1 downto 0);

-- pots - go high as capacitor charges

POT_IN : in std_logic_vector(7 downto 0);

-- sio interface

SIO_IN1 : IN std_logic;

SIO_IN2 : IN std_logic;

SIO_IN3 : IN std_logic;

DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);

CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);

CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);

CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);

IRQ_N_OUT : OUT std_logic;

SIO_OUT1 : OUT std_logic;

SIO_OUT2 : OUT std_logic;

SIO_OUT3 : OUT std_logic;

SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally

POT_RESET : out std_logic

);

END component;

function vectorize(s: std_logic) return std_logic_vector is

variable v: std_logic_vector(0 downto 0);

begin

v(0) := s;

return v;

end;

signal addr_decoded : std_logic_vector(15 downto 0);

signal config_6502_next : std_logic_vector(7 downto 0);

signal config_6502_reg : std_logic_vector(7 downto 0);

signal ram_select_next : std_logic_vector(3 downto 0);

signal ram_select_reg : std_logic_vector(3 downto 0);

signal rom_select_next : std_logic_vector(3 downto 0);

signal rom_select_reg : std_logic_vector(3 downto 0);

signal gpio_enable_next : std_logic;

signal gpio_enable_reg : std_logic;

signal pause_next : std_logic_vector(31 downto 0);

signal pause_reg : std_logic_vector(31 downto 0);

signal paused_next : std_logic;

signal paused_reg : std_logic;

signal ledg_next : std_logic_vector(7 downto 0);

signal ledg_reg : std_logic_vector(7 downto 0);

signal ledr_next : std_logic_vector(9 downto 0);

signal ledr_reg : std_logic_vector(9 downto 0);

signal reset_n_next : std_logic;

signal reset_n_reg : std_logic;

signal reset_6502_cpu_next : std_logic;

signal reset_6502_cpu_reg : std_logic;

signal reset_zpu_next : std_logic;

signal reset_zpu_reg : std_logic;

signal spi_miso : std_logic;

signal spi_mosi : std_logic;

signal spi_busy : std_logic;

signal spi_enable : std_logic;

signal spi_chip_select : std_logic_vector(0 downto 0);

signal spi_clk_out : std_logic;

signal spi_tx_data : std_logic_vector(7 downto 0);

signal spi_rx_data : std_logic_vector(7 downto 0);

signal spi_addr_next : std_logic;

signal spi_addr_reg : std_logic;

signal spi_speed_next : std_logic_vector(7 downto 0);

signal spi_speed_reg : std_logic_vector(7 downto 0);

signal zpu_hex_next : std_logic_vector(15 downto 0);

signal zpu_hex_reg : std_logic_vector(15 downto 0);

signal pokey_data_out : std_logic_vector(7 downto 0);

signal sector_next : std_logic_vector(31 downto 0);

signal sector_reg : std_logic_vector(31 downto 0);

signal sector_request_next : std_logic;

signal sector_request_reg : std_logic; -- cleared when ready asserted

begin

-- register

process(clk,pll_locked)

begin

if (clk'event and clk='1') then

if (pll_locked = '0') then

config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles

rom_select_reg <= "0010";

ram_select_reg <= "0010";

gpio_enable_reg <= '0';

pause_reg <= (others=>'0');

paused_reg <= '0';

ledg_reg <= (others=>'0');

ledr_reg <= (others=>'0');

spi_addr_reg <= '1';

spi_speed_reg <= X"80";

zpu_hex_reg <= X"b007";

reset_n_reg <= '0';

reset_zpu_reg <= '1';

reset_6502_cpu_reg <= '1';

sector_reg <= (others=>'0');

sector_request_reg <= '0';

else

config_6502_reg <= config_6502_next;

rom_select_reg <= rom_select_next;

ram_select_reg <= ram_select_next;

gpio_enable_reg <= gpio_enable_next;

pause_reg <= pause_next;

paused_reg <= paused_next;

ledg_reg <= ledg_next;

ledr_reg <= ledr_next;

spi_addr_reg <= spi_addr_next;

spi_speed_reg <= spi_speed_next;

zpu_hex_reg <= zpu_hex_next;

reset_n_reg <= reset_n_next;

reset_zpu_reg <= reset_zpu_next;

reset_6502_cpu_reg <= reset_6502_cpu_next;

sector_reg <= sector_next;

sector_request_reg <= sector_request_next;

end if;

end if;

end process;

-- decode address

decode_addr1 : complete_address_decoder

generic map(width=>4)

port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);

-- spi - for sd card access without bit banging...

-- 200KHz to start with - probably fine for 8-bit, can up it later after init

spi_master1 : spi_master

generic map(slaves=>1,d_width=>8)

port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),

tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,

rx_data=>spi_rx_data,busy=>spi_busy);

-- spi-programming model:

-- reg for write/read

-- data (send/receive)

-- busy

-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...

-- chip select

-- uart - another Pokey! Running at atari frequency.

uart1 : pokey

port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en,

reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",

sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...

data_out=>pokey_data_out,

sio_out1=>sio_data_in);

-- hardware regs for ZPU

--

-- KEYS -> all for ZPU. SWITCHES -> all for ZPU

-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram

-- these need storing somewhere...

-- TODO - volume output from here

-- TODO - hex digits register

-- TODO - if we take over antic we need to point antic to alternative RAM!

-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...

-- TODO - reset pokey and pia interrupts too?

--

-- virtual joystick button -> keyboard (windows key?)

-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.

--

-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.

--

-- STEP 1 -> joystick -> keyboard (DONE)

-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled (DONE)

-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)

-- STEP 4 -> zpu starts 6502 on key1 (DONE)

-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)

--

-- CONFIG_ATARI:

-- R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset

-- R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo

-- R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo

-- R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)

-- PAUSE (DONE) -- W: 0-31:wait for n cycles

-- SWITCH (DONE)

-- R: 0-9 - switches

-- KEY (DONE)

-- R: 0-3 - keys

-- LEDG (DONE)

-- R/W: 0-9

-- LEDR (DONE)

-- R/W: 0-9

-- SPI_DATA (DONE)

-- W - write data (starts transmission)

-- R - read data (wait for complete first)

-- SPI_STATE/SPI_CTRL (DONE)

-- R: 0=busy

-- W: 0=select_n, speed

-- SIO

-- R: 0=CMD

-- FPGA board (DONE)

-- R(32 bits) 0=DE1

-- HEX digits

-- W(16 bits)

-- SECTOR

-- W(32 bits) - write here initiates a request_reset_zpu

-- R: 0=request_active

-- TODO, ROM select, RAM select etc etc

-- TODO firmware with OSD!

-- Writes to registers

process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg, sector_request_reg, sector_ready, sector_reg)

begin

config_6502_next <= config_6502_reg;

rom_select_next <= rom_select_reg;

ram_select_next <= ram_select_reg;

gpio_enable_next <= gpio_enable_reg;

pause_next <= pause_reg;

ledg_next <= ledg_reg;

ledr_next <= ledr_reg;

spi_speed_next <= spi_speed_reg;

spi_addr_next <= spi_addr_reg;

spi_tx_data <= (others=>'0');

spi_enable <= '0';

zpu_hex_next <= zpu_hex_reg;

sector_next <= sector_reg;

sector_request_next <= sector_request_reg and not(sector_ready);

paused_next <= '0';

if (not(pause_reg = X"00000000")) then

pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));

paused_next <= '1';

end if;

if (wr_en = '1' and addr(4) = '0') then

if(addr_decoded(0) = '1') then

config_6502_next <= cpu_data_in(7 downto 0);

ram_select_next <= cpu_DATA_IN(11 downto 8);

rom_select_next <= cpu_DATA_IN(15 downto 12);

gpio_enable_next <= cpu_DATA_IN(16);

end if;

if(addr_decoded(1) = '1') then

pause_next <= cpu_data_in;

paused_next <= '1';

end if;

if(addr_decoded(4) = '1') then

ledg_next <= cpu_data_in(7 downto 0);

end if;

if(addr_decoded(5) = '1') then

ledr_next <= cpu_data_in(9 downto 0);

end if;

if(addr_decoded(6) = '1') then

-- TODO, check overrun?

spi_tx_data <= cpu_data_in(7 downto 0);

spi_enable <= '1';

end if;

if(addr_decoded(7) = '1') then

spi_addr_next <= cpu_data_in(0);

if (cpu_data_in(1) = '1') then

spi_speed_next <= X"80"; -- slow, for init

else

spi_speed_next <= X"04"; -- turbo!

end if;

end if;

if(addr_decoded(10) = '1') then

zpu_hex_next <= cpu_data_in(15 downto 0);

end if;

if(addr_decoded(11) = '1') then

sector_next <= cpu_data_in;

sector_request_next <= '1';

end if;

end if;

end process;

-- Read from registers

process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg, sector_request_reg)

begin

data_out <= (others=>'0');

if (addr(4) = '0') then

if (addr_decoded(0) = '1') then

data_out(7 downto 0) <= config_6502_reg;

data_out(11 downto 8) <= ram_select_reg;

data_out(15 downto 12) <= rom_select_reg;

data_out(16) <= gpio_enable_reg;

end if;

if (addr_decoded(2) = '1') then

data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.

end if;

if (addr_decoded(3) = '1') then

data_out(3 downto 0) <= key;

end if;

if (addr_decoded(4) = '1') then

data_out(7 downto 0) <= ledg_reg;

end if;

if (addr_decoded(5) = '1') then

data_out(9 downto 0) <= ledr_reg;

end if;

if (addr_decoded(6) = '1') then

data_out(7 downto 0) <= spi_rx_data;

end if;

if (addr_decoded(7) = '1') then

data_out(0) <= spi_busy;

end if;

if(addr_decoded(8) = '1') then

data_out(0) <= sio_command_OUT;

end if;

if (addr_decoded(9) = '1') then

--data_out <= X"00000000"; -- DE1!

--data_out <= X"00000001"; -- DE2!

--data_out <= X"00000002"; -- SOCKIT!

--data_out <= X"00000003"; -- REPLAY!

data_out <= X"00000004"; -- MMC!

end if;

if (addr_decoded(10) = '1') then

data_out(15 downto 0) <= zpu_hex_reg;

end if;

if (addr_decoded(11) = '1') then

data_out(0) <= sector_request_reg;

end if;

else

data_out(7 downto 0) <= pokey_data_out;

end if;

end process;

process(request_reset_zpu, config_6502_next, config_6502_reg)

begin

reset_n_next <= '1';

reset_zpu_next <= '0';

reset_6502_cpu_next <= config_6502_reg(7);

if (request_reset_zpu = '1') then

reset_n_next <= '0';

reset_zpu_next <= '1';

reset_6502_cpu_next <= '1';

end if;

end process;

-- outputs

PAUSE_ZPU <= paused_reg;

LEDG <= ledg_reg;

LEDR <= ledr_reg;

SDCARD_CLK <= spi_clk_out;

SDCARD_CMD <= spi_mosi;

spi_miso <= SDCARD_DAT; -- INPUT!! XXX

SDCARD_DAT3 <= spi_chip_select(0);

PAL <= '1'; -- TODO

--USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...

USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...

RAM_SELECT <= ram_select_reg;

VGA <= '1';

COMPOSITE_ON_HSYNC <= '0';

GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!

ROM_SELECT <= rom_select_reg;

reset_n <= reset_n_reg; -- system reset or pll not locked

reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked

reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled

pause_6502 <= config_6502_reg(6); -- zpu software controlled

throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled

zpu_hex <= zpu_hex_reg;

sector <= sector_reg;

sector_request <= sector_request_reg;

end vhdl;

-- Copyright (C) 1991-2012 Altera Corporation

-- Your use of Altera Corporation's design tools, logic functions

-- and other software and tools, and its AMPP partner logic

-- functions, and any output files from any of the foregoing

-- (including device programming or simulation files), and any

-- associated documentation or information are expressly subject

-- to the terms and conditions of the Altera Program License

-- Subscription Agreement, Altera MegaCore Function License

-- Agreement, or other applicable license agreement, including,

-- without limitation, that your use is for the sole purpose of

-- programming logic devices manufactured by Altera and sold by

-- Altera or its authorized distributors. Please refer to the

-- applicable agreement for further details.

-- PROGRAM "Quartus II 64-Bit"

-- VERSION "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"

-- CREATED "Tue Dec 31 22:21:48 2013"

LIBRARY ieee;

USE ieee.std_logic_1164.all;

use ieee.numeric_std.all;

LIBRARY work;

ENTITY atari800core IS

PORT

(

CLOCK_27 : IN STD_LOGIC_VECTOR(1 downto 0);

-- PS2K_CLK : IN STD_LOGIC;

-- PS2K_DAT : IN STD_LOGIC;

-- PS2M_CLK : IN STD_LOGIC;

-- PS2M_DAT : IN STD_LOGIC;

VGA_VS : OUT STD_LOGIC;

VGA_HS : OUT STD_LOGIC;

VGA_B : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

VGA_G : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

VGA_R : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

-- JOY1_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);

-- JOY2_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);

AUDIO_L : OUT std_logic;

AUDIO_R : OUT std_logic;

SDRAM_BA : OUT STD_LOGIC_VECTOR(1 downto 0);

SDRAM_nCS : OUT STD_LOGIC;

SDRAM_nRAS : OUT STD_LOGIC;

SDRAM_nCAS : OUT STD_LOGIC;

SDRAM_nWE : OUT STD_LOGIC;

SDRAM_DQMH : OUT STD_LOGIC;

SDRAM_DQML : OUT STD_LOGIC;

SDRAM_CLK : OUT STD_LOGIC;

SDRAM_CKE : OUT STD_LOGIC;

SDRAM_A : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);

SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

-- SD_DAT0 : IN STD_LOGIC;

-- SD_CLK : OUT STD_LOGIC;

-- SD_CMD : OUT STD_LOGIC;

-- SD_DAT3 : OUT STD_LOGIC

LED : OUT std_logic;

UART_TX : OUT STD_LOGIC;

UART_RX : IN STD_LOGIC;

SPI_DO : INOUT STD_LOGIC;

SPI_DI : IN STD_LOGIC;

SPI_SCK : IN STD_LOGIC;

SPI_SS2 : IN STD_LOGIC;

SPI_SS3 : IN STD_LOGIC;

SPI_SS4 : IN STD_LOGIC;

CONF_DATA0 : IN STD_LOGIC -- AKA SPI_SS5

);

END atari800core;

ARCHITECTURE bdf_type OF atari800core IS

--

--component generic_ram_infer IS

-- generic

-- (

-- ADDRESS_WIDTH : natural := 9;

-- SPACE : natural := 512;

-- DATA_WIDTH : natural := 8

-- );

-- PORT

-- (

-- clock: IN std_logic;

-- data: IN std_logic_vector (data_width-1 DOWNTO 0);

-- address: IN std_logic_vector(address_width-1 downto 0);

-- we: IN std_logic;

-- q: OUT std_logic_vector (data_width-1 DOWNTO 0)

-- );

--END component;

component mist_sector_buffer IS

PORT

(

address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);

address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);

clock_a : IN STD_LOGIC := '1';

clock_b : IN STD_LOGIC ;

data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

wren_a : IN STD_LOGIC := '0';

wren_b : IN STD_LOGIC := '0';

q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

END component;

component synchronizer IS

PORT

(

CLK : IN STD_LOGIC;

RAW : IN STD_LOGIC;

SYNC : OUT STD_LOGIC

);

END component;

component data_io IS

PORT

(

CLK : in std_logic;

RESET_n : in std_logic;

-- SPI connection - up to upstream to make miso 'Z' on ss_io going high

SPI_CLK : in std_logic;

SPI_SS_IO : in std_logic;

SPI_MISO: out std_logic;

SPI_MOSI : in std_logic;

-- Sector access request

request : in std_logic;

sector : in std_logic_vector(23 downto 0);

ready : out std_logic;

-- DMA to RAM

ADDR: out std_logic_vector(8 downto 0);

DATA_OUT : out std_logic_vector(7 downto 0);

DATA_IN : in std_logic_vector(7 downto 0);

WR_EN : out std_logic

);

end component;

component user_io

PORT(

SPI_CLK : in std_logic;

SPI_SS_IO : in std_logic;

SPI_MISO : out std_logic;

SPI_MOSI : in std_logic;

CORE_TYPE : in std_logic_vector(7 downto 0);

JOY0 : out std_logic_vector(5 downto 0);

JOY1 : out std_logic_vector(5 downto 0);

KEYBOARD : out std_logic_vector(127 downto 0);

BUTTONS : out std_logic_vector(1 downto 0);

SWITCHES : out std_logic_vector(1 downto 0)

);

end component;

COMPONENT complete_address_decoder IS

generic (width : natural := 1);

PORT

(

addr_in : in std_logic_vector(width-1 downto 0);

addr_decoded : out std_logic_vector((2**width)-1 downto 0)

);

END component;

COMPONENT cpu

PORT(CLK : IN STD_LOGIC;

RESET : IN STD_LOGIC;

ENABLE : IN STD_LOGIC;

IRQ_n : IN STD_LOGIC;

NMI_n : IN STD_LOGIC;

MEMORY_READY : IN STD_LOGIC;

THROTTLE : IN STD_LOGIC;

RDY : IN STD_LOGIC;

DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

R_W_n : OUT STD_LOGIC;

CPU_FETCH : OUT STD_LOGIC;

A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END COMPONENT;

component hq_dac

port (

reset :in std_logic;

clk :in std_logic;

clk_ena : in std_logic;

pcm_in : in std_logic_vector(19 downto 0);

dac_out : out std_logic

);

end component;

component internalromram IS

PORT(

clock : IN STD_LOGIC; --system clock

reset_n : IN STD_LOGIC; --asynchronous reset

ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);

ROM_REQUEST_COMPLETE : out STD_LOGIC;

ROM_REQUEST : in std_logic;

ROM_DATA : out std_logic_vector(7 downto 0);

RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);

RAM_WR_ENABLE : in std_logic;

RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);

RAM_REQUEST_COMPLETE : out STD_LOGIC;

RAM_REQUEST : in std_logic;

RAM_DATA : out std_logic_vector(7 downto 0)

);

END component;

COMPONENT antic

PORT(CLK : IN STD_LOGIC;

WR_EN : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

MEMORY_READY_ANTIC : IN STD_LOGIC;

MEMORY_READY_CPU : IN STD_LOGIC;

ANTIC_ENABLE_179 : IN STD_LOGIC;

PAL : IN STD_LOGIC;

lightpen : IN STD_LOGIC;

ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

NMI_N_OUT : OUT STD_LOGIC;

ANTIC_READY : OUT STD_LOGIC;

COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;

COLOUR_CLOCK_OUT : OUT STD_LOGIC;

HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;

dma_fetch_out : OUT STD_LOGIC;

refresh_out : OUT STD_LOGIC;

dma_clock_out : OUT STD_LOGIC;

AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

);

END COMPONENT;

COMPONENT ledsw

PORT(CLK : IN STD_LOGIC;

KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)

);

END COMPONENT;

COMPONENT pokey_mixer

PORT(CLK : IN STD_LOGIC;

GTIA_SOUND : IN STD_LOGIC;

CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);

COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);

CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

);

END COMPONENT;

COMPONENT ps2_keyboard

PORT(CLK : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

PS2_CLK : IN STD_LOGIC;

PS2_DAT : IN STD_LOGIC;

KEY_EVENT : OUT STD_LOGIC;

KEY_EXTENDED : OUT STD_LOGIC;

KEY_UP : OUT STD_LOGIC;

KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END COMPONENT;

COMPONENT zpu_glue

PORT(CLK : IN STD_LOGIC;

RESET : IN STD_LOGIC;

PAUSE : IN STD_LOGIC;

MEMORY_READY : IN STD_LOGIC;

ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

MEMORY_FETCH : OUT STD_LOGIC;

ZPU_READ_ENABLE : OUT STD_LOGIC;

ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;

ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;

ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;

ZPU_CONFIG_WRITE : OUT STD_LOGIC;

ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);

ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);

ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END COMPONENT;

COMPONENT pokey

PORT(CLK : IN STD_LOGIC;

CPU_MEMORY_READY : IN STD_LOGIC;

ANTIC_MEMORY_READY : IN STD_LOGIC;

WR_EN : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

SIO_IN1 : IN STD_LOGIC;

SIO_IN2 : IN STD_LOGIC;

SIO_IN3 : IN STD_LOGIC;

SIO_CLOCK : INOUT STD_LOGIC;

ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

IRQ_N_OUT : OUT STD_LOGIC;

SIO_OUT1 : OUT STD_LOGIC;

SIO_OUT2 : OUT STD_LOGIC;

SIO_OUT3 : OUT STD_LOGIC;

POT_RESET : OUT STD_LOGIC;

CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)

);

END COMPONENT;

COMPONENT pia

PORT( CLK : IN STD_LOGIC;

ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

EN : IN STD_LOGIC;

WR_EN : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

CA1 : IN STD_LOGIC;

CB1 : IN STD_LOGIC;

CA2_DIR_OUT : OUT std_logic;

CA2_OUT : OUT std_logic;

CA2_IN : IN STD_LOGIC;

CB2_DIR_OUT : OUT std_logic;

CB2_OUT : OUT std_logic;

CB2_IN : IN STD_LOGIC;

-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)

-- pull up - i.e. 0 driven only

PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode

PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);

PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);

PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);

PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull

PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull

-- CPU interface

DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

IRQA_N : OUT STD_LOGIC;

IRQB_N : OUT STD_LOGIC );

END COMPONENT;

COMPONENT shared_enable

PORT(CLK : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

MEMORY_READY_CPU : IN STD_LOGIC;

MEMORY_READY_ANTIC : IN STD_LOGIC;

PAUSE_6502 : IN STD_LOGIC;

THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);

POKEY_ENABLE_179 : OUT STD_LOGIC;

ANTIC_ENABLE_179 : OUT STD_LOGIC;

oldcpu_enable : OUT STD_LOGIC;

CPU_ENABLE_OUT : OUT STD_LOGIC;

SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;

SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC

);

END COMPONENT;

COMPONENT pokey_ps2_decoder

PORT(CLK : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

KEY_EVENT : IN STD_LOGIC;

KEY_EXTENDED : IN STD_LOGIC;

KEY_UP : IN STD_LOGIC;

KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

KEY_HELD : OUT STD_LOGIC;

SHIFT_PRESSED : OUT STD_LOGIC;

BREAK_PRESSED : OUT STD_LOGIC;

KEY_INTERRUPT : OUT STD_LOGIC;

CONSOL_START : OUT STD_LOGIC;

CONSOL_SELECT : OUT STD_LOGIC;

CONSOL_OPTION : OUT STD_LOGIC;

SYSTEM_RESET : OUT STD_LOGIC;

KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

VIRTUAL_KEYS : out std_logic_vector(3 downto 0)

);

END COMPONENT;

COMPONENT address_decoder

PORT(CLK : IN STD_LOGIC;

CPU_FETCH : IN STD_LOGIC;

CPU_WRITE_N : IN STD_LOGIC;

ANTIC_FETCH : IN STD_LOGIC;

antic_refresh : IN STD_LOGIC;

ZPU_FETCH : IN STD_LOGIC;

ZPU_READ_ENABLE : IN STD_LOGIC;

ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;

ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;

ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;

RAM_REQUEST_COMPLETE : IN STD_LOGIC;

ROM_REQUEST_COMPLETE : IN STD_LOGIC;

CART_REQUEST_COMPLETE : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

CART_RD4 : IN STD_LOGIC;

CART_RD5 : IN STD_LOGIC;

use_sdram : IN STD_LOGIC;

SDRAM_REQUEST_COMPLETE : IN STD_LOGIC;

ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

ram_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

rom_select : in std_logic_vector(5 downto 0);

cart_select : in std_logic_vector(6 downto 0);

cart_activate : in std_logic;

SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);

ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

MEMORY_READY_ANTIC : OUT STD_LOGIC;

MEMORY_READY_ZPU : OUT STD_LOGIC;

MEMORY_READY_CPU : OUT STD_LOGIC;

GTIA_WR_ENABLE : OUT STD_LOGIC;

POKEY_WR_ENABLE : OUT STD_LOGIC;

POKEY2_WR_ENABLE : OUT STD_LOGIC;

ANTIC_WR_ENABLE : OUT STD_LOGIC;

PIA_WR_ENABLE : OUT STD_LOGIC;

PIA_RD_ENABLE : OUT STD_LOGIC;

RAM_WR_ENABLE : OUT STD_LOGIC;

PBI_WR_ENABLE : OUT STD_LOGIC;

RAM_REQUEST : OUT STD_LOGIC;

ROM_REQUEST : OUT STD_LOGIC;

CART_REQUEST : OUT STD_LOGIC;

CART_S4_n : OUT STD_LOGIC;

CART_S5_n : OUT STD_LOGIC;

CART_CCTL_n : OUT STD_LOGIC;

WIDTH_8bit_ACCESS : OUT STD_LOGIC;

WIDTH_16bit_ACCESS : OUT STD_LOGIC;

WIDTH_32bit_ACCESS : OUT STD_LOGIC;

SDRAM_READ_EN : OUT STD_LOGIC;

SDRAM_WRITE_EN : OUT STD_LOGIC;

SDRAM_REQUEST : OUT STD_LOGIC;

SDRAM_REFRESH : OUT STD_LOGIC;

MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);

ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);

SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);

WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

D6_WR_ENABLE : out std_logic

);

END COMPONENT;

COMPONENT sdram_statemachine

GENERIC (ADDRESS_WIDTH : INTEGER;

AP_BIT : INTEGER;

COLUMN_WIDTH : INTEGER;

ROW_WIDTH : INTEGER

);

PORT(CLK_SYSTEM : IN STD_LOGIC;

CLK_SDRAM : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

READ_EN : IN STD_LOGIC;

WRITE_EN : IN STD_LOGIC;

REQUEST : IN STD_LOGIC;

BYTE_ACCESS : IN STD_LOGIC;

WORD_ACCESS : IN STD_LOGIC;

LONGWORD_ACCESS : IN STD_LOGIC;

REFRESH : IN STD_LOGIC;

ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);

DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

COMPLETE : OUT STD_LOGIC;

SDRAM_BA0 : OUT STD_LOGIC;

SDRAM_BA1 : OUT STD_LOGIC;

SDRAM_CKE : OUT STD_LOGIC;

SDRAM_CS_N : OUT STD_LOGIC;

SDRAM_RAS_N : OUT STD_LOGIC;

SDRAM_CAS_N : OUT STD_LOGIC;

SDRAM_WE_N : OUT STD_LOGIC;

SDRAM_ldqm : OUT STD_LOGIC;

SDRAM_udqm : OUT STD_LOGIC;

DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)

);

END COMPONENT;

component sdram_statemachine_mcc IS

generic

(

ADDRESS_WIDTH : natural := 22;

ROW_WIDTH : natural := 12;

AP_BIT : natural := 10;

COLUMN_WIDTH : natural := 8

);

PORT

(

CLK_SYSTEM : IN STD_LOGIC;

CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock

RESET_N : in STD_LOGIC;

-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?

DATA_IN : in std_logic_vector(31 downto 0);

ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment

READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh

WRITE_EN : in std_logic;

REQUEST : in std_logic; -- Toggle this to issue a new request

BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.

WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.

LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000

REFRESH : in std_logic;

REPLY : out std_logic; -- This matches the request once complete

DATA_OUT : out std_logic_vector(31 downto 0);

-- sdram itself

SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);

SDRAM_DQ : inout std_logic_vector(15 downto 0);

SDRAM_BA0 : out std_logic;

SDRAM_BA1 : out std_logic;

SDRAM_CS_N : out std_logic;

SDRAM_RAS_N : out std_logic;

SDRAM_CAS_N : out std_logic;

SDRAM_WE_N : out std_logic;

SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads

SDRAM_udqm : out std_logic

);

END component;

COMPONENT zpu_rom

PORT(clock : IN STD_LOGIC;

address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);

q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)

);

END COMPONENT;

COMPONENT scandoubler

PORT(CLK : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

VGA : IN STD_LOGIC;

COMPOSITE_ON_HSYNC : IN STD_LOGIC;

colour_enable : IN STD_LOGIC;

doubled_enable : IN STD_LOGIC;

vsync_in : IN STD_LOGIC;

hsync_in : IN STD_LOGIC;

colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

VSYNC : OUT STD_LOGIC;

HSYNC : OUT STD_LOGIC;

B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END COMPONENT;

COMPONENT zpu_ram

PORT(wren : IN STD_LOGIC;

clock : IN STD_LOGIC;

address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END COMPONENT;

COMPONENT zpu_config_regs

PORT(CLK : IN STD_LOGIC;

ENABLE_179 : IN STD_LOGIC;

WR_EN : IN STD_LOGIC;

SDCARD_DAT : IN STD_LOGIC;

SIO_COMMAND_OUT : IN STD_LOGIC;

SIO_DATA_OUT : IN STD_LOGIC;

PLL_LOCKED : IN STD_LOGIC;

REQUEST_RESET_ZPU : IN STD_LOGIC;

ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);

CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

SDCARD_CLK : OUT STD_LOGIC;

SDCARD_CMD : OUT STD_LOGIC;

SDCARD_DAT3 : OUT STD_LOGIC;

SIO_DATA_IN : OUT STD_LOGIC;

PAUSE_ZPU : OUT STD_LOGIC;

PAL : OUT STD_LOGIC;

USE_SDRAM : OUT STD_LOGIC;

VGA : OUT STD_LOGIC;

COMPOSITE_ON_HSYNC : OUT STD_LOGIC;

GPIO_ENABLE : OUT STD_LOGIC;

RESET_6502 : OUT STD_LOGIC;

RESET_ZPU : OUT STD_LOGIC;

RESET_N : OUT STD_LOGIC;

PAUSE_6502 : OUT STD_LOGIC;

DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);

RAM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

ROM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

sector : out std_logic_vector(31 downto 0);

sector_request : out std_logic;

sector_ready : in std_logic

);

END COMPONENT;

COMPONENT pll

PORT(inclk0 : IN STD_LOGIC;

c0 : OUT STD_LOGIC;

c1 : OUT STD_LOGIC;

c2 : OUT STD_LOGIC;

locked : OUT STD_LOGIC

);

END COMPONENT;

COMPONENT gtia

PORT(CLK : IN STD_LOGIC;

WR_EN : IN STD_LOGIC;

CPU_MEMORY_READY : IN STD_LOGIC;

ANTIC_MEMORY_READY : IN STD_LOGIC;

ANTIC_FETCH : IN STD_LOGIC;

CPU_ENABLE_ORIGINAL : IN STD_LOGIC;

RESET_N : IN STD_LOGIC;

PAL : IN STD_LOGIC;

COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;

COLOUR_CLOCK : IN STD_LOGIC;

COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;

CONSOL_START : IN STD_LOGIC;

CONSOL_SELECT : IN STD_LOGIC;

CONSOL_OPTION : IN STD_LOGIC;

TRIG0 : IN STD_LOGIC;

TRIG1 : IN STD_LOGIC;

TRIG2 : IN STD_LOGIC;

TRIG3 : IN STD_LOGIC;

ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);

AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

VSYNC : OUT STD_LOGIC;

HSYNC : OUT STD_LOGIC;

sound : OUT STD_LOGIC;

COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END COMPONENT;

COMPONENT irq_glue

PORT(pokey_irq : IN STD_LOGIC;

pia_irqa : IN STD_LOGIC;

pia_irqb : IN STD_LOGIC;

combined_irq : OUT STD_LOGIC

);

END COMPONENT;

component reg_file IS

generic

(

BYTES : natural := 1;

WIDTH : natural := 1

);

PORT

(

CLK : IN STD_LOGIC;

ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);

DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

WR_EN : IN STD_LOGIC;

DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END component;

component covox IS

PORT

(

CLK : IN STD_LOGIC;

ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

WR_EN : IN STD_LOGIC;

covox_channel0 : out std_logic_vector(7 downto 0);

covox_channel1 : out std_logic_vector(7 downto 0);

covox_channel2 : out std_logic_vector(7 downto 0);

covox_channel3 : out std_logic_vector(7 downto 0)

);

END component;

SIGNAL ANTIC_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL ANTIC_AN : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL ANTIC_COLOUR_CLOCK_OUT : STD_LOGIC;

SIGNAL ANTIC_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL CACHE_ANTIC_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL ANTIC_ENABLE_179 : STD_LOGIC;

SIGNAL ANTIC_FETCH : STD_LOGIC;

SIGNAL ANTIC_HIGHRES_COLOUR_CLOCK_OUT : STD_LOGIC;

SIGNAL ANTIC_ORIGINAL_COLOUR_CLOCK_OUT : STD_LOGIC;

SIGNAL ANTIC_RDY : STD_LOGIC;

SIGNAL ANTIC_REFRESH : STD_LOGIC;

SIGNAL ANTIC_WRITE_ENABLE : STD_LOGIC;

SIGNAL AUDIO_LEFT : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL AUDIO_RIGHT : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL BREAK_PRESSED : STD_LOGIC;

SIGNAL CART_RD4 : STD_LOGIC;

SIGNAL CART_RD5 : STD_LOGIC;

SIGNAL CART_REQUEST : STD_LOGIC;

SIGNAL CART_REQUEST_COMPLETE : STD_LOGIC;

SIGNAL CART_ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL CART_S4_n : STD_LOGIC;

SIGNAL CART_S5_N : STD_LOGIC;

signal CART_CCTL_N : std_logic;

SIGNAL CA2_OUT : STD_LOGIC;

SIGNAL CA2_DIR_OUT: STD_LOGIC;

SIGNAL CB2_OUT : STD_LOGIC;

SIGNAL CB2_DIR_OUT: STD_LOGIC;

SIGNAL CLK : STD_LOGIC;

SIGNAL CLK_SDRAM : STD_LOGIC;

SIGNAL COMPOSITE_ON_HSYNC : STD_LOGIC;

SIGNAL CONSOL_OPTION : STD_LOGIC;

SIGNAL CONSOL_SELECT : STD_LOGIC;

SIGNAL CONSOL_START : STD_LOGIC;

SIGNAL CPU_6502_RESET : STD_LOGIC;

SIGNAL CPU_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL CPU_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL CPU_FETCH : STD_LOGIC;

SIGNAL CPU_SHARED_ENABLE : STD_LOGIC;

SIGNAL ENABLE_179_MEMWAIT : STD_LOGIC;

SIGNAL GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);

SIGNAL GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);

SIGNAL GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);

SIGNAL GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);

SIGNAL GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);

SIGNAL GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);

SIGNAL GPIO_CA2_IN: STD_LOGIC;

SIGNAL GPIO_CB2_IN: STD_LOGIC;

SIGNAL GPIO_ENABLE : STD_LOGIC;

SIGNAL GPIO_PORTA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL GPIO_PORTB_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL GPIO_SIO_IN : STD_LOGIC;

SIGNAL GPIO_SIO_OUT : STD_LOGIC;

SIGNAL GREEN_LEDS : STD_LOGIC_VECTOR(1 TO 1);

SIGNAL GREREN_LEDS : STD_LOGIC_VECTOR(0 TO 0);

SIGNAL GTIA_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL CACHE_GTIA_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL GTIA_SOUND : STD_LOGIC;

SIGNAL GTIA_WRITE_ENABLE : STD_LOGIC;

SIGNAL IRQ_n : STD_LOGIC;

SIGNAL KBCODE_DUMMY : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL KEY_HELD : STD_LOGIC;

SIGNAL KEY_INTERRUPT : STD_LOGIC;

SIGNAL KEYBOARD_RESPONSE : STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL KEYBOARD_SCAN : STD_LOGIC_VECTOR(5 DOWNTO 0);

SIGNAL LIGHTPEN : STD_LOGIC;

SIGNAL MEMORY_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL MEMORY_READY_ANTIC : STD_LOGIC;

SIGNAL MEMORY_READY_CPU : STD_LOGIC;

SIGNAL MEMORY_READY_ZPU : STD_LOGIC;

SIGNAL NMI_n : STD_LOGIC;

SIGNAL PAL : STD_LOGIC;

SIGNAL PAUSE_6502 : STD_LOGIC;

SIGNAL PBI_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL PBI_WRITE_ENABLE : STD_LOGIC;

SIGNAL PIA_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL PIA_IRQA : STD_LOGIC;

SIGNAL PIA_IRQB : STD_LOGIC;

SIGNAL PIA_READ_ENABLE : STD_LOGIC;

SIGNAL PIA_WRITE_ENABLE : STD_LOGIC;

SIGNAL PLL_LOCKED : STD_LOGIC;

SIGNAL POKEY2_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL CACHE_POKEY2_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL POKEY2_WRITE_ENABLE : STD_LOGIC;

SIGNAL POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL CACHE_POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL POKEY_ENABLE_179 : STD_LOGIC;

SIGNAL POKEY_IRQ : STD_LOGIC;

SIGNAL POKEY_WRITE_ENABLE : STD_LOGIC;

SIGNAL PORTA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL PORTA_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL PORTB_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL PORTB_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL POT_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL POT_RESET : STD_LOGIC;

SIGNAL R_W_N : STD_LOGIC;

SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(18 DOWNTO 0);

SIGNAL RAM_DO : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL RAM_REQUEST : STD_LOGIC;

SIGNAL RAM_REQUEST_COMPLETE : STD_LOGIC;

SIGNAL RAM_SELECT : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL RAM_WRITE_ENABLE : STD_LOGIC;

SIGNAL RESET_N : STD_LOGIC;

SIGNAL ROM_ADDR : STD_LOGIC_VECTOR(21 DOWNTO 0);

SIGNAL ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL ROM_REQUEST : STD_LOGIC;

SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;

SIGNAL ROM_SELECT : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SCANDOUBLER_SHARED_ENABLE_HIGH : STD_LOGIC;

SIGNAL SCANDOUBLER_SHARED_ENABLE_LOW : STD_LOGIC;

SIGNAL SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);

SIGNAL SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL SDRAM_READ_ENABLE : STD_LOGIC;

SIGNAL SDRAM_REFRESH : STD_LOGIC;

--SIGNAL SDRAM_REPLY : STD_LOGIC;

SIGNAL SDRAM_REQUEST_COMPLETE : STD_LOGIC;

SIGNAL SDRAM_REQUEST : STD_LOGIC;

SIGNAL SDRAM_WRITE_ENABLE : STD_LOGIC;

SIGNAL SHIFT_PRESSED : STD_LOGIC;

SIGNAL SIO_COMMAND_OUT : STD_LOGIC;

SIGNAL SIO_DATA_IN : STD_LOGIC;

SIGNAL SIO_DATA_OUT : STD_LOGIC;

SIGNAL SYNC_KEYS : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNC_SWITCHES : STD_LOGIC_VECTOR(9 DOWNTO 0);

SIGNAL SYSTEM_RESET_REQUEST : STD_LOGIC;

SIGNAL THROTTLE_COUNT_6502 : STD_LOGIC_VECTOR(5 DOWNTO 0);

SIGNAL TRIGGERS : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL USE_SDRAM : STD_LOGIC;

SIGNAL VGA : STD_LOGIC;

SIGNAL VIRTUAL_STICKS : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL VIRTUAL_TRIGGERS : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL VIRTUAL_KEYS : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL WIDTH_16BIT_ACCESS : STD_LOGIC;

SIGNAL WIDTH_32BIT_ACCESS : STD_LOGIC;

SIGNAL WIDTH_8BIT_ACCESS : STD_LOGIC;

SIGNAL WRITE_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL ZPU_16BIT_WRITE_ENABLE : STD_LOGIC;

SIGNAL ZPU_32BIT_WRITE_ENABLE : STD_LOGIC;

SIGNAL ZPU_8BIT_WRITE_ENABLE : STD_LOGIC;

SIGNAL ZPU_ADDR_FETCH : STD_LOGIC_VECTOR(23 DOWNTO 0);

SIGNAL ZPU_ADDR_ROM_RAM : STD_LOGIC_VECTOR(23 DOWNTO 0);

SIGNAL ZPU_CONFIG_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL ZPU_CONFIG_WRITE_ENABLE : STD_LOGIC;

SIGNAL ZPU_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL ZPU_FETCH : STD_LOGIC;

SIGNAL ZPU_HEX : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL ZPU_PAUSE : STD_LOGIC;

SIGNAL ZPU_RAM_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL ZPU_READ_ENABLE : STD_LOGIC;

SIGNAL ZPU_RESET : STD_LOGIC;

SIGNAL ZPU_ROM_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL ZPU_SECTOR_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL ZPU_STACK_WRITE : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;

SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;

SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC;

SIGNAL SYNTHESIZED_WIRE_11 : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;

SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;

SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL LEDR_dummy : STD_LOGIC_VECTOR(9 DOWNTO 0);

SIGNAL LEDG_dummy : STD_LOGIC_VECTOR(7 DOWNTO 0);

signal UART_TXD_dummy : std_logic;

-- STUB OUT FOR NOW

SIGNAL PS2K_CLK : STD_LOGIC;

SIGNAL PS2K_DAT : STD_LOGIC;

signal JOY1_n : STD_LOGIC_VECTOR(5 DOWNTO 0);

signal JOY2_n : STD_LOGIC_VECTOR(5 DOWNTO 0);

signal JOY1 : STD_LOGIC_VECTOR(5 DOWNTO 0);

signal JOY2 : STD_LOGIC_VECTOR(5 DOWNTO 0);

SIGNAL SD_DAT0 : STD_LOGIC;

SIGNAL SD_CLK : STD_LOGIC;

SIGNAL SD_CMD : STD_LOGIC;

SIGNAL SD_DAT3 : STD_LOGIC;

signal mist_buttons : std_logic_vector(1 downto 0);

signal mist_switches : std_logic_vector(1 downto 0);

signal keyboard : std_logic_vector(127 downto 0);

signal atari_keyboard : std_logic_vector(63 downto 0);

SIGNAL SHIFT_PRESSED_DUMMY : STD_LOGIC;

SIGNAL BREAK_PRESSED_DUMMY : STD_LOGIC;

SIGNAL CONTROL_PRESSED : STD_LOGIC;

SIGNAL CONSOL_OPTION_DUMMY : STD_LOGIC;

SIGNAL CONSOL_SELECT_DUMMY : STD_LOGIC;

SIGNAL CONSOL_START_DUMMY : STD_LOGIC;

signal capslock_pressed : std_logic;

signal capsheld_next : std_logic;

signal capsheld_reg : std_logic;

signal mist_sector_ready : std_logic;

signal mist_sector_ready_sync : std_logic;

signal mist_sector_request : std_logic;

signal mist_sector_request_sync : std_logic;

signal mist_sector : std_logic_vector(31 downto 0);

signal mist_sector_sync : std_logic_vector(31 downto 0);

signal mist_addr : std_logic_vector(8 downto 0);

signal mist_do : std_logic_vector(7 downto 0);

signal mist_di : std_logic_vector(7 downto 0);

signal mist_wren : std_logic;

signal spi_miso_data : std_logic;

signal spi_miso_io : std_logic;

signal covox_write_enable : std_logic;

signal covox_channel0 : std_logic_vector(7 downto 0);

signal covox_channel1 : std_logic_vector(7 downto 0);

signal covox_channel2 : std_logic_vector(7 downto 0);

signal covox_channel3 : std_logic_vector(7 downto 0);

BEGIN

-- mist spi io

mist_spi_interface : data_io

PORT map

(

CLK =>spi_sck,

RESET_n =>reset_n,

-- SPI connection - up to upstream to make miso 'Z' on ss_io going high

SPI_CLK =>spi_sck,

SPI_SS_IO => spi_ss2,