Revision 1422
Added by markw 10 months ago
| pll.vhd | ||
|---|---|---|
|
-- altpll
|
||
|
--
|
||
|
-- Simulation Library Files(s):
|
||
|
-- altera_mf
|
||
|
--
|
||
|
-- ============================================================
|
||
|
-- ************************************************************
|
||
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||
|
--
|
||
|
-- 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||
|
-- 23.1std.1 Build 993 05/14/2024 SC Lite Edition
|
||
|
-- ************************************************************
|
||
|
|
||
|
|
||
|
--Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||
|
--Copyright (C) 2024 Intel Corporation. All rights reserved.
|
||
|
--Your use of Intel Corporation's design tools, logic functions
|
||
|
--and other software and tools, and any partner logic
|
||
|
--functions, and any output files from any of the foregoing
|
||
| ... | ... | |
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
|
||
|
-- Retrieval info: LIB_FILE: altera_mf
|
||
|
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||
Also available in: Unified diff
Updated ip to quartus v23 version