Index: atari_chips/pokeyv2/flash_16/flash/flash_generation.rpt
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/flash_generation.rpt	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/flash_generation.rpt	(revision 1422)
@@ -1,8 +1,42 @@
+Info: Starting: Create simulation model
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation --family="MAX 10" --part=10M16SCU169C8G
+Progress: Loading build_10M16_monov2/flash.qsys
+Progress: Reading input file
+Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
+Progress: Parameterizing module onchip_flash_0
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: flash: Generating flash "flash" for SIM_VHDL
+Info: onchip_flash_0: "flash" instantiated altera_onchip_flash "onchip_flash_0"
+Info: flash: Done "flash" with 2 modules, 5 files
+Info: qsys-generate succeeded.
+Info: Finished: Create simulation model
+Info: Starting: Create Modelsim Project.
+Info: sim-script-gen --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ --use-relative-paths=true
+Info: Doing: ip-make-simscript --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ --use-relative-paths=true
+Info: Generating the following file(s) for VCSMX simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ directory:
+Info: 	synopsys/vcsmx/synopsys_sim.setup
+Info: 	synopsys/vcsmx/vcsmx_setup.sh
+Info: Generating the following file(s) for MODELSIM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ directory:
+Info: 	mentor/msim_setup.tcl
+Info: Generating the following file(s) for XCELIUM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ directory:
+Info: 	xcelium/cds.lib
+Info: 	xcelium/hdl.var
+Info: 	xcelium/xcelium_setup.sh
+Info: 	1 .cds.lib files in xcelium/cds_libs/ directory
+Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
+Info: Generating the following file(s) for RIVIERA simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ directory:
+Info: 	aldec/rivierapro_setup.tcl
+Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/.
+Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
+Info: Finished: Create Modelsim Project.
 Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash --family="MAX 10" --part=10M16SCU169C8G
-Progress: Loading build_10M16_fullv2/flash.qsys
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash --family="MAX 10" --part=10M16SCU169C8G
+Progress: Loading build_10M16_monov2/flash.qsys
 Progress: Reading input file
-Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
+Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
 Progress: Parameterizing module onchip_flash_0
 Progress: Building connections
 Progress: Parameterizing connections
@@ -12,10 +46,10 @@
 Info: Finished: Create block symbol file (.bsf)
 Info: 
 Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis --family="MAX 10" --part=10M16SCU169C8G
-Progress: Loading build_10M16_fullv2/flash.qsys
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis --family="MAX 10" --part=10M16SCU169C8G
+Progress: Loading build_10M16_monov2/flash.qsys
 Progress: Reading input file
-Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
+Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
 Progress: Parameterizing module onchip_flash_0
 Progress: Building connections
 Progress: Parameterizing connections
Index: atari_chips/pokeyv2/flash_16/flash/synthesis/flash.vhd
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/synthesis/flash.vhd	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/synthesis/flash.vhd	(revision 1422)
@@ -1,6 +1,6 @@
 -- flash.vhd
 
--- Generated using ACDS version 19.1 670
+-- Generated using ACDS version 23.1 993
 
 library IEEE;
 use IEEE.std_logic_1164.all;
Index: atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2019 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2020 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_util.v
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_util.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_util.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2020 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_08/flash.qsys
===================================================================
--- atari_chips/pokeyv2/flash_08/flash.qsys	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash.qsys	(revision 1422)
@@ -64,7 +64,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="20.1"
+   version="23.1"
    enabled="1"
    autoexport="1">
   <parameter name="AUTO_CLOCK_RATE" value="0" />
Index: atari_chips/pokeyv2/flash_16/flash/flash.bsf
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/flash.bsf	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/flash.bsf	(revision 1422)
@@ -4,7 +4,7 @@
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2024  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
Index: atari_chips/pokeyv2/flash_16/flash/flash.xml
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/flash.xml	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/flash.xml	(revision 1422)
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <deploy
- date="2020.11.14.09:21:06"
- outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/">
+ date="2024.08.31.14:38:21"
+ outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/">
  <perimeter>
   <parameter
      name="AUTO_GENERATION_ID"
@@ -184,13 +184,13 @@
  </perimeter>
  <entity
    path=""
-   parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M16SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1605342065,AUTO_UNIQUE_ID=(altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=1024,ADDR_RANGE2_END_ADDR=104447,ADDR_RANGE2_OFFSET=39936,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=17,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=16,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=104447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M16SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=36863,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=104447,SECTOR4_MAP=5,SECTOR4_START_ADDR=36864,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x23fff,0x24000 - 0x65fff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
+   parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M16SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1725107901,AUTO_UNIQUE_ID=(altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=1024,ADDR_RANGE2_END_ADDR=104447,ADDR_RANGE2_OFFSET=39936,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=17,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=16,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=104447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M16SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=36863,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=104447,SECTOR4_MAP=5,SECTOR4_START_ADDR=36864,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x23fff,0x24000 - 0x65fff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
    instancePathKey="flash"
    kind="flash"
    version="1.0"
    name="flash">
   <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_GENERATION_ID" value="1605342065" />
+  <parameter name="AUTO_GENERATION_ID" value="1725107901" />
   <parameter name="AUTO_DEVICE" value="10M16SCU169C8G" />
   <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
   <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
@@ -199,42 +199,42 @@
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
   <generatedFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/flash.vhd"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/flash.vhd"
        type="VHDL" />
   </generatedFiles>
   <childGeneratedFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_util.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_util.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash.sdc"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash.sdc"
        type="SDC"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
        type="VERILOG"
        attributes="" />
   </childGeneratedFiles>
   <sourceFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash.qsys" />
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash.qsys" />
   </sourceFiles>
   <childSourceFiles>
    <file
-       path="/home/markw/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
+       path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
   </childSourceFiles>
   <messages>
    <message level="Debug" culprit="flash">queue size: 0 starting:flash "flash"</message>
@@ -258,10 +258,10 @@
  </entity>
  <entity
    path="submodules/"
-   parameterizationKey="altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=1024,ADDR_RANGE2_END_ADDR=104447,ADDR_RANGE2_OFFSET=39936,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=17,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=16,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=104447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M16SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=36863,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=104447,SECTOR4_MAP=5,SECTOR4_START_ADDR=36864,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x23fff,0x24000 - 0x65fff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
+   parameterizationKey="altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=1024,ADDR_RANGE2_END_ADDR=104447,ADDR_RANGE2_OFFSET=39936,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=17,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=16,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=104447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M16SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=36863,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=104447,SECTOR4_MAP=5,SECTOR4_START_ADDR=36864,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x23fff,0x24000 - 0x65fff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
    instancePathKey="flash:.:onchip_flash_0"
    kind="altera_onchip_flash"
-   version="19.1"
+   version="23.1"
    name="altera_onchip_flash">
   <parameter name="SECTOR_READ_PROTECTION_MODE" value="16" />
   <parameter name="MIN_UFM_VALID_ADDR" value="0" />
@@ -331,27 +331,27 @@
   <parameter name="IS_DUAL_BOOT" value="False" />
   <generatedFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_util.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_util.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash.sdc"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash.sdc"
        type="SDC"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
        type="VERILOG"
        attributes="" />
   </generatedFiles>
@@ -358,7 +358,7 @@
   <childGeneratedFiles/>
   <sourceFiles>
    <file
-       path="/home/markw/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
+       path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
   </sourceFiles>
   <childSourceFiles/>
   <instantiator instantiator="flash" as="onchip_flash_0" />
Index: atari_chips/pokeyv2/flash_16/flash/synthesis/flash.qip
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/synthesis/flash.qip	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/synthesis/flash.qip	(revision 1422)
@@ -1,8 +1,8 @@
 set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_NAME "Qsys"
-set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "flash" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../flash.sopcinfo"]
-set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1605342065"
+set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1725107901"
 set_global_assignment -library "flash" -name MISC_FILE [file join $::quartus(qip_path) "../flash.cmp"]
 set_global_assignment -library "flash" -name SLD_FILE [file join $::quartus(qip_path) "flash.debuginfo"]
 set_global_assignment -entity "flash" -library "flash" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -15,7 +15,7 @@
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYwNTM0MjA2NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyNTEwNzkwMQ==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMTZTQ1UxNjlDOEc=::QXV0byBERVZJQ0U="
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -28,7 +28,7 @@
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MjMuMQ=="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE9uLUNoaXAgRmxhc2ggTWVnYWZ1bmN0aW9uIHdpdGggQXZhbG9uLU1NIFNsYXZlIEludGVyZmFjZS4="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "REFUQV9JTlRFUkZBQ0U=::UGFyYWxsZWw=::RGF0YSBpbnRlcmZhY2U="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "UkVBRF9CVVJTVF9NT0RF::SW5jcmVtZW50aW5n::UmVhZCBidXJzdCBtb2Rl"
@@ -91,5 +91,5 @@
 set_global_assignment -library "flash" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rtl/altera_onchip_flash_block.v"]
 
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_NAME "altera_onchip_flash"
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_ENV "Qsys"
Index: atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash.v
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2019 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_util.v
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_util.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_util.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2019 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_04/flash/flash.bsf
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/flash.bsf	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/flash.bsf	(revision 1422)
@@ -4,7 +4,7 @@
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2024  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
Index: atari_chips/pokeyv2/flash_04/flash/flash.html
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/flash.html	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/flash.html	(revision 1422)
@@ -67,7 +67,7 @@
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2020.06.18.10:29:34</td>
+    <td class="l">2024.08.31.14:41:48</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -85,7 +85,7 @@
      <br/>All Components
      <br/>&#160;&#160;
      <a href="#module_onchip_flash_0"><b>onchip_flash_0</b>
-     </a> altera_onchip_flash 19.1</span>
+     </a> altera_onchip_flash 23.1</span>
    </div>
   </div>
   <div style="width:100% ;  height:10px"> </div>
@@ -110,7 +110,7 @@
   <a name="module_onchip_flash_0"> </a>
   <div>
    <hr/>
-   <h2>onchip_flash_0</h2>altera_onchip_flash v19.1
+   <h2>onchip_flash_0</h2>altera_onchip_flash v23.1
    <br/>
    <br/>
    <br/>
@@ -460,7 +460,7 @@
   <table class="blueBar">
    <tr>
     <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0.01 seconds</td>
+    <td class="r">rendering took 0.00 seconds</td>
    </tr>
   </table>
  </body>
Index: atari_chips/pokeyv2/flash_04/flash/flash.xml
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/flash.xml	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/flash.xml	(revision 1422)
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <deploy
- date="2020.06.18.10:29:34"
- outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/">
+ date="2024.08.31.14:41:48"
+ outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/">
  <perimeter>
   <parameter
      name="AUTO_GENERATION_ID"
@@ -184,13 +184,13 @@
  </perimeter>
  <entity
    path=""
-   parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M04SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1592468974,AUTO_UNIQUE_ID=(altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=4095,ADDR_RANGE1_OFFSET=4608,ADDR_RANGE2_END_ADDR=54783,ADDR_RANGE2_OFFSET=25600,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=04,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=4095,MAX_VALID_ADDR=54783,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M04SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=2,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=18943,SECTOR2_MAP=4,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=54783,SECTOR3_MAP=5,SECTOR3_START_ADDR=18944,SECTOR4_END_ADDR=0,SECTOR4_MAP=0,SECTOR4_START_ADDR=0,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=NA,0x00000 - 0x03fff,NA,0x04000 - 0x127ff,0x12800 - 0x357ff,SECTOR_ID=NA,1,NA,2,3,SECTOR_READ_PROTECTION_MODE=24,SECTOR_STORAGE_TYPE=NA,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
+   parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M04SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1725108108,AUTO_UNIQUE_ID=(altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=4095,ADDR_RANGE1_OFFSET=4608,ADDR_RANGE2_END_ADDR=54783,ADDR_RANGE2_OFFSET=25600,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=04,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=4095,MAX_VALID_ADDR=54783,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M04SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=2,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=18943,SECTOR2_MAP=4,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=54783,SECTOR3_MAP=5,SECTOR3_START_ADDR=18944,SECTOR4_END_ADDR=0,SECTOR4_MAP=0,SECTOR4_START_ADDR=0,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=NA,0x00000 - 0x03fff,NA,0x04000 - 0x127ff,0x12800 - 0x357ff,SECTOR_ID=NA,1,NA,2,3,SECTOR_READ_PROTECTION_MODE=24,SECTOR_STORAGE_TYPE=NA,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
    instancePathKey="flash"
    kind="flash"
    version="1.0"
    name="flash">
   <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_GENERATION_ID" value="1592468974" />
+  <parameter name="AUTO_GENERATION_ID" value="1725108108" />
   <parameter name="AUTO_DEVICE" value="10M04SCU169C8G" />
   <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
   <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
@@ -199,42 +199,42 @@
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
   <generatedFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/flash.vhd"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/flash.vhd"
        type="VHDL" />
   </generatedFiles>
   <childGeneratedFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_util.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_util.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash.sdc"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash.sdc"
        type="SDC"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
        type="VERILOG"
        attributes="" />
   </childGeneratedFiles>
   <sourceFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys" />
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash.qsys" />
   </sourceFiles>
   <childSourceFiles>
    <file
-       path="/home/markw/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
+       path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
   </childSourceFiles>
   <messages>
    <message level="Debug" culprit="flash">queue size: 0 starting:flash "flash"</message>
@@ -258,10 +258,10 @@
  </entity>
  <entity
    path="submodules/"
-   parameterizationKey="altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=4095,ADDR_RANGE1_OFFSET=4608,ADDR_RANGE2_END_ADDR=54783,ADDR_RANGE2_OFFSET=25600,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=04,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=4095,MAX_VALID_ADDR=54783,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M04SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=2,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=18943,SECTOR2_MAP=4,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=54783,SECTOR3_MAP=5,SECTOR3_START_ADDR=18944,SECTOR4_END_ADDR=0,SECTOR4_MAP=0,SECTOR4_START_ADDR=0,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=NA,0x00000 - 0x03fff,NA,0x04000 - 0x127ff,0x12800 - 0x357ff,SECTOR_ID=NA,1,NA,2,3,SECTOR_READ_PROTECTION_MODE=24,SECTOR_STORAGE_TYPE=NA,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
+   parameterizationKey="altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=4095,ADDR_RANGE1_OFFSET=4608,ADDR_RANGE2_END_ADDR=54783,ADDR_RANGE2_OFFSET=25600,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=04,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=4095,MAX_VALID_ADDR=54783,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M04SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=2,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=18943,SECTOR2_MAP=4,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=54783,SECTOR3_MAP=5,SECTOR3_START_ADDR=18944,SECTOR4_END_ADDR=0,SECTOR4_MAP=0,SECTOR4_START_ADDR=0,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=NA,0x00000 - 0x03fff,NA,0x04000 - 0x127ff,0x12800 - 0x357ff,SECTOR_ID=NA,1,NA,2,3,SECTOR_READ_PROTECTION_MODE=24,SECTOR_STORAGE_TYPE=NA,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
    instancePathKey="flash:.:onchip_flash_0"
    kind="altera_onchip_flash"
-   version="19.1"
+   version="23.1"
    name="altera_onchip_flash">
   <parameter name="SECTOR_READ_PROTECTION_MODE" value="24" />
   <parameter name="MIN_UFM_VALID_ADDR" value="0" />
@@ -331,27 +331,27 @@
   <parameter name="IS_DUAL_BOOT" value="False" />
   <generatedFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_util.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_util.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash.sdc"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash.sdc"
        type="SDC"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
        type="VERILOG"
        attributes="" />
   </generatedFiles>
@@ -358,7 +358,7 @@
   <childGeneratedFiles/>
   <sourceFiles>
    <file
-       path="/home/markw/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
+       path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
   </sourceFiles>
   <childSourceFiles/>
   <instantiator instantiator="flash" as="onchip_flash_0" />
Index: atari_chips/pokeyv2/flash_04/flash/flash_generation.rpt
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/flash_generation.rpt	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/flash_generation.rpt	(revision 1422)
@@ -1,8 +1,42 @@
+Info: Starting: Create simulation model
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation --family="MAX 10" --part=10M04SCU169C8G
+Progress: Loading build_10M04_quad_auto_v3/flash.qsys
+Progress: Reading input file
+Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
+Progress: Parameterizing module onchip_flash_0
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: flash: Generating flash "flash" for SIM_VHDL
+Info: onchip_flash_0: "flash" instantiated altera_onchip_flash "onchip_flash_0"
+Info: flash: Done "flash" with 2 modules, 5 files
+Info: qsys-generate succeeded.
+Info: Finished: Create simulation model
+Info: Starting: Create Modelsim Project.
+Info: sim-script-gen --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ --use-relative-paths=true
+Info: Doing: ip-make-simscript --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ --use-relative-paths=true
+Info: Generating the following file(s) for MODELSIM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ directory:
+Info: 	mentor/msim_setup.tcl
+Info: Generating the following file(s) for VCSMX simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ directory:
+Info: 	synopsys/vcsmx/synopsys_sim.setup
+Info: 	synopsys/vcsmx/vcsmx_setup.sh
+Info: Generating the following file(s) for RIVIERA simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ directory:
+Info: 	aldec/rivierapro_setup.tcl
+Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
+Info: Generating the following file(s) for XCELIUM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ directory:
+Info: 	xcelium/cds.lib
+Info: 	xcelium/hdl.var
+Info: 	xcelium/xcelium_setup.sh
+Info: 	1 .cds.lib files in xcelium/cds_libs/ directory
+Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/.
+Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
+Info: Finished: Create Modelsim Project.
 Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash --family="MAX 10" --part=10M04SCU169C8G
-Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash --family="MAX 10" --part=10M04SCU169C8G
+Progress: Loading build_10M04_quad_auto_v3/flash.qsys
 Progress: Reading input file
-Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
+Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
 Progress: Parameterizing module onchip_flash_0
 Progress: Building connections
 Progress: Parameterizing connections
@@ -12,10 +46,10 @@
 Info: Finished: Create block symbol file (.bsf)
 Info: 
 Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis --family="MAX 10" --part=10M04SCU169C8G
-Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis --family="MAX 10" --part=10M04SCU169C8G
+Progress: Loading build_10M04_quad_auto_v3/flash.qsys
 Progress: Reading input file
-Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
+Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
 Progress: Parameterizing module onchip_flash_0
 Progress: Building connections
 Progress: Parameterizing connections
Index: atari_chips/pokeyv2/flash_04/flash/flash_generation_previous.rpt
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/flash_generation_previous.rpt	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/flash_generation_previous.rpt	(revision 1422)
@@ -1,6 +1,6 @@
 Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_quad_sid/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_quad_sid/flash --family="MAX 10" --part=10M08SCU169C8G
-Progress: Loading build_10M08_quad_sid/flash.qsys
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash --family="MAX 10" --part=10M04SCU169C8G
+Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
 Progress: Reading input file
 Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
 Progress: Parameterizing module onchip_flash_0
@@ -12,8 +12,8 @@
 Info: Finished: Create block symbol file (.bsf)
 Info: 
 Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_quad_sid/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_quad_sid/flash/synthesis --family="MAX 10" --part=10M08SCU169C8G
-Progress: Loading build_10M08_quad_sid/flash.qsys
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis --family="MAX 10" --part=10M04SCU169C8G
+Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
 Progress: Reading input file
 Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
 Progress: Parameterizing module onchip_flash_0
Index: atari_chips/pokeyv2/flash_04/flash/synthesis/flash.debuginfo
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/synthesis/flash.debuginfo	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/synthesis/flash.debuginfo	(revision 1422)
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport name="flash" kind="system" version="19.1" fabric="QSYS">
- <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
- <!-- 2020.06.18.10:29:34 -->
+<EnsembleReport name="flash" kind="system" version="23.1" fabric="QSYS">
+ <!-- Format version 23.1 993 (Future versions may contain additional information.) -->
+ <!-- 2024.08.31.14:41:48 -->
  <!-- A collection of modules and connections -->
  <parameter name="clockCrossingAdapter">
   <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -53,7 +53,7 @@
  </parameter>
  <parameter name="generationId">
   <type>int</type>
-  <value>1592468974</value>
+  <value>1725108108</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
@@ -150,7 +150,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="19.1"
+   version="23.1"
    path="onchip_flash_0">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -787,7 +787,7 @@
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk" kind="clock_sink" version="19.1">
+  <interface name="clk" kind="clock_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -848,7 +848,7 @@
     <role>clk</role>
    </port>
   </interface>
-  <interface name="nreset" kind="reset_sink" version="19.1">
+  <interface name="nreset" kind="reset_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -893,7 +893,7 @@
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="data" kind="avalon_slave" version="19.1">
+  <interface name="data" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1276,7 +1276,7 @@
     <role>burstcount</role>
    </port>
   </interface>
-  <interface name="csr" kind="avalon_slave" version="19.1">
+  <interface name="csr" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1648,7 +1648,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>On-Chip Flash Intel FPGA IP</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1656,7 +1656,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Input</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1664,7 +1664,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Input</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -1672,8 +1672,8 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Avalon Memory Mapped Slave</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
- <reportVersion>19.1 670</reportVersion>
- <uniqueIdentifier>F44D30F4F5CE00000172C68C2D62</uniqueIdentifier>
+ <reportVersion>23.1 993</reportVersion>
+ <uniqueIdentifier>02424E4C123F00000191A874BC9A</uniqueIdentifier>
 </EnsembleReport>
Index: atari_chips/pokeyv2/flash_04/flash/synthesis/flash.qip
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/synthesis/flash.qip	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/synthesis/flash.qip	(revision 1422)
@@ -1,8 +1,8 @@
 set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_NAME "Qsys"
-set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "flash" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../flash.sopcinfo"]
-set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1592468974"
+set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1725108108"
 set_global_assignment -library "flash" -name MISC_FILE [file join $::quartus(qip_path) "../flash.cmp"]
 set_global_assignment -library "flash" -name SLD_FILE [file join $::quartus(qip_path) "flash.debuginfo"]
 set_global_assignment -entity "flash" -library "flash" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -15,7 +15,7 @@
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU5MjQ2ODk3NA==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyNTEwODEwOA==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDRTQ1UxNjlDOEc=::QXV0byBERVZJQ0U="
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -28,7 +28,7 @@
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MjMuMQ=="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE9uLUNoaXAgRmxhc2ggTWVnYWZ1bmN0aW9uIHdpdGggQXZhbG9uLU1NIFNsYXZlIEludGVyZmFjZS4="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "REFUQV9JTlRFUkZBQ0U=::UGFyYWxsZWw=::RGF0YSBpbnRlcmZhY2U="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "UkVBRF9CVVJTVF9NT0RF::SW5jcmVtZW50aW5n::UmVhZCBidXJzdCBtb2Rl"
@@ -89,5 +89,5 @@
 set_global_assignment -library "flash" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rtl/altera_onchip_flash_block.v"]
 
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_NAME "altera_onchip_flash"
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_ENV "Qsys"
Index: atari_chips/pokeyv2/flash_04/flash/synthesis/flash.vhd
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/synthesis/flash.vhd	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/synthesis/flash.vhd	(revision 1422)
@@ -1,6 +1,6 @@
 -- flash.vhd
 
--- Generated using ACDS version 19.1 670
+-- Generated using ACDS version 23.1 993
 
 library IEEE;
 use IEEE.std_logic_1164.all;
Index: atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash.sdc
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash.sdc	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash.sdc	(revision 1422)
@@ -1,4 +1,4 @@
-# (C) 2001-2019 Intel Corporation. All rights reserved.
+# (C) 2001-2024 Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions and other 
 # software and tools, and its AMPP partner logic functions, and any output 
 # files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash.v
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2019 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2019 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2019 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
@@ -217,7 +217,6 @@
     reg flash_drdin_neg_reg;
     reg [15:0] write_count;
     reg [25:0] erase_count;
-    reg [2:0] read_count;
     reg [2:0] read_ctrl_count;
     reg [2:0] data_count;
     reg write_timeout;
@@ -331,8 +330,8 @@
     generate // generate combi based on read burst mode
         if (WRAPPING_BURST_MODE == 0) begin
             // incrementing read
-            //assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
-            assign flash_read_addr = avmm_addr; // intel ufm read bug fix 'Is there a known issue with the MAX 10 On Chip Flash IP, for UFM read operations?'
+            assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
+            //assign flash_read_addr = avmm_addr; // intel ufm read bug fix 'Is there a known issue with the MAX 10 On Chip Flash IP, for UFM read operations?'
             assign cur_e_addr = csr_sector_erase_addr;
             assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
             assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
@@ -422,7 +421,6 @@
         reset_n_reg2 = 0;
         read_wait = 0;
         read_wait_neg = 0;
-        read_count = 0;
         is_sector1_writable_reg = 0;
         is_sector2_writable_reg = 0;
         is_sector3_writable_reg = 0;
@@ -599,6 +597,7 @@
                 if (~reset_n_w) begin
                     write_state <= WRITE_STATE_IDLE;
                     write_wait <= 0;
+                    csr_status_w_pass <= 1'b0;
                 end
                 else begin
                     case (write_state)
@@ -614,6 +613,7 @@
                                 if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
                                     write_state <= WRITE_STATE_ADDR;
                                     write_wait <= 1;
+                                    csr_status_w_pass <= 1'b0;
                                 end
                             end
                         end
@@ -723,6 +723,7 @@
             always @ (posedge clock) begin
                 if (~reset_n_w) begin
                     erase_state <= ERASE_STATE_IDLE;
+                    csr_status_e_pass <= 1'b0;
                 end
                 else begin
                     case (erase_state)
@@ -736,6 +737,7 @@
                             // check command
                             if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
                                 erase_state <= ERASE_STATE_ADDR;
+                                csr_status_e_pass <= 1'b0;
                             end
                         end
 
@@ -829,6 +831,7 @@
                 if (~reset_n_w) begin
                     read_state <= READ_STATE_IDLE;
                     read_wait <= 0;
+                    csr_status_r_pass <= 0;
                 end
                 else begin
                     case (read_state)
@@ -851,6 +854,7 @@
                                     read_state <= READ_STATE_ADDR;
                                     flash_seq_read_ardin <= avmm_addr;
                                     avmm_burstcount_input_reg <= avmm_burstcount;
+                                    csr_status_r_pass <= 0;
                                 end
                             end
                         end
@@ -940,10 +944,14 @@
             // -------------------------------------------------------------------
             // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
             // -------------------------------------------------------------------        
+            
+            reg [2:0] read_count;
+            
             always @ (posedge clock) begin
                 if (~reset_n_w) begin
                     read_state <= READ_STATE_IDLE;
                     read_wait <= 0;
+                    read_count <= 3'd0;
                 end
                 else begin
                     case (read_state)
Index: atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_util.v
===================================================================
--- atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_util.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_util.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2019 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: atari_chips/pokeyv2/flash_04/flash.qsys
===================================================================
--- atari_chips/pokeyv2/flash_04/flash.qsys	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash.qsys	(revision 1422)
@@ -6,7 +6,7 @@
    version="1.0"
    description=""
    tags="INTERNAL_COMPONENT=true"
-   categories="" />
+   categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
    element onchip_flash_0
@@ -64,7 +64,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="19.1"
+   version="23.1"
    enabled="1"
    autoexport="1">
   <parameter name="AUTO_CLOCK_RATE" value="0" />
Index: atari_chips/pokeyv2/flash_04/flash.sopcinfo
===================================================================
--- atari_chips/pokeyv2/flash_04/flash.sopcinfo	(revision 1421)
+++ atari_chips/pokeyv2/flash_04/flash.sopcinfo	(revision 1422)
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="flash" kind="flash" version="1.0" fabric="QSYS">
- <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
- <!-- 2020.06.18.10:30:08 -->
+ <!-- Format version 23.1 993 (Future versions may contain additional information.) -->
+ <!-- 2024.08.31.14:41:48 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1592469008</value>
+  <value>1725108108</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -98,7 +98,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="19.1"
+   version="23.1"
    path="onchip_flash_0">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -735,7 +735,7 @@
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk" kind="clock_sink" version="19.1">
+  <interface name="clk" kind="clock_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -796,7 +796,7 @@
     <role>clk</role>
    </port>
   </interface>
-  <interface name="nreset" kind="reset_sink" version="19.1">
+  <interface name="nreset" kind="reset_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -841,7 +841,7 @@
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="data" kind="avalon_slave" version="19.1">
+  <interface name="data" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1224,7 +1224,7 @@
     <role>burstcount</role>
    </port>
   </interface>
-  <interface name="csr" kind="avalon_slave" version="19.1">
+  <interface name="csr" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1596,7 +1596,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>On-Chip Flash Intel FPGA IP</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1604,7 +1604,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Input</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1612,7 +1612,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Input</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -1620,8 +1620,8 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Avalon Memory Mapped Slave</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
- <reportVersion>19.1 670</reportVersion>
+ <reportVersion>23.1 993</reportVersion>
  <uniqueIdentifier></uniqueIdentifier>
 </EnsembleReport>
Index: atari_chips/pokeyv2/flash_08/flash/flash.bsf
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/flash.bsf	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/flash.bsf	(revision 1422)
@@ -4,7 +4,7 @@
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2020  Intel Corporation. All rights reserved.
+Copyright (C) 2024  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
Index: atari_chips/pokeyv2/flash_08/flash/flash.html
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/flash.html	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/flash.html	(revision 1422)
@@ -67,7 +67,7 @@
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2021.01.13.14:03:24</td>
+    <td class="l">2024.08.31.14:17:13</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -85,7 +85,7 @@
      <br/>All Components
      <br/>&#160;&#160;
      <a href="#module_onchip_flash_0"><b>onchip_flash_0</b>
-     </a> altera_onchip_flash 20.1</span>
+     </a> altera_onchip_flash 23.1</span>
    </div>
   </div>
   <div style="width:100% ;  height:10px"> </div>
@@ -110,7 +110,7 @@
   <a name="module_onchip_flash_0"> </a>
   <div>
    <hr/>
-   <h2>onchip_flash_0</h2>altera_onchip_flash v20.1
+   <h2>onchip_flash_0</h2>altera_onchip_flash v23.1
    <br/>
    <br/>
    <br/>
@@ -133,7 +133,7 @@
        </tr>
        <tr>
         <td class="parametername">CLOCK_FREQUENCY</td>
-        <td class="parametervalue">80.0</td>
+        <td class="parametervalue">116.0</td>
        </tr>
        <tr>
         <td class="parametername">CONFIGURATION_SCHEME</td>
@@ -329,19 +329,19 @@
        </tr>
        <tr>
         <td class="parametername">FLASH_RESET_CYCLE_MAX_INDEX</td>
-        <td class="parametervalue">20</td>
+        <td class="parametervalue">29</td>
        </tr>
        <tr>
         <td class="parametername">FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX</td>
-        <td class="parametervalue">96</td>
+        <td class="parametervalue">139</td>
        </tr>
        <tr>
         <td class="parametername">FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX</td>
-        <td class="parametervalue">28000000</td>
+        <td class="parametervalue">40600000</td>
        </tr>
        <tr>
         <td class="parametername">FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX</td>
-        <td class="parametervalue">24400</td>
+        <td class="parametervalue">35380</td>
        </tr>
        <tr>
         <td class="parametername">PARALLEL_MODE</td>
@@ -460,7 +460,7 @@
   <table class="blueBar">
    <tr>
     <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0.02 seconds</td>
+    <td class="r">rendering took 0.01 seconds</td>
    </tr>
   </table>
  </body>
Index: atari_chips/pokeyv2/flash_08/flash/flash.xml
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/flash.xml	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/flash.xml	(revision 1422)
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <deploy
- date="2021.01.13.14:03:24"
- outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/">
+ date="2024.08.31.14:17:13"
+ outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/">
  <perimeter>
   <parameter
      name="AUTO_GENERATION_ID"
@@ -184,13 +184,13 @@
  </perimeter>
  <entity
    path=""
-   parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M08SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1610543004,AUTO_UNIQUE_ID=(altera_onchip_flash:20.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=512,ADDR_RANGE2_END_ADDR=58879,ADDR_RANGE2_OFFSET=21504,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=80.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=96,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=28000000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=20,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=24400,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=58879,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M08SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Wrapping,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=23039,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=58879,SECTOR4_MAP=5,SECTOR4_START_ADDR=23040,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=true,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
+   parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M08SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1725106633,AUTO_UNIQUE_ID=(altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=512,ADDR_RANGE2_END_ADDR=58879,ADDR_RANGE2_OFFSET=21504,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=58879,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M08SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Wrapping,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=23039,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=58879,SECTOR4_MAP=5,SECTOR4_START_ADDR=23040,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=true,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
    instancePathKey="flash"
    kind="flash"
    version="1.0"
    name="flash">
   <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_GENERATION_ID" value="1610543004" />
+  <parameter name="AUTO_GENERATION_ID" value="1725106633" />
   <parameter name="AUTO_DEVICE" value="10M08SCU169C8G" />
   <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
   <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
@@ -199,42 +199,42 @@
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
   <generatedFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/flash.vhd"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/flash.vhd"
        type="VHDL" />
   </generatedFiles>
   <childGeneratedFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_util.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_util.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash.sdc"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash.sdc"
        type="SDC"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
        type="VERILOG"
        attributes="" />
   </childGeneratedFiles>
   <sourceFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash.qsys" />
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash.qsys" />
   </sourceFiles>
   <childSourceFiles>
    <file
-       path="/home/markw/intelFPGA_lite/20.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
+       path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
   </childSourceFiles>
   <messages>
    <message level="Debug" culprit="flash">queue size: 0 starting:flash "flash"</message>
@@ -258,10 +258,10 @@
  </entity>
  <entity
    path="submodules/"
-   parameterizationKey="altera_onchip_flash:20.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=512,ADDR_RANGE2_END_ADDR=58879,ADDR_RANGE2_OFFSET=21504,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=80.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=96,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=28000000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=20,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=24400,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=58879,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M08SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Wrapping,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=23039,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=58879,SECTOR4_MAP=5,SECTOR4_START_ADDR=23040,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=true,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
+   parameterizationKey="altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=512,ADDR_RANGE2_END_ADDR=58879,ADDR_RANGE2_OFFSET=21504,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=58879,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M08SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Wrapping,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=23039,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=58879,SECTOR4_MAP=5,SECTOR4_START_ADDR=23040,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=true,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
    instancePathKey="flash:.:onchip_flash_0"
    kind="altera_onchip_flash"
-   version="20.1"
+   version="23.1"
    name="altera_onchip_flash">
   <parameter name="SECTOR_READ_PROTECTION_MODE" value="16" />
   <parameter name="MIN_UFM_VALID_ADDR" value="0" />
@@ -268,7 +268,7 @@
   <parameter name="AVMM_DATA_ADDR_WIDTH" value="16" />
   <parameter name="SECTOR3_START_ADDR" value="8192" />
   <parameter name="AUTO_CLOCK_RATE" value="0" />
-  <parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX" value="28000000" />
+  <parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX" value="40600000" />
   <parameter name="SECTOR1_END_ADDR" value="4095" />
   <parameter name="SECTOR4_END_ADDR" value="58879" />
   <parameter name="initializationFileNameForSim" value="altera_onchip_flash.dat" />
@@ -288,7 +288,7 @@
   <parameter name="WRAPPING_BURST_MODE" value="true" />
   <parameter name="SECTOR5_MAP" value="0" />
   <parameter name="FLASH_SEQ_READ_DATA_COUNT" value="2" />
-  <parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX" value="24400" />
+  <parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX" value="35380" />
   <parameter name="autoInitializationFileName" value="flash_onchip_flash_0" />
   <parameter name="DEVICE_FAMILY" value="MAX 10" />
   <parameter name="ADDR_RANGE3_OFFSET" value="0" />
@@ -295,7 +295,7 @@
   <parameter name="ADDR_RANGE2_OFFSET" value="21504" />
   <parameter name="SECTOR2_END_ADDR" value="8191" />
   <parameter name="SECTOR4_MAP" value="5" />
-  <parameter name="FLASH_RESET_CYCLE_MAX_INDEX" value="20" />
+  <parameter name="FLASH_RESET_CYCLE_MAX_INDEX" value="29" />
   <parameter
      name="SECTOR_ADDRESS_MAPPING"
      value="0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff" />
@@ -302,7 +302,7 @@
   <parameter name="IS_ERAM_SKIP" value="True" />
   <parameter name="READ_BURST_MODE" value="Wrapping" />
   <parameter name="READ_AND_WRITE_MODE" value="true" />
-  <parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX" value="96" />
+  <parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX" value="139" />
   <parameter name="SECTOR5_START_ADDR" value="0" />
   <parameter name="PART_NAME" value="10M08SCU169C8G" />
   <parameter name="ADDR_RANGE1_OFFSET" value="512" />
@@ -323,7 +323,7 @@
   <parameter name="READ_BURST_COUNT" value="2" />
   <parameter name="FLASH_READ_CYCLE_MAX_INDEX" value="4" />
   <parameter name="AVMM_DATA_BURSTCOUNT_WIDTH" value="2" />
-  <parameter name="CLOCK_FREQUENCY" value="80.0" />
+  <parameter name="CLOCK_FREQUENCY" value="116.0" />
   <parameter name="SECTOR_STORAGE_TYPE" value="UFM,UFM,NA,CFM,CFM" />
   <parameter name="ADDR_RANGE2_END_ADDR" value="58879" />
   <parameter name="SECTOR5_END_ADDR" value="0" />
@@ -331,27 +331,27 @@
   <parameter name="IS_DUAL_BOOT" value="False" />
   <generatedFiles>
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_util.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_util.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
        type="VERILOG"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash.sdc"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash.sdc"
        type="SDC"
        attributes="" />
    <file
-       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
        type="VERILOG"
        attributes="" />
   </generatedFiles>
@@ -358,7 +358,7 @@
   <childGeneratedFiles/>
   <sourceFiles>
    <file
-       path="/home/markw/intelFPGA_lite/20.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
+       path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
   </sourceFiles>
   <childSourceFiles/>
   <instantiator instantiator="flash" as="onchip_flash_0" />
Index: atari_chips/pokeyv2/flash_08/flash/flash_generation.rpt
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/flash_generation.rpt	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/flash_generation.rpt	(revision 1422)
@@ -1,8 +1,42 @@
+Info: Starting: Create simulation model
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation --family="MAX 10" --part=10M08SCU169C8G
+Progress: Loading build_sidmax_10M08_full/flash.qsys
+Progress: Reading input file
+Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
+Progress: Parameterizing module onchip_flash_0
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: flash: Generating flash "flash" for SIM_VHDL
+Info: onchip_flash_0: "flash" instantiated altera_onchip_flash "onchip_flash_0"
+Info: flash: Done "flash" with 2 modules, 5 files
+Info: qsys-generate succeeded.
+Info: Finished: Create simulation model
+Info: Starting: Create Modelsim Project.
+Info: sim-script-gen --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ --use-relative-paths=true
+Info: Doing: ip-make-simscript --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ --use-relative-paths=true
+Info: Generating the following file(s) for XCELIUM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ directory:
+Info: 	xcelium/cds.lib
+Info: 	xcelium/hdl.var
+Info: 	xcelium/xcelium_setup.sh
+Info: 	1 .cds.lib files in xcelium/cds_libs/ directory
+Info: Generating the following file(s) for RIVIERA simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ directory:
+Info: 	aldec/rivierapro_setup.tcl
+Info: Generating the following file(s) for VCSMX simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ directory:
+Info: 	synopsys/vcsmx/synopsys_sim.setup
+Info: 	synopsys/vcsmx/vcsmx_setup.sh
+Info: Generating the following file(s) for MODELSIM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ directory:
+Info: 	mentor/msim_setup.tcl
+Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
+Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/.
+Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
+Info: Finished: Create Modelsim Project.
 Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash --family="MAX 10" --part=10M08SCU169C8G
-Progress: Loading build_burst/flash.qsys
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash --family="MAX 10" --part=10M08SCU169C8G
+Progress: Loading build_sidmax_10M08_full/flash.qsys
 Progress: Reading input file
-Progress: Adding onchip_flash_0 [altera_onchip_flash 20.1]
+Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
 Progress: Parameterizing module onchip_flash_0
 Progress: Building connections
 Progress: Parameterizing connections
@@ -12,10 +46,10 @@
 Info: Finished: Create block symbol file (.bsf)
 Info: 
 Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis --family="MAX 10" --part=10M08SCU169C8G
-Progress: Loading build_burst/flash.qsys
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis --family="MAX 10" --part=10M08SCU169C8G
+Progress: Loading build_sidmax_10M08_full/flash.qsys
 Progress: Reading input file
-Progress: Adding onchip_flash_0 [altera_onchip_flash 20.1]
+Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
 Progress: Parameterizing module onchip_flash_0
 Progress: Building connections
 Progress: Parameterizing connections
Index: atari_chips/pokeyv2/flash_08/flash/synthesis/flash.debuginfo
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/synthesis/flash.debuginfo	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/synthesis/flash.debuginfo	(revision 1422)
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport name="flash" kind="system" version="20.1" fabric="QSYS">
- <!-- Format version 20.1 720 (Future versions may contain additional information.) -->
- <!-- 2021.01.13.14:03:24 -->
+<EnsembleReport name="flash" kind="system" version="23.1" fabric="QSYS">
+ <!-- Format version 23.1 993 (Future versions may contain additional information.) -->
+ <!-- 2024.08.31.14:17:13 -->
  <!-- A collection of modules and connections -->
  <parameter name="clockCrossingAdapter">
   <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -53,7 +53,7 @@
  </parameter>
  <parameter name="generationId">
   <type>int</type>
-  <value>1610543004</value>
+  <value>1725106633</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
@@ -101,7 +101,7 @@
  </parameter>
  <parameter name="projectName">
   <type>java.lang.String</type>
-  <value>minimal_flash.qpf</value>
+  <value>pokeymax.qpf</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -150,7 +150,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="20.1"
+   version="23.1"
    path="onchip_flash_0">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -296,7 +296,7 @@
   </parameter>
   <parameter name="CLOCK_FREQUENCY">
    <type>double</type>
-   <value>80.0</value>
+   <value>116.0</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
@@ -693,7 +693,7 @@
   </parameter>
   <parameter name="FLASH_RESET_CYCLE_MAX_INDEX">
    <type>int</type>
-   <value>20</value>
+   <value>29</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
@@ -701,7 +701,7 @@
   </parameter>
   <parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX">
    <type>int</type>
-   <value>96</value>
+   <value>139</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
@@ -709,7 +709,7 @@
   </parameter>
   <parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX">
    <type>int</type>
-   <value>28000000</value>
+   <value>40600000</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
@@ -717,7 +717,7 @@
   </parameter>
   <parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX">
    <type>int</type>
-   <value>24400</value>
+   <value>35380</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
@@ -787,7 +787,7 @@
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk" kind="clock_sink" version="20.1">
+  <interface name="clk" kind="clock_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -848,7 +848,7 @@
     <role>clk</role>
    </port>
   </interface>
-  <interface name="nreset" kind="reset_sink" version="20.1">
+  <interface name="nreset" kind="reset_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -893,7 +893,7 @@
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="data" kind="avalon_slave" version="20.1">
+  <interface name="data" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1276,7 +1276,7 @@
     <role>burstcount</role>
    </port>
   </interface>
-  <interface name="csr" kind="avalon_slave" version="20.1">
+  <interface name="csr" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1648,7 +1648,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>On-Chip Flash Intel FPGA IP</displayName>
-  <version>20.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1656,7 +1656,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Input</displayName>
-  <version>20.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1664,7 +1664,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Input</displayName>
-  <version>20.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -1672,8 +1672,8 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Avalon Memory Mapped Slave</displayName>
-  <version>20.1</version>
+  <version>23.1</version>
  </plugin>
- <reportVersion>20.1 720</reportVersion>
- <uniqueIdentifier>F44D30F4F5CE00000176FBD7FCF7</uniqueIdentifier>
+ <reportVersion>23.1 993</reportVersion>
+ <uniqueIdentifier>02424E4C123F00000191A85E3CEF</uniqueIdentifier>
 </EnsembleReport>
Index: atari_chips/pokeyv2/flash_08/flash/synthesis/flash.qip
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/synthesis/flash.qip	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/synthesis/flash.qip	(revision 1422)
@@ -1,8 +1,8 @@
 set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_NAME "Qsys"
-set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "flash" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../flash.sopcinfo"]
-set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1610543004"
+set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1725106633"
 set_global_assignment -library "flash" -name MISC_FILE [file join $::quartus(qip_path) "../flash.cmp"]
 set_global_assignment -library "flash" -name SLD_FILE [file join $::quartus(qip_path) "flash.debuginfo"]
 set_global_assignment -entity "flash" -library "flash" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -15,7 +15,7 @@
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxMDU0MzAwNA==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyNTEwNjYzMw==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDhTQ1UxNjlDOEc=::QXV0byBERVZJQ0U="
 set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -28,11 +28,11 @@
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MjMuMQ=="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE9uLUNoaXAgRmxhc2ggTWVnYWZ1bmN0aW9uIHdpdGggQXZhbG9uLU1NIFNsYXZlIEludGVyZmFjZS4="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "REFUQV9JTlRFUkZBQ0U=::UGFyYWxsZWw=::RGF0YSBpbnRlcmZhY2U="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "UkVBRF9CVVJTVF9NT0RF::V3JhcHBpbmc=::UmVhZCBidXJzdCBtb2Rl"
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfRlJFUVVFTkNZ::ODAuMA==::Q2xvY2sgZnJlcXVlbmN5"
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfRlJFUVVFTkNZ::MTE2LjA=::Q2xvY2sgZnJlcXVlbmN5"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "Q09ORklHVVJBVElPTl9NT0RF::U2luZ2xlIFVuY29tcHJlc3NlZCBJbWFnZQ==::Q29uZmlndXJhdGlvbiBNb2Rl"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "U0VDVE9SX0FDQ0VTU19NT0RF::UmVhZCBhbmQgd3JpdGUsUmVhZCBhbmQgd3JpdGUsUmVhZCBvbmx5LFJlYWQgYW5kIHdyaXRlLFJlYWQgYW5kIHdyaXRl::QWNjZXNzIE1vZGU="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "aW5pdEZsYXNoQ29udGVudA==::ZmFsc2U=::SW5pdGlhbGl6ZSBmbGFzaCBjb250ZW50"
@@ -70,10 +70,10 @@
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfU0VRX1JFQURfREFUQV9DT1VOVA==::Mg==::RkxBU0hfU0VRX1JFQURfREFUQV9DT1VOVA=="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfQUREUl9BTElHTk1FTlRfQklUUw==::MQ==::RkxBU0hfQUREUl9BTElHTk1FTlRfQklUUw=="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfUkVBRF9DWUNMRV9NQVhfSU5ERVg=::NA==::RkxBU0hfUkVBRF9DWUNMRV9NQVhfSU5ERVg="
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfUkVTRVRfQ1lDTEVfTUFYX0lOREVY::MjA=::RkxBU0hfUkVTRVRfQ1lDTEVfTUFYX0lOREVY"
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfQlVTWV9USU1FT1VUX0NZQ0xFX01BWF9JTkRFWA==::OTY=::RkxBU0hfQlVTWV9USU1FT1VUX0NZQ0xFX01BWF9JTkRFWA=="
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfRVJBU0VfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg=::MjgwMDAwMDA=::RkxBU0hfRVJBU0VfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg="
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfV1JJVEVfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg=::MjQ0MDA=::RkxBU0hfV1JJVEVfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg="
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfUkVTRVRfQ1lDTEVfTUFYX0lOREVY::Mjk=::RkxBU0hfUkVTRVRfQ1lDTEVfTUFYX0lOREVY"
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfQlVTWV9USU1FT1VUX0NZQ0xFX01BWF9JTkRFWA==::MTM5::RkxBU0hfQlVTWV9USU1FT1VUX0NZQ0xFX01BWF9JTkRFWA=="
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfRVJBU0VfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg=::NDA2MDAwMDA=::RkxBU0hfRVJBU0VfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg="
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "RkxBU0hfV1JJVEVfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg=::MzUzODA=::RkxBU0hfV1JJVEVfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "UEFSQUxMRUxfTU9ERQ==::dHJ1ZQ==::UEFSQUxMRUxfTU9ERQ=="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "UkVBRF9BTkRfV1JJVEVfTU9ERQ==::dHJ1ZQ==::UkVBRF9BTkRfV1JJVEVfTU9ERQ=="
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "V1JBUFBJTkdfQlVSU1RfTU9ERQ==::dHJ1ZQ==::V1JBUFBJTkdfQlVSU1RfTU9ERQ=="
@@ -90,5 +90,5 @@
 set_global_assignment -library "flash" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rtl/altera_onchip_flash_block.v"]
 
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_NAME "altera_onchip_flash"
-set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_ENV "Qsys"
Index: atari_chips/pokeyv2/flash_08/flash/synthesis/flash.vhd
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/synthesis/flash.vhd	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/synthesis/flash.vhd	(revision 1422)
@@ -1,6 +1,6 @@
 -- flash.vhd
 
--- Generated using ACDS version 20.1 720
+-- Generated using ACDS version 23.1 993
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -135,10 +135,10 @@
 			FLASH_SEQ_READ_DATA_COUNT           => 2,
 			FLASH_ADDR_ALIGNMENT_BITS           => 1,
 			FLASH_READ_CYCLE_MAX_INDEX          => 4,
-			FLASH_RESET_CYCLE_MAX_INDEX         => 20,
-			FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX  => 96,
-			FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 28000000,
-			FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 24400,
+			FLASH_RESET_CYCLE_MAX_INDEX         => 29,
+			FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX  => 139,
+			FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40600000,
+			FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35380,
 			PARALLEL_MODE                       => true,
 			READ_AND_WRITE_MODE                 => true,
 			WRAPPING_BURST_MODE                 => true,
Index: atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash.sdc
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash.sdc	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash.sdc	(revision 1422)
@@ -1,4 +1,4 @@
-# (C) 2001-2020 Intel Corporation. All rights reserved.
+# (C) 2001-2024 Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions and other 
 # software and tools, and its AMPP partner logic functions, and any output 
 # files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash.v
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2020 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v
===================================================================
--- atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2020 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
@@ -330,8 +330,8 @@
     generate // generate combi based on read burst mode
         if (WRAPPING_BURST_MODE == 0) begin
             // incrementing read
-	    //assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
-            assign flash_read_addr = avmm_addr; // intel ufm read bug fix 'Is there a known issue with the MAX 10 On Chip Flash IP, for UFM read operations?'
+            assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
+            //assign flash_read_addr = avmm_addr; // intel ufm read bug fix 'Is there a known issue with the MAX 10 On Chip Flash IP, for UFM read operations?'
             assign cur_e_addr = csr_sector_erase_addr;
             assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
             assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
Index: atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: atari_chips/pokeyv2/flash_08/flash.sopcinfo
===================================================================
--- atari_chips/pokeyv2/flash_08/flash.sopcinfo	(revision 1421)
+++ atari_chips/pokeyv2/flash_08/flash.sopcinfo	(revision 1422)
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="flash" kind="flash" version="1.0" fabric="QSYS">
- <!-- Format version 20.1 720 (Future versions may contain additional information.) -->
- <!-- 2021.01.13.13:51:58 -->
+ <!-- Format version 23.1 993 (Future versions may contain additional information.) -->
+ <!-- 2024.08.31.14:17:13 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1610542318</value>
+  <value>1725106633</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -98,7 +98,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="20.1"
+   version="23.1"
    path="onchip_flash_0">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -735,7 +735,7 @@
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk" kind="clock_sink" version="20.1">
+  <interface name="clk" kind="clock_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -796,7 +796,7 @@
     <role>clk</role>
    </port>
   </interface>
-  <interface name="nreset" kind="reset_sink" version="20.1">
+  <interface name="nreset" kind="reset_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -841,7 +841,7 @@
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="data" kind="avalon_slave" version="20.1">
+  <interface name="data" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1224,7 +1224,7 @@
     <role>burstcount</role>
    </port>
   </interface>
-  <interface name="csr" kind="avalon_slave" version="20.1">
+  <interface name="csr" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1596,7 +1596,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>On-Chip Flash Intel FPGA IP</displayName>
-  <version>20.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1604,7 +1604,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Input</displayName>
-  <version>20.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1612,7 +1612,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Input</displayName>
-  <version>20.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -1620,8 +1620,8 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Avalon Memory Mapped Slave</displayName>
-  <version>20.1</version>
+  <version>23.1</version>
  </plugin>
- <reportVersion>20.1 720</reportVersion>
+ <reportVersion>23.1 993</reportVersion>
  <uniqueIdentifier></uniqueIdentifier>
 </EnsembleReport>
Index: atari_chips/pokeyv2/flash_16/flash/flash.html
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/flash.html	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/flash.html	(revision 1422)
@@ -67,7 +67,7 @@
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2020.11.14.09:21:05</td>
+    <td class="l">2024.08.31.14:38:21</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -85,7 +85,7 @@
      <br/>All Components
      <br/>&#160;&#160;
      <a href="#module_onchip_flash_0"><b>onchip_flash_0</b>
-     </a> altera_onchip_flash 19.1</span>
+     </a> altera_onchip_flash 23.1</span>
    </div>
   </div>
   <div style="width:100% ;  height:10px"> </div>
@@ -110,7 +110,7 @@
   <a name="module_onchip_flash_0"> </a>
   <div>
    <hr/>
-   <h2>onchip_flash_0</h2>altera_onchip_flash v19.1
+   <h2>onchip_flash_0</h2>altera_onchip_flash v23.1
    <br/>
    <br/>
    <br/>
Index: atari_chips/pokeyv2/flash_16/flash/synthesis/flash.debuginfo
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/synthesis/flash.debuginfo	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/synthesis/flash.debuginfo	(revision 1422)
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport name="flash" kind="system" version="19.1" fabric="QSYS">
- <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
- <!-- 2020.11.14.09:21:06 -->
+<EnsembleReport name="flash" kind="system" version="23.1" fabric="QSYS">
+ <!-- Format version 23.1 993 (Future versions may contain additional information.) -->
+ <!-- 2024.08.31.14:38:21 -->
  <!-- A collection of modules and connections -->
  <parameter name="clockCrossingAdapter">
   <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -53,7 +53,7 @@
  </parameter>
  <parameter name="generationId">
   <type>int</type>
-  <value>1605342065</value>
+  <value>1725107901</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
@@ -150,7 +150,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="19.1"
+   version="23.1"
    path="onchip_flash_0">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -787,7 +787,7 @@
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk" kind="clock_sink" version="19.1">
+  <interface name="clk" kind="clock_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -848,7 +848,7 @@
     <role>clk</role>
    </port>
   </interface>
-  <interface name="nreset" kind="reset_sink" version="19.1">
+  <interface name="nreset" kind="reset_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -893,7 +893,7 @@
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="data" kind="avalon_slave" version="19.1">
+  <interface name="data" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1276,7 +1276,7 @@
     <role>burstcount</role>
    </port>
   </interface>
-  <interface name="csr" kind="avalon_slave" version="19.1">
+  <interface name="csr" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1648,7 +1648,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>On-Chip Flash Intel FPGA IP</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1656,7 +1656,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Input</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1664,7 +1664,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Input</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -1672,8 +1672,8 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Avalon Memory Mapped Slave</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
- <reportVersion>19.1 670</reportVersion>
- <uniqueIdentifier>F44D30F4F5CE00000175C5D7F57C</uniqueIdentifier>
+ <reportVersion>23.1 993</reportVersion>
+ <uniqueIdentifier>02424E4C123F00000191A87192A2</uniqueIdentifier>
 </EnsembleReport>
Index: atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash.sdc
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash.sdc	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash.sdc	(revision 1422)
@@ -1,4 +1,4 @@
-# (C) 2001-2019 Intel Corporation. All rights reserved.
+# (C) 2001-2024 Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions and other 
 # software and tools, and its AMPP partner logic functions, and any output 
 # files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v
===================================================================
--- atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2019 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
@@ -217,7 +217,6 @@
     reg flash_drdin_neg_reg;
     reg [15:0] write_count;
     reg [25:0] erase_count;
-    reg [2:0] read_count;
     reg [2:0] read_ctrl_count;
     reg [2:0] data_count;
     reg write_timeout;
@@ -331,8 +330,8 @@
     generate // generate combi based on read burst mode
         if (WRAPPING_BURST_MODE == 0) begin
             // incrementing read
-            //assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
-            assign flash_read_addr = avmm_addr; // intel ufm read bug fix 'Is there a known issue with the MAX 10 On Chip Flash IP, for UFM read operations?'
+            assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
+            //assign flash_read_addr = avmm_addr; // intel ufm read bug fix 'Is there a known issue with the MAX 10 On Chip Flash IP, for UFM read operations?'
             assign cur_e_addr = csr_sector_erase_addr;
             assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
             assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
@@ -422,7 +421,6 @@
         reset_n_reg2 = 0;
         read_wait = 0;
         read_wait_neg = 0;
-        read_count = 0;
         is_sector1_writable_reg = 0;
         is_sector2_writable_reg = 0;
         is_sector3_writable_reg = 0;
@@ -599,6 +597,7 @@
                 if (~reset_n_w) begin
                     write_state <= WRITE_STATE_IDLE;
                     write_wait <= 0;
+                    csr_status_w_pass <= 1'b0;
                 end
                 else begin
                     case (write_state)
@@ -614,6 +613,7 @@
                                 if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
                                     write_state <= WRITE_STATE_ADDR;
                                     write_wait <= 1;
+                                    csr_status_w_pass <= 1'b0;
                                 end
                             end
                         end
@@ -723,6 +723,7 @@
             always @ (posedge clock) begin
                 if (~reset_n_w) begin
                     erase_state <= ERASE_STATE_IDLE;
+                    csr_status_e_pass <= 1'b0;
                 end
                 else begin
                     case (erase_state)
@@ -736,6 +737,7 @@
                             // check command
                             if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
                                 erase_state <= ERASE_STATE_ADDR;
+                                csr_status_e_pass <= 1'b0;
                             end
                         end
 
@@ -829,6 +831,7 @@
                 if (~reset_n_w) begin
                     read_state <= READ_STATE_IDLE;
                     read_wait <= 0;
+                    csr_status_r_pass <= 0;
                 end
                 else begin
                     case (read_state)
@@ -851,6 +854,7 @@
                                     read_state <= READ_STATE_ADDR;
                                     flash_seq_read_ardin <= avmm_addr;
                                     avmm_burstcount_input_reg <= avmm_burstcount;
+                                    csr_status_r_pass <= 0;
                                 end
                             end
                         end
@@ -940,10 +944,14 @@
             // -------------------------------------------------------------------
             // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
             // -------------------------------------------------------------------        
+            
+            reg [2:0] read_count;
+            
             always @ (posedge clock) begin
                 if (~reset_n_w) begin
                     read_state <= READ_STATE_IDLE;
                     read_wait <= 0;
+                    read_count <= 3'd0;
                 end
                 else begin
                     case (read_state)
Index: atari_chips/pokeyv2/lvds_rx.bsf
===================================================================
--- atari_chips/pokeyv2/lvds_rx.bsf	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx.bsf	(revision 1422)
@@ -4,7 +4,7 @@
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2020  Intel Corporation. All rights reserved.
+Copyright (C) 2024  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
Index: atari_chips/pokeyv2/lvds_rx.vhd
===================================================================
--- atari_chips/pokeyv2/lvds_rx.vhd	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx.vhd	(revision 1422)
@@ -1,8 +1,8 @@
--- megafunction wizard: %Soft LVDS Intel FPGA IP v20.1%
+-- megafunction wizard: %Soft LVDS Intel FPGA IP v23.1%
 -- GENERATION: XML
 -- lvds_rx.vhd
 
--- Generated using ACDS version 20.1 720
+-- Generated using ACDS version 23.1 993
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -17,17 +17,17 @@
 end entity lvds_rx;
 
 architecture rtl of lvds_rx is
-	component altera_soft_lvds_rx_twD2Tqf3 is
+	component altera_soft_lvds_rx_uCmNW05P is
 		port (
 			data  : in  std_logic_vector(0 downto 0) := (others => 'X'); -- data
 			clock : in  std_logic                    := 'X';             -- clock
 			q     : out std_logic_vector(0 downto 0)                     -- q
 		);
-	end component altera_soft_lvds_rx_twD2Tqf3;
+	end component altera_soft_lvds_rx_uCmNW05P;
 
 begin
 
-	lvds_rx_inst : component altera_soft_lvds_rx_twD2Tqf3
+	lvds_rx_inst : component altera_soft_lvds_rx_uCmNW05P
 		port map (
 			data  => data,  --  data.data
 			clock => clock, -- clock.clock
@@ -41,7 +41,7 @@
 --	************************************************************
 --	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --	************************************************************
---	Copyright (C) 1991-2021 Altera Corporation
+--	Copyright (C) 1991-2024 Altera Corporation
 --	Any megafunction design, and related net list (encrypted or decrypted),
 --	support information, device programming or simulation file, and any other
 --	associated documentation or information provided by Altera or a partner
@@ -61,7 +61,7 @@
 --	their respective licensors.  No other licenses, including any licenses
 --	needed under any third party's intellectual property, are provided herein.
 ---->
--- Retrieval info: <instance entity-name="altera_soft_lvds" version="20.1" >
+-- Retrieval info: <instance entity-name="altera_soft_lvds" version="23.1" >
 -- Retrieval info: 	<generic name="DEVICE_FAMILY" value="MAX 10" />
 -- Retrieval info: 	<generic name="DEVICE_TYPE" value="Single Supply" />
 -- Retrieval info: 	<generic name="FUNCTIONAL_MODE" value="RX" />
@@ -130,4 +130,4 @@
 -- Retrieval info: 	<generic name="VOD_SETTING" value="0" />
 -- Retrieval info: </instance>
 -- IPFS_FILES : lvds_rx.vho
--- RELATED_FILES: lvds_rx.vhd, altera_soft_lvds_rx_twD2Tqf3.v
+-- RELATED_FILES: lvds_rx.vhd, altera_soft_lvds_rx_uCmNW05P.v
Index: atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1422)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2021.04.24.15:13:51
+# ACDS 23.1 993 linux 2024.08.31.14:19:57
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,12 +107,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2021.04.24.15:13:51
+# ACDS 23.1 993 linux 2024.08.31.14:19:57
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="lvds_rx"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/20.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/23.1std/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0
@@ -196,7 +196,7 @@
 # ----------------------------------------
 # compile design files in correct order
 if [ $SKIP_COM -eq 0 ]; then
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v" -work lvds_rx
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v" -work lvds_rx
   vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QSYS_SIMDIR/lvds_rx.vhd"                                                  
 fi
 
Index: atari_chips/pokeyv2/lvds_tx.sip
===================================================================
--- atari_chips/pokeyv2/lvds_tx.sip	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx.sip	(revision 1422)
@@ -1,7 +1,7 @@
 set_global_assignment -entity "lvds_tx" -library "lib_lvds_tx" -name IP_TOOL_NAME "altera_soft_lvds"
-set_global_assignment -entity "lvds_tx" -library "lib_lvds_tx" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "lvds_tx" -library "lib_lvds_tx" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "lvds_tx" -library "lib_lvds_tx" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lib_lvds_tx" -name SPD_FILE [file join $::quartus(sip_path) "lvds_tx.spd"]
 
 set_global_assignment -library "lib_lvds_tx" -name MISC_FILE [file join $::quartus(sip_path) "lvds_tx_sim/lvds_tx.vhd"]
-set_global_assignment -library "lib_lvds_tx" -name MISC_FILE [file join $::quartus(sip_path) "lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v"]
+set_global_assignment -library "lib_lvds_tx" -name MISC_FILE [file join $::quartus(sip_path) "lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v"]
Index: atari_chips/pokeyv2/lvds_rx.qip
===================================================================
--- atari_chips/pokeyv2/lvds_rx.qip	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx.qip	(revision 1422)
@@ -1,5 +1,5 @@
 set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_TOOL_NAME "altera_soft_lvds"
-set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lvds_rx" -name MISC_FILE [file join $::quartus(qip_path) "lvds_rx.cmp"]
 set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -11,75 +11,75 @@
 set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_VERSION "MjMuMQ=="
 set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_DESCRIPTION "U29mdCBMVkRTIEludGVsIEZQR0EgSVAgdXNpbmcgY29yZSBsb2dpYyBlbGVtZW50cy4="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_NAME "YWx0ZXJhX3NvZnRfbHZkc19yeF90d0QyVHFmMw=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_DISPLAY_NAME "U29mdCBMVkRTIEludGVsIEZQR0EgSVA="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_VERSION "MjAuMQ=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_DESCRIPTION "U29mdCBMVkRTIEludGVsIEZQR0EgSVAgdXNpbmcgY29yZSBsb2dpYyBlbGVtZW50cy4="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REVWSUNFX1RZUEU=::U2luZ2xlIFN1cHBseQ==::UG93ZXIgU3VwcGx5IE1vZGU="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05BTF9NT0RF::Ulg=::RnVuY3Rpb25hbCBtb2Rl"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NIQU5ORUxT::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "V0lEVEg=::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TFBNX1dJRFRI::MQ==::TFBNX1dJRFRI"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REVTRVJJQUxJWkFUSU9OX0ZBQ1RPUg==::MQ==::U0VSREVTIGZhY3Rvcg=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX1BMTA==::T0ZG::VVNFX0VYVEVSTkFMX1BMTA=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q09NTU9OX1JYX1RYX1BMTA==::T0ZG::VXNlIGNvbW1vbiBQTEwocykgZm9yIHJlY2VpdmVycyBhbmQgdHJhbnNtaXR0ZXJzLg=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UExMX1NFTEZfUkVTRVRfT05fTE9TU19MT0NL::T0ZG::RW5hYmxlIHNlbGYtcmVzZXQgb24gbG9zcyBsb2NrIGluIFBMTA=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QRVJJT0Q=::NTAwMA==::SU5DTE9DS19QRVJJT0Q="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9EQVRBX0FMSUdO::UE9SVF9VTlVTRUQ=::RW5hYmxlIGJpdHNsaXAgbW9kZQ=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04=::UE9SVF9VTlVTRUQ=::UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9EQVRBX0FMSUdOX0lOUFVU::T0ZG::QWRkIGV4dHJhIHJlZ2lzdGVyIGZvciByeF9kYXRhX2FsaWduIHBvcnQ="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9PVVRQVVQ=::T0ZG::UkVHSVNURVJFRF9PVVRQVVQ="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ=::MC4wMA==::T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q09SRUNMT0NLX0RJVklERV9CWQ==::Mg==::Q09SRUNMT0NLX0RJVklERV9CWQ=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QSEFTRV9TSElGVA==::MA==::SU5DTE9DS19QSEFTRV9TSElGVA=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9JTlBVVA==::T0ZG::UkVHSVNURVJFRF9JTlBVVA=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX0NPUkVDTE9DS19JTlBVVA==::T0ZG::RW5hYmxlIHR4X2NvcmVjbG9jayBwb3J0"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUkVTT1VSQ0U=::QVVUTw==::T1VUQ0xPQ0tfUkVTT1VSQ0U="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "QlVGRkVSX0lNUExFTUVOVEFUSU9O::UkFN::QlVGRkVSX0lNUExFTUVOVEFUSU9O"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TFZEU19SWF9SRUdfU0VUVElOR19VSQ==::ZmFsc2U=::UmVtb3ZlIExWRFNfUlhfUkVHSVNURVIgYXR0cmlidXRlIGVtYmVkZGVkIGludG8gUlRMLg=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TFZEU19SWF9SRUdfU0VUVElORw==::T0ZG::TFZEU19SWF9SRUdfU0VUVElORw=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUUFVUX0RBVEFfUkFURQ==::NzIw::RGF0YSByYXRlOg=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU1QTEVNRU5UX0lOX0xFUw==::T04=::SU1QTEVNRU5UX0lOX0xFUw=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRF::NzIwLjAgTWJwcw==::REFUQV9SQVRF"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU5fTEVOR1RI::NDg=::Q0FSUllfQ0hBSU5fTEVOR1RI"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU=::MA==::RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX0NPVU5U::MA==::RFBMTF9MT0NLX0NPVU5U"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX1dJTkRPVw==::MA==::RFBMTF9MT0NLX1dJTkRPVw=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19CT09TVA==::MA==::SU5DTE9DS19CT09TVA=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg==::MA==::U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ=::MA==::U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU4=::TUFOVUFM::Q0FSUllfQ0hBSU4="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ::T04=::Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ::T0ZG::RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9DQUxJQlJBVElPTg==::T04=::RU5BQkxFX0RQQV9DQUxJQlJBVElPTg=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg==::T0ZG::RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9NT0RF::T0ZG::RU5BQkxFX0RQQV9NT0RF"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04=::T0ZG::RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NPRlRfQ0RSX01PREU=::T0ZG::RU5BQkxFX1NPRlRfQ0RSX01PREU="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19EQVRBX0FMSUdOTUVOVA==::RURHRV9BTElHTkVE::SU5DTE9DS19EQVRBX0FMSUdOTUVOVA=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TE9XX1BPV0VSX01PREU=::QVVUTw==::TE9XX1BPV0VSX01PREU="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ=::T0ZG::U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX0RQTExfUkFXUEVSUk9S::T0ZG::VVNFX0RQTExfUkFXUEVSUk9S"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX05PX1BIQVNFX1NISUZU::T04=::VVNFX05PX1BIQVNFX1NISUZU"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "WF9PTl9CSVRTTElQ::T04=::WF9PTl9CSVRTTElQ"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RElGRkVSRU5USUFMX0RSSVZF::MA==::RElGRkVSRU5USUFMX0RSSVZF"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMS19MQVRFTkNZ::T0ZG::RU5BQkxFX0NMS19MQVRFTkNZ"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TVVMVElfQ0xPQ0s=::T0ZG::TVVMVElfQ0xPQ0s="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfQUxJR05NRU5U::RURHRV9BTElHTkVE::T1VUQ0xPQ0tfQUxJR05NRU5U"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfTVVMVElQTFlfQlk=::MQ==::T1VUQ0xPQ0tfTVVMVElQTFlfQlk="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UExMX0NPTVBFTlNBVElPTl9NT0RF::QVVUTw==::UExMX0NPTVBFTlNBVElPTl9NT0RF"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UFJFRU1QSEFTSVNfU0VUVElORw==::MA==::UFJFRU1QSEFTSVNfU0VUVElORw=="
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Vk9EX1NFVFRJTkc=::MA==::Vk9EX1NFVFRJTkc="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_NAME "YWx0ZXJhX3NvZnRfbHZkc19yeF91Q21OVzA1UA=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_DISPLAY_NAME "U29mdCBMVkRTIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_VERSION "MjMuMQ=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_DESCRIPTION "U29mdCBMVkRTIEludGVsIEZQR0EgSVAgdXNpbmcgY29yZSBsb2dpYyBlbGVtZW50cy4="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REVWSUNFX1RZUEU=::U2luZ2xlIFN1cHBseQ==::UG93ZXIgU3VwcGx5IE1vZGU="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05BTF9NT0RF::Ulg=::RnVuY3Rpb25hbCBtb2Rl"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NIQU5ORUxT::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "V0lEVEg=::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TFBNX1dJRFRI::MQ==::TFBNX1dJRFRI"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REVTRVJJQUxJWkFUSU9OX0ZBQ1RPUg==::MQ==::U0VSREVTIGZhY3Rvcg=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX1BMTA==::T0ZG::VVNFX0VYVEVSTkFMX1BMTA=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q09NTU9OX1JYX1RYX1BMTA==::T0ZG::VXNlIGNvbW1vbiBQTEwocykgZm9yIHJlY2VpdmVycyBhbmQgdHJhbnNtaXR0ZXJzLg=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UExMX1NFTEZfUkVTRVRfT05fTE9TU19MT0NL::T0ZG::RW5hYmxlIHNlbGYtcmVzZXQgb24gbG9zcyBsb2NrIGluIFBMTA=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QRVJJT0Q=::NTAwMA==::SU5DTE9DS19QRVJJT0Q="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9EQVRBX0FMSUdO::UE9SVF9VTlVTRUQ=::RW5hYmxlIGJpdHNsaXAgbW9kZQ=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04=::UE9SVF9VTlVTRUQ=::UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9EQVRBX0FMSUdOX0lOUFVU::T0ZG::QWRkIGV4dHJhIHJlZ2lzdGVyIGZvciByeF9kYXRhX2FsaWduIHBvcnQ="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9PVVRQVVQ=::T0ZG::UkVHSVNURVJFRF9PVVRQVVQ="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ=::MC4wMA==::T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q09SRUNMT0NLX0RJVklERV9CWQ==::Mg==::Q09SRUNMT0NLX0RJVklERV9CWQ=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QSEFTRV9TSElGVA==::MA==::SU5DTE9DS19QSEFTRV9TSElGVA=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9JTlBVVA==::T0ZG::UkVHSVNURVJFRF9JTlBVVA=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX0NPUkVDTE9DS19JTlBVVA==::T0ZG::RW5hYmxlIHR4X2NvcmVjbG9jayBwb3J0"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUkVTT1VSQ0U=::QVVUTw==::T1VUQ0xPQ0tfUkVTT1VSQ0U="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "QlVGRkVSX0lNUExFTUVOVEFUSU9O::UkFN::QlVGRkVSX0lNUExFTUVOVEFUSU9O"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TFZEU19SWF9SRUdfU0VUVElOR19VSQ==::ZmFsc2U=::UmVtb3ZlIExWRFNfUlhfUkVHSVNURVIgYXR0cmlidXRlIGVtYmVkZGVkIGludG8gUlRMLg=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TFZEU19SWF9SRUdfU0VUVElORw==::T0ZG::TFZEU19SWF9SRUdfU0VUVElORw=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUUFVUX0RBVEFfUkFURQ==::NzIw::RGF0YSByYXRlOg=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU1QTEVNRU5UX0lOX0xFUw==::T04=::SU1QTEVNRU5UX0lOX0xFUw=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRF::NzIwLjAgTWJwcw==::REFUQV9SQVRF"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU5fTEVOR1RI::NDg=::Q0FSUllfQ0hBSU5fTEVOR1RI"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU=::MA==::RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX0NPVU5U::MA==::RFBMTF9MT0NLX0NPVU5U"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX1dJTkRPVw==::MA==::RFBMTF9MT0NLX1dJTkRPVw=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19CT09TVA==::MA==::SU5DTE9DS19CT09TVA=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg==::MA==::U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ=::MA==::U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU4=::TUFOVUFM::Q0FSUllfQ0hBSU4="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ::T04=::Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ::T0ZG::RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9DQUxJQlJBVElPTg==::T04=::RU5BQkxFX0RQQV9DQUxJQlJBVElPTg=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg==::T0ZG::RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9NT0RF::T0ZG::RU5BQkxFX0RQQV9NT0RF"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04=::T0ZG::RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NPRlRfQ0RSX01PREU=::T0ZG::RU5BQkxFX1NPRlRfQ0RSX01PREU="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19EQVRBX0FMSUdOTUVOVA==::RURHRV9BTElHTkVE::SU5DTE9DS19EQVRBX0FMSUdOTUVOVA=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TE9XX1BPV0VSX01PREU=::QVVUTw==::TE9XX1BPV0VSX01PREU="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ=::T0ZG::U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX0RQTExfUkFXUEVSUk9S::T0ZG::VVNFX0RQTExfUkFXUEVSUk9S"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX05PX1BIQVNFX1NISUZU::T04=::VVNFX05PX1BIQVNFX1NISUZU"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "WF9PTl9CSVRTTElQ::T04=::WF9PTl9CSVRTTElQ"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RElGRkVSRU5USUFMX0RSSVZF::MA==::RElGRkVSRU5USUFMX0RSSVZF"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMS19MQVRFTkNZ::T0ZG::RU5BQkxFX0NMS19MQVRFTkNZ"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TVVMVElfQ0xPQ0s=::T0ZG::TVVMVElfQ0xPQ0s="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfQUxJR05NRU5U::RURHRV9BTElHTkVE::T1VUQ0xPQ0tfQUxJR05NRU5U"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfTVVMVElQTFlfQlk=::MQ==::T1VUQ0xPQ0tfTVVMVElQTFlfQlk="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UExMX0NPTVBFTlNBVElPTl9NT0RF::QVVUTw==::UExMX0NPTVBFTlNBVElPTl9NT0RF"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UFJFRU1QSEFTSVNfU0VUVElORw==::MA==::UFJFRU1QSEFTSVNfU0VUVElORw=="
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Vk9EX1NFVFRJTkc=::MA==::Vk9EX1NFVFRJTkc="
 
 set_global_assignment -library "lvds_rx" -name VHDL_FILE [file join $::quartus(qip_path) "lvds_rx.vhd"]
-set_global_assignment -library "lvds_rx" -name VERILOG_FILE [file join $::quartus(qip_path) "lvds_rx/altera_soft_lvds_rx_twD2Tqf3.v"]
+set_global_assignment -library "lvds_rx" -name VERILOG_FILE [file join $::quartus(qip_path) "lvds_rx/altera_soft_lvds_rx_uCmNW05P.v"]
 
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_TOOL_NAME "altera_soft_lvds"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_TOOL_VERSION "20.1"
-set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_TOOL_NAME "altera_soft_lvds"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_TOOL_VERSION "23.1"
+set_global_assignment -entity "altera_soft_lvds_rx_uCmNW05P" -library "lvds_rx" -name IP_TOOL_ENV "mwpim"
Index: atari_chips/pokeyv2/lvds_rx_sim/aldec/rivierapro_setup.tcl
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/aldec/rivierapro_setup.tcl	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx_sim/aldec/rivierapro_setup.tcl	(revision 1422)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2021.04.24.15:13:51
+# ACDS 23.1 993 linux 2024.08.31.14:19:57
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
@@ -113,7 +113,7 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/20.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
@@ -221,7 +221,7 @@
 # Compile the design files in correct order
 alias com {
   echo "\[exec\] com"
-  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v" -work lvds_rx
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v" -work lvds_rx
   eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QSYS_SIMDIR/lvds_rx.vhd"                                                  
 }
 
Index: atari_chips/pokeyv2/lvds_rx_sim.f
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim.f	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx_sim.f	(revision 1422)
@@ -1,2 +1,2 @@
 lvds_rx_sim/lvds_rx.vhd
-lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v
+lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v
Index: atari_chips/pokeyv2/lvds_tx.spd
===================================================================
--- atari_chips/pokeyv2/lvds_tx.spd	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx.spd	(revision 1422)
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <simPackage>
  <file
-   path="lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v"
+   path="lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v"
    type="VERILOG"
    library="lvds_tx" />
  <file path="lvds_tx_sim/lvds_tx.vhd" type="VHDL" />
Index: atari_chips/pokeyv2/lvds_tx_sim/mentor/msim_setup.tcl
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/mentor/msim_setup.tcl	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx_sim/mentor/msim_setup.tcl	(revision 1422)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2021.04.24.15:12:23
+# ACDS 23.1 993 linux 2024.08.31.14:19:17
 
 # ----------------------------------------
 # Initialize variables
@@ -113,7 +113,7 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/20.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
@@ -150,7 +150,7 @@
 ensure_lib          ./libraries/work/
 vmap       work     ./libraries/work/
 vmap       work_lib ./libraries/work/
-if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
   ensure_lib                  ./libraries/altera_ver/      
   vmap       altera_ver       ./libraries/altera_ver/      
   ensure_lib                  ./libraries/lpm_ver/         
@@ -183,7 +183,7 @@
 # Compile device library files
 alias dev_com {
   echo "\[exec\] dev_com"
-  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+  if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"               -work altera_ver      
     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                        -work lpm_ver         
     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                           -work sgate_ver       
@@ -215,7 +215,7 @@
 # Compile the design files in correct order
 alias com {
   echo "\[exec\] com"
-  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v" -work lvds_tx
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v" -work lvds_tx
   eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS    "$QSYS_SIMDIR/lvds_tx.vhd"                                                  
 }
 
Index: atari_chips/pokeyv2/paddle_gpio.bsf
===================================================================
--- atari_chips/pokeyv2/paddle_gpio.bsf	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio.bsf	(revision 1422)
@@ -4,7 +4,7 @@
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2020  Intel Corporation. All rights reserved.
+Copyright (C) 2024  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
Index: atari_chips/pokeyv2/paddle_gpio_sim/aldec/rivierapro_setup.tcl
===================================================================
--- atari_chips/pokeyv2/paddle_gpio_sim/aldec/rivierapro_setup.tcl	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio_sim/aldec/rivierapro_setup.tcl	(revision 1422)
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2024.04.16.22:45:10
+# ACDS 23.1 993 linux 2024.08.31.14:44:44
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
@@ -113,7 +113,7 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/20.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
Index: atari_chips/pokeyv2/paddle_gpio_sim/paddle_gpio.vhd
===================================================================
--- atari_chips/pokeyv2/paddle_gpio_sim/paddle_gpio.vhd	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio_sim/paddle_gpio.vhd	(revision 1422)
@@ -1,6 +1,6 @@
 -- paddle_gpio.vhd
 
--- Generated using ACDS version 20.1 720
+-- Generated using ACDS version 23.1 993
 
 library IEEE;
 use IEEE.std_logic_1164.all;
Index: atari_chips/pokeyv2/pll.vhd
===================================================================
--- atari_chips/pokeyv2/pll.vhd	(revision 1421)
+++ atari_chips/pokeyv2/pll.vhd	(revision 1422)
@@ -9,16 +9,16 @@
 -- 			altpll
 --
 -- Simulation Library Files(s):
--- 			altera_mf
+-- 			
 -- ============================================================
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+-- 23.1std.1 Build 993 05/14/2024 SC Lite Edition
 -- ************************************************************
 
 
---Copyright (C) 2020  Intel Corporation. All rights reserved.
+--Copyright (C) 2024  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and any partner logic 
 --functions, and any output files from any of the foregoing 
@@ -420,5 +420,4 @@
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
 -- Retrieval info: CBX_MODULE_PREFIX: ON
Index: atari_chips/pokeyv2/flash_16/flash.sopcinfo
===================================================================
--- atari_chips/pokeyv2/flash_16/flash.sopcinfo	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash.sopcinfo	(revision 1422)
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="flash" kind="flash" version="1.0" fabric="QSYS">
- <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
- <!-- 2020.11.14.09:21:05 -->
+ <!-- Format version 23.1 993 (Future versions may contain additional information.) -->
+ <!-- 2024.08.31.14:38:21 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1605342065</value>
+  <value>1725107901</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -98,7 +98,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="19.1"
+   version="23.1"
    path="onchip_flash_0">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -735,7 +735,7 @@
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk" kind="clock_sink" version="19.1">
+  <interface name="clk" kind="clock_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -796,7 +796,7 @@
     <role>clk</role>
    </port>
   </interface>
-  <interface name="nreset" kind="reset_sink" version="19.1">
+  <interface name="nreset" kind="reset_sink" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -841,7 +841,7 @@
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="data" kind="avalon_slave" version="19.1">
+  <interface name="data" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1224,7 +1224,7 @@
     <role>burstcount</role>
    </port>
   </interface>
-  <interface name="csr" kind="avalon_slave" version="19.1">
+  <interface name="csr" kind="avalon_slave" version="23.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -1596,7 +1596,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>On-Chip Flash Intel FPGA IP</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1604,7 +1604,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Input</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -1612,7 +1612,7 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Input</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -1620,8 +1620,8 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Avalon Memory Mapped Slave</displayName>
-  <version>19.1</version>
+  <version>23.1</version>
  </plugin>
- <reportVersion>19.1 670</reportVersion>
+ <reportVersion>23.1 993</reportVersion>
  <uniqueIdentifier></uniqueIdentifier>
 </EnsembleReport>
Index: atari_chips/pokeyv2/lvds_rx.spd
===================================================================
--- atari_chips/pokeyv2/lvds_rx.spd	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx.spd	(revision 1422)
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <simPackage>
  <file
-   path="lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v"
+   path="lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v"
    type="VERILOG"
    library="lvds_rx" />
  <file path="lvds_rx_sim/lvds_rx.vhd" type="VHDL" />
Index: atari_chips/pokeyv2/lvds_rx_sim/mentor/msim_setup.tcl
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/mentor/msim_setup.tcl	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx_sim/mentor/msim_setup.tcl	(revision 1422)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2021.04.24.15:13:51
+# ACDS 23.1 993 linux 2024.08.31.14:19:57
 
 # ----------------------------------------
 # Initialize variables
@@ -113,7 +113,7 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/20.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
@@ -150,7 +150,7 @@
 ensure_lib          ./libraries/work/
 vmap       work     ./libraries/work/
 vmap       work_lib ./libraries/work/
-if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
   ensure_lib                  ./libraries/altera_ver/      
   vmap       altera_ver       ./libraries/altera_ver/      
   ensure_lib                  ./libraries/lpm_ver/         
@@ -183,7 +183,7 @@
 # Compile device library files
 alias dev_com {
   echo "\[exec\] dev_com"
-  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+  if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"               -work altera_ver      
     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                        -work lpm_ver         
     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                           -work sgate_ver       
@@ -215,7 +215,7 @@
 # Compile the design files in correct order
 alias com {
   echo "\[exec\] com"
-  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v" -work lvds_rx
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v" -work lvds_rx
   eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS    "$QSYS_SIMDIR/lvds_rx.vhd"                                                  
 }
 
Index: atari_chips/pokeyv2/lvds_tx.qip
===================================================================
--- atari_chips/pokeyv2/lvds_tx.qip	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx.qip	(revision 1422)
@@ -1,5 +1,5 @@
 set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_TOOL_NAME "altera_soft_lvds"
-set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lvds_tx" -name MISC_FILE [file join $::quartus(qip_path) "lvds_tx.cmp"]
 set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -11,75 +11,75 @@
 set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_COMPONENT_VERSION "MjMuMQ=="
 set_global_assignment -entity "lvds_tx" -library "lvds_tx" -name IP_COMPONENT_DESCRIPTION "U29mdCBMVkRTIEludGVsIEZQR0EgSVAgdXNpbmcgY29yZSBsb2dpYyBlbGVtZW50cy4="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_NAME "YWx0ZXJhX3NvZnRfbHZkc190eF90d0Q1Q1NYVw=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_DISPLAY_NAME "U29mdCBMVkRTIEludGVsIEZQR0EgSVA="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_VERSION "MjAuMQ=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_DESCRIPTION "U29mdCBMVkRTIEludGVsIEZQR0EgSVAgdXNpbmcgY29yZSBsb2dpYyBlbGVtZW50cy4="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "REVWSUNFX1RZUEU=::U2luZ2xlIFN1cHBseQ==::UG93ZXIgU3VwcGx5IE1vZGU="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05BTF9NT0RF::VFg=::RnVuY3Rpb25hbCBtb2Rl"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05BTF9NT0RFX1VJX0JPT0w=::ZmFsc2U=::RnVuY3Rpb25hbCBNb2RlOg=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NIQU5ORUxT::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "V0lEVEg=::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TFBNX1dJRFRI::MQ==::TFBNX1dJRFRI"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "REVTRVJJQUxJWkFUSU9OX0ZBQ1RPUg==::MQ==::U0VSREVTIGZhY3Rvcg=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX1BMTA==::T0ZG::VVNFX0VYVEVSTkFMX1BMTA=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q09NTU9OX1JYX1RYX1BMTA==::T0ZG::VXNlIGNvbW1vbiBQTEwocykgZm9yIHJlY2VpdmVycyBhbmQgdHJhbnNtaXR0ZXJzLg=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UExMX1NFTEZfUkVTRVRfT05fTE9TU19MT0NL::T0ZG::RW5hYmxlIHNlbGYtcmVzZXQgb24gbG9zcyBsb2NrIGluIFBMTA=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QRVJJT0Q=::NTAwMA==::SU5DTE9DS19QRVJJT0Q="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9EQVRBX0FMSUdO::UE9SVF9VTlVTRUQ=::RW5hYmxlIGJpdHNsaXAgbW9kZQ=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04=::UE9SVF9VTlVTRUQ=::UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9EQVRBX0FMSUdOX0lOUFVU::T0ZG::QWRkIGV4dHJhIHJlZ2lzdGVyIGZvciByeF9kYXRhX2FsaWduIHBvcnQ="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9PVVRQVVQ=::T0ZG::UkVHSVNURVJFRF9PVVRQVVQ="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ=::MC4wMA==::T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q09SRUNMT0NLX0RJVklERV9CWQ==::Mg==::Q09SRUNMT0NLX0RJVklERV9CWQ=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QSEFTRV9TSElGVA==::MA==::SU5DTE9DS19QSEFTRV9TSElGVA=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9JTlBVVA==::T0ZG::UkVHSVNURVJFRF9JTlBVVA=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "VVNFX0NPUkVDTE9DS19JTlBVVA==::T0ZG::RW5hYmxlIHR4X2NvcmVjbG9jayBwb3J0"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUkVTT1VSQ0U=::QVVUTw==::T1VUQ0xPQ0tfUkVTT1VSQ0U="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "QlVGRkVSX0lNUExFTUVOVEFUSU9O::UkFN::QlVGRkVSX0lNUExFTUVOVEFUSU9O"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TFZEU19SWF9SRUdfU0VUVElORw==::T0ZG::TFZEU19SWF9SRUdfU0VUVElORw=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUUFVUX0RBVEFfUkFURQ==::NzIw::RGF0YSByYXRlOg=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU1QTEVNRU5UX0lOX0xFUw==::T04=::SU1QTEVNRU5UX0lOX0xFUw=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRF::NzIwLjAgTWJwcw==::REFUQV9SQVRF"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU5fTEVOR1RI::NDg=::Q0FSUllfQ0hBSU5fTEVOR1RI"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU=::MA==::RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX0NPVU5U::MA==::RFBMTF9MT0NLX0NPVU5U"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX1dJTkRPVw==::MA==::RFBMTF9MT0NLX1dJTkRPVw=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19CT09TVA==::MA==::SU5DTE9DS19CT09TVA=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg==::MA==::U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ=::MA==::U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU4=::TUFOVUFM::Q0FSUllfQ0hBSU4="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ::T04=::Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ::T0ZG::RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9DQUxJQlJBVElPTg==::T04=::RU5BQkxFX0RQQV9DQUxJQlJBVElPTg=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg==::T0ZG::RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9NT0RF::T0ZG::RU5BQkxFX0RQQV9NT0RF"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04=::T0ZG::RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NPRlRfQ0RSX01PREU=::T0ZG::RU5BQkxFX1NPRlRfQ0RSX01PREU="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19EQVRBX0FMSUdOTUVOVA==::RURHRV9BTElHTkVE::SU5DTE9DS19EQVRBX0FMSUdOTUVOVA=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TE9XX1BPV0VSX01PREU=::QVVUTw==::TE9XX1BPV0VSX01PREU="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ=::T0ZG::U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "VVNFX0RQTExfUkFXUEVSUk9S::T0ZG::VVNFX0RQTExfUkFXUEVSUk9S"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "VVNFX05PX1BIQVNFX1NISUZU::T04=::VVNFX05PX1BIQVNFX1NISUZU"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "WF9PTl9CSVRTTElQ::T04=::WF9PTl9CSVRTTElQ"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RElGRkVSRU5USUFMX0RSSVZF::MA==::RElGRkVSRU5USUFMX0RSSVZF"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMS19MQVRFTkNZ::T0ZG::RU5BQkxFX0NMS19MQVRFTkNZ"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TVVMVElfQ0xPQ0s=::T0ZG::TVVMVElfQ0xPQ0s="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfQUxJR05NRU5U::RURHRV9BTElHTkVE::T1VUQ0xPQ0tfQUxJR05NRU5U"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfTVVMVElQTFlfQlk=::MQ==::T1VUQ0xPQ0tfTVVMVElQTFlfQlk="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UExMX0NPTVBFTlNBVElPTl9NT0RF::QVVUTw==::UExMX0NPTVBFTlNBVElPTl9NT0RF"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UFJFRU1QSEFTSVNfU0VUVElORw==::MA==::UFJFRU1QSEFTSVNfU0VUVElORw=="
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Vk9EX1NFVFRJTkc=::MA==::Vk9EX1NFVFRJTkc="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_NAME "YWx0ZXJhX3NvZnRfbHZkc190eF91Q21NWGZHQg=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_DISPLAY_NAME "U29mdCBMVkRTIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_VERSION "MjMuMQ=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_DESCRIPTION "U29mdCBMVkRTIEludGVsIEZQR0EgSVAgdXNpbmcgY29yZSBsb2dpYyBlbGVtZW50cy4="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "REVWSUNFX1RZUEU=::U2luZ2xlIFN1cHBseQ==::UG93ZXIgU3VwcGx5IE1vZGU="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05BTF9NT0RF::VFg=::RnVuY3Rpb25hbCBtb2Rl"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05BTF9NT0RFX1VJX0JPT0w=::ZmFsc2U=::RnVuY3Rpb25hbCBNb2RlOg=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NIQU5ORUxT::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "V0lEVEg=::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TFBNX1dJRFRI::MQ==::TFBNX1dJRFRI"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "REVTRVJJQUxJWkFUSU9OX0ZBQ1RPUg==::MQ==::U0VSREVTIGZhY3Rvcg=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX1BMTA==::T0ZG::VVNFX0VYVEVSTkFMX1BMTA=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q09NTU9OX1JYX1RYX1BMTA==::T0ZG::VXNlIGNvbW1vbiBQTEwocykgZm9yIHJlY2VpdmVycyBhbmQgdHJhbnNtaXR0ZXJzLg=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UExMX1NFTEZfUkVTRVRfT05fTE9TU19MT0NL::T0ZG::RW5hYmxlIHNlbGYtcmVzZXQgb24gbG9zcyBsb2NrIGluIFBMTA=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QRVJJT0Q=::NTAwMA==::SU5DTE9DS19QRVJJT0Q="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9EQVRBX0FMSUdO::UE9SVF9VTlVTRUQ=::RW5hYmxlIGJpdHNsaXAgbW9kZQ=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04=::UE9SVF9VTlVTRUQ=::UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9EQVRBX0FMSUdOX0lOUFVU::T0ZG::QWRkIGV4dHJhIHJlZ2lzdGVyIGZvciByeF9kYXRhX2FsaWduIHBvcnQ="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9PVVRQVVQ=::T0ZG::UkVHSVNURVJFRF9PVVRQVVQ="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ=::MC4wMA==::T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q09SRUNMT0NLX0RJVklERV9CWQ==::Mg==::Q09SRUNMT0NLX0RJVklERV9CWQ=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QSEFTRV9TSElGVA==::MA==::SU5DTE9DS19QSEFTRV9TSElGVA=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9JTlBVVA==::T0ZG::UkVHSVNURVJFRF9JTlBVVA=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "VVNFX0NPUkVDTE9DS19JTlBVVA==::T0ZG::RW5hYmxlIHR4X2NvcmVjbG9jayBwb3J0"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUkVTT1VSQ0U=::QVVUTw==::T1VUQ0xPQ0tfUkVTT1VSQ0U="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "QlVGRkVSX0lNUExFTUVOVEFUSU9O::UkFN::QlVGRkVSX0lNUExFTUVOVEFUSU9O"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TFZEU19SWF9SRUdfU0VUVElORw==::T0ZG::TFZEU19SWF9SRUdfU0VUVElORw=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUUFVUX0RBVEFfUkFURQ==::NzIw::RGF0YSByYXRlOg=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU1QTEVNRU5UX0lOX0xFUw==::T04=::SU1QTEVNRU5UX0lOX0xFUw=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRF::NzIwLjAgTWJwcw==::REFUQV9SQVRF"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU5fTEVOR1RI::NDg=::Q0FSUllfQ0hBSU5fTEVOR1RI"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU=::MA==::RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX0NPVU5U::MA==::RFBMTF9MT0NLX0NPVU5U"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX1dJTkRPVw==::MA==::RFBMTF9MT0NLX1dJTkRPVw=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19CT09TVA==::MA==::SU5DTE9DS19CT09TVA=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg==::MA==::U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ=::MA==::U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU4=::TUFOVUFM::Q0FSUllfQ0hBSU4="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ::T04=::Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ::T0ZG::RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9DQUxJQlJBVElPTg==::T04=::RU5BQkxFX0RQQV9DQUxJQlJBVElPTg=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg==::T0ZG::RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9NT0RF::T0ZG::RU5BQkxFX0RQQV9NT0RF"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04=::T0ZG::RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NPRlRfQ0RSX01PREU=::T0ZG::RU5BQkxFX1NPRlRfQ0RSX01PREU="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19EQVRBX0FMSUdOTUVOVA==::RURHRV9BTElHTkVE::SU5DTE9DS19EQVRBX0FMSUdOTUVOVA=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TE9XX1BPV0VSX01PREU=::QVVUTw==::TE9XX1BPV0VSX01PREU="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ=::T0ZG::U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "VVNFX0RQTExfUkFXUEVSUk9S::T0ZG::VVNFX0RQTExfUkFXUEVSUk9S"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "VVNFX05PX1BIQVNFX1NISUZU::T04=::VVNFX05PX1BIQVNFX1NISUZU"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "WF9PTl9CSVRTTElQ::T04=::WF9PTl9CSVRTTElQ"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RElGRkVSRU5USUFMX0RSSVZF::MA==::RElGRkVSRU5USUFMX0RSSVZF"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMS19MQVRFTkNZ::T0ZG::RU5BQkxFX0NMS19MQVRFTkNZ"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "TVVMVElfQ0xPQ0s=::T0ZG::TVVMVElfQ0xPQ0s="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfQUxJR05NRU5U::RURHRV9BTElHTkVE::T1VUQ0xPQ0tfQUxJR05NRU5U"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfTVVMVElQTFlfQlk=::MQ==::T1VUQ0xPQ0tfTVVMVElQTFlfQlk="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UExMX0NPTVBFTlNBVElPTl9NT0RF::QVVUTw==::UExMX0NPTVBFTlNBVElPTl9NT0RF"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "UFJFRU1QSEFTSVNfU0VUVElORw==::MA==::UFJFRU1QSEFTSVNfU0VUVElORw=="
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_COMPONENT_PARAMETER "Vk9EX1NFVFRJTkc=::MA==::Vk9EX1NFVFRJTkc="
 
 set_global_assignment -library "lvds_tx" -name VHDL_FILE [file join $::quartus(qip_path) "lvds_tx.vhd"]
-set_global_assignment -library "lvds_tx" -name VERILOG_FILE [file join $::quartus(qip_path) "lvds_tx/altera_soft_lvds_tx_twD5CSXW.v"]
+set_global_assignment -library "lvds_tx" -name VERILOG_FILE [file join $::quartus(qip_path) "lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v"]
 
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_TOOL_NAME "altera_soft_lvds"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_TOOL_VERSION "20.1"
-set_global_assignment -entity "altera_soft_lvds_tx_twD5CSXW" -library "lvds_tx" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_TOOL_NAME "altera_soft_lvds"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_TOOL_VERSION "23.1"
+set_global_assignment -entity "altera_soft_lvds_tx_uCmMXfGB" -library "lvds_tx" -name IP_TOOL_ENV "mwpim"
Index: atari_chips/pokeyv2/lvds_tx_sim/aldec/rivierapro_setup.tcl
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/aldec/rivierapro_setup.tcl	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx_sim/aldec/rivierapro_setup.tcl	(revision 1422)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2021.04.24.15:12:23
+# ACDS 23.1 993 linux 2024.08.31.14:19:17
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
@@ -113,7 +113,7 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/20.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
@@ -221,7 +221,7 @@
 # Compile the design files in correct order
 alias com {
   echo "\[exec\] com"
-  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v" -work lvds_tx
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v" -work lvds_tx
   eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QSYS_SIMDIR/lvds_tx.vhd"                                                  
 }
 
Index: atari_chips/pokeyv2/lvds_tx_sim.f
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim.f	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx_sim.f	(revision 1422)
@@ -1,2 +1,2 @@
 lvds_tx_sim/lvds_tx.vhd
-lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v
+lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v
Index: atari_chips/pokeyv2/paddle_gpio.sip
===================================================================
--- atari_chips/pokeyv2/paddle_gpio.sip	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio.sip	(revision 1422)
@@ -1,5 +1,5 @@
 set_global_assignment -entity "paddle_gpio" -library "lib_paddle_gpio" -name IP_TOOL_NAME "altera_gpio_lite"
-set_global_assignment -entity "paddle_gpio" -library "lib_paddle_gpio" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "paddle_gpio" -library "lib_paddle_gpio" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "paddle_gpio" -library "lib_paddle_gpio" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lib_paddle_gpio" -name SPD_FILE [file join $::quartus(sip_path) "paddle_gpio.spd"]
 
Index: atari_chips/pokeyv2/paddle_gpio_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv
===================================================================
--- atari_chips/pokeyv2/paddle_gpio_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv	(revision 1422)
@@ -1,29 +1,3 @@
-// Copyright (C) 2020 Intel Corporation. All rights reserved.
-// This simulation model contains highly confidential and
-// proprietary information of Intel and is being provided
-// in accordance with and subject to the protections of the
-// applicable Intel Program License Subscription Agreement
-// which governs its use and disclosure. Your use of Intel
-// Corporation's design tools, logic functions and other
-// software and tools, and its AMPP partner logic functions,
-// and any output files any of the foregoing (including device
-// programming or simulation files), and any associated
-// documentation or information are expressly subject to the
-// terms and conditions of the Intel Program License Subscription
-// Agreement, the Intel Quartus Prime License Agreement, the
-// Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is 
-// for the sole purpose of simulating designs for use exclusively
-// in logic devices manufactured by Intel and sold by Intel or 
-// its authorized distributors. Please refer to the applicable
-// agreement for further details. Intel products and services
-// are protected under numerous U.S. and foreign patents, 
-// maskwork rights, copyrights and other intellectual property laws.
-// Intel assumes no responsibility or liability arising out of the
-// application or use of this simulation model.
-// ACDS 20.1std.1
-// ALTERA_TIMESTAMP:Thu Nov 12 05:58:29 PST 2020
-// encrypted_file_type : local_encrypted
 `pragma protect begin_protected
 `pragma protect version = 1
 `pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6e"
@@ -31,683 +5,683 @@
 `pragma protect data_method = "aes128-cbc"
 `pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
 `pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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 `pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 32384)
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 `pragma protect end_protected
Index: atari_chips/pokeyv2/pll.cmp
===================================================================
--- atari_chips/pokeyv2/pll.cmp	(revision 1421)
+++ atari_chips/pokeyv2/pll.cmp	(revision 1422)
@@ -1,4 +1,4 @@
---Copyright (C) 2020  Intel Corporation. All rights reserved.
+--Copyright (C) 2024  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and any partner logic 
 --functions, and any output files from any of the foregoing 
Index: atari_chips/pokeyv2/pllv3.qip
===================================================================
--- atari_chips/pokeyv2/pllv3.qip	(revision 1421)
+++ atari_chips/pokeyv2/pllv3.qip	(revision 1422)
@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pllv3.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllv3.cmp"]
Index: atari_chips/pokeyv2/flash_16/flash.qsys
===================================================================
--- atari_chips/pokeyv2/flash_16/flash.qsys	(revision 1421)
+++ atari_chips/pokeyv2/flash_16/flash.qsys	(revision 1422)
@@ -6,7 +6,7 @@
    version="1.0"
    description=""
    tags="INTERNAL_COMPONENT=true"
-   categories="" />
+   categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
    element onchip_flash_0
@@ -64,7 +64,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="19.1"
+   version="23.1"
    enabled="1"
    autoexport="1">
   <parameter name="AUTO_CLOCK_RATE" value="0" />
Index: atari_chips/pokeyv2/lvds_rx.sip
===================================================================
--- atari_chips/pokeyv2/lvds_rx.sip	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx.sip	(revision 1422)
@@ -1,7 +1,7 @@
 set_global_assignment -entity "lvds_rx" -library "lib_lvds_rx" -name IP_TOOL_NAME "altera_soft_lvds"
-set_global_assignment -entity "lvds_rx" -library "lib_lvds_rx" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "lvds_rx" -library "lib_lvds_rx" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "lvds_rx" -library "lib_lvds_rx" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lib_lvds_rx" -name SPD_FILE [file join $::quartus(sip_path) "lvds_rx.spd"]
 
 set_global_assignment -library "lib_lvds_rx" -name MISC_FILE [file join $::quartus(sip_path) "lvds_rx_sim/lvds_rx.vhd"]
-set_global_assignment -library "lib_lvds_rx" -name MISC_FILE [file join $::quartus(sip_path) "lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v"]
+set_global_assignment -library "lib_lvds_rx" -name MISC_FILE [file join $::quartus(sip_path) "lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v"]
Index: atari_chips/pokeyv2/lvds_rx_sim/lvds_rx.vhd
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/lvds_rx.vhd	(revision 1421)
+++ atari_chips/pokeyv2/lvds_rx_sim/lvds_rx.vhd	(revision 1422)
@@ -1,6 +1,6 @@
 -- lvds_rx.vhd
 
--- Generated using ACDS version 20.1 720
+-- Generated using ACDS version 23.1 993
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -15,17 +15,17 @@
 end entity lvds_rx;
 
 architecture rtl of lvds_rx is
-	component altera_soft_lvds_rx_twD2Tqf3 is
+	component altera_soft_lvds_rx_uCmNW05P is
 		port (
 			data  : in  std_logic_vector(0 downto 0) := (others => 'X'); -- data
 			clock : in  std_logic                    := 'X';             -- clock
 			q     : out std_logic_vector(0 downto 0)                     -- q
 		);
-	end component altera_soft_lvds_rx_twD2Tqf3;
+	end component altera_soft_lvds_rx_uCmNW05P;
 
 begin
 
-	lvds_rx_inst : component altera_soft_lvds_rx_twD2Tqf3
+	lvds_rx_inst : component altera_soft_lvds_rx_uCmNW05P
 		port map (
 			data  => data,  --  data.data
 			clock => clock, -- clock.clock
Index: atari_chips/pokeyv2/lvds_tx.bsf
===================================================================
--- atari_chips/pokeyv2/lvds_tx.bsf	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx.bsf	(revision 1422)
@@ -4,7 +4,7 @@
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2020  Intel Corporation. All rights reserved.
+Copyright (C) 2024  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
Index: atari_chips/pokeyv2/lvds_tx.vhd
===================================================================
--- atari_chips/pokeyv2/lvds_tx.vhd	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx.vhd	(revision 1422)
@@ -1,8 +1,8 @@
--- megafunction wizard: %Soft LVDS Intel FPGA IP v20.1%
+-- megafunction wizard: %Soft LVDS Intel FPGA IP v23.1%
 -- GENERATION: XML
 -- lvds_tx.vhd
 
--- Generated using ACDS version 20.1 720
+-- Generated using ACDS version 23.1 993
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -16,16 +16,16 @@
 end entity lvds_tx;
 
 architecture rtl of lvds_tx is
-	component altera_soft_lvds_tx_twD5CSXW is
+	component altera_soft_lvds_tx_uCmMXfGB is
 		port (
 			tx_in  : in  std_logic_vector(0 downto 0) := (others => 'X'); -- tx_in
 			tx_out : out std_logic_vector(0 downto 0)                     -- tx_out
 		);
-	end component altera_soft_lvds_tx_twD5CSXW;
+	end component altera_soft_lvds_tx_uCmMXfGB;
 
 begin
 
-	lvds_tx_inst : component altera_soft_lvds_tx_twD5CSXW
+	lvds_tx_inst : component altera_soft_lvds_tx_uCmMXfGB
 		port map (
 			tx_in  => tx_in,  --  tx_in.tx_in
 			tx_out => tx_out  -- tx_out.tx_out
@@ -38,7 +38,7 @@
 --	************************************************************
 --	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --	************************************************************
---	Copyright (C) 1991-2021 Altera Corporation
+--	Copyright (C) 1991-2024 Altera Corporation
 --	Any megafunction design, and related net list (encrypted or decrypted),
 --	support information, device programming or simulation file, and any other
 --	associated documentation or information provided by Altera or a partner
@@ -58,7 +58,7 @@
 --	their respective licensors.  No other licenses, including any licenses
 --	needed under any third party's intellectual property, are provided herein.
 ---->
--- Retrieval info: <instance entity-name="altera_soft_lvds" version="20.1" >
+-- Retrieval info: <instance entity-name="altera_soft_lvds" version="23.1" >
 -- Retrieval info: 	<generic name="DEVICE_FAMILY" value="MAX 10" />
 -- Retrieval info: 	<generic name="DEVICE_TYPE" value="Single Supply" />
 -- Retrieval info: 	<generic name="FUNCTIONAL_MODE" value="TX" />
@@ -127,4 +127,4 @@
 -- Retrieval info: 	<generic name="VOD_SETTING" value="0" />
 -- Retrieval info: </instance>
 -- IPFS_FILES : lvds_tx.vho
--- RELATED_FILES: lvds_tx.vhd, altera_soft_lvds_tx_twD5CSXW.v
+-- RELATED_FILES: lvds_tx.vhd, altera_soft_lvds_tx_uCmMXfGB.v
Index: atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1422)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2021.04.24.15:12:23
+# ACDS 23.1 993 linux 2024.08.31.14:19:17
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,12 +107,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2021.04.24.15:12:23
+# ACDS 23.1 993 linux 2024.08.31.14:19:17
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="lvds_tx"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/20.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/23.1std/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0
@@ -196,7 +196,7 @@
 # ----------------------------------------
 # compile design files in correct order
 if [ $SKIP_COM -eq 0 ]; then
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v" -work lvds_tx
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v" -work lvds_tx
   vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QSYS_SIMDIR/lvds_tx.vhd"                                                  
 fi
 
Index: atari_chips/pokeyv2/paddle_gpio.qip
===================================================================
--- atari_chips/pokeyv2/paddle_gpio.qip	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio.qip	(revision 1422)
@@ -1,5 +1,5 @@
 set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_TOOL_NAME "altera_gpio_lite"
-set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "paddle_gpio" -name MISC_FILE [file join $::quartus(qip_path) "paddle_gpio.cmp"]
 set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -11,7 +11,7 @@
 set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_COMPONENT_VERSION "MjMuMQ=="
 set_global_assignment -entity "paddle_gpio" -library "paddle_gpio" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ=="
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
@@ -18,7 +18,7 @@
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_VERSION "MjMuMQ=="
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::YmlkaXI=::RGF0YSBkaXJlY3Rpb24="
@@ -66,5 +66,5 @@
 set_global_assignment -library "paddle_gpio" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "paddle_gpio/altera_gpio_lite.sv"]
 
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_TOOL_NAME "altera_gpio_lite"
-set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "altera_gpio_lite" -library "paddle_gpio" -name IP_TOOL_ENV "mwpim"
Index: atari_chips/pokeyv2/paddle_gpio_sim/altera_gpio_lite/altera_gpio_lite.sv
===================================================================
--- atari_chips/pokeyv2/paddle_gpio_sim/altera_gpio_lite/altera_gpio_lite.sv	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio_sim/altera_gpio_lite/altera_gpio_lite.sv	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2020 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/paddle_gpio_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- atari_chips/pokeyv2/paddle_gpio_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1422)
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 20.1 720 linux 2024.04.16.22:45:10
+# ACDS 23.1 993 linux 2024.08.31.14:44:44
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,12 +107,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2024.04.16.22:45:10
+# ACDS 23.1 993 linux 2024.08.31.14:44:44
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="paddle_gpio"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/20.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/23.1std/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0
Index: atari_chips/pokeyv2/pllv3.cmp
===================================================================
--- atari_chips/pokeyv2/pllv3.cmp	(revision 1421)
+++ atari_chips/pokeyv2/pllv3.cmp	(revision 1422)
@@ -1,4 +1,4 @@
---Copyright (C) 2020  Intel Corporation. All rights reserved.
+--Copyright (C) 2024  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and any partner logic 
 --functions, and any output files from any of the foregoing 
Index: atari_chips/pokeyv2/lvds_tx_sim/lvds_tx.vhd
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/lvds_tx.vhd	(revision 1421)
+++ atari_chips/pokeyv2/lvds_tx_sim/lvds_tx.vhd	(revision 1422)
@@ -1,6 +1,6 @@
 -- lvds_tx.vhd
 
--- Generated using ACDS version 20.1 720
+-- Generated using ACDS version 23.1 993
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -14,16 +14,16 @@
 end entity lvds_tx;
 
 architecture rtl of lvds_tx is
-	component altera_soft_lvds_tx_twD5CSXW is
+	component altera_soft_lvds_tx_uCmMXfGB is
 		port (
 			tx_in  : in  std_logic_vector(0 downto 0) := (others => 'X'); -- tx_in
 			tx_out : out std_logic_vector(0 downto 0)                     -- tx_out
 		);
-	end component altera_soft_lvds_tx_twD5CSXW;
+	end component altera_soft_lvds_tx_uCmMXfGB;
 
 begin
 
-	lvds_tx_inst : component altera_soft_lvds_tx_twD5CSXW
+	lvds_tx_inst : component altera_soft_lvds_tx_uCmMXfGB
 		port map (
 			tx_in  => tx_in,  --  tx_in.tx_in
 			tx_out => tx_out  -- tx_out.tx_out
Index: atari_chips/pokeyv2/paddle_gpio/altera_gpio_lite.sv
===================================================================
--- atari_chips/pokeyv2/paddle_gpio/altera_gpio_lite.sv	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio/altera_gpio_lite.sv	(revision 1422)
@@ -1,4 +1,4 @@
-// (C) 2001-2020 Intel Corporation. All rights reserved.
+// (C) 2001-2024 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 
Index: atari_chips/pokeyv2/paddle_gpio.vhd
===================================================================
--- atari_chips/pokeyv2/paddle_gpio.vhd	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio.vhd	(revision 1422)
@@ -1,8 +1,8 @@
--- megafunction wizard: %GPIO Lite Intel FPGA IP v20.1%
+-- megafunction wizard: %GPIO Lite Intel FPGA IP v23.1%
 -- GENERATION: XML
 -- paddle_gpio.vhd
 
--- Generated using ACDS version 20.1 720
+-- Generated using ACDS version 23.1 993
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -155,7 +155,7 @@
 --	their respective licensors.  No other licenses, including any licenses
 --	needed under any third party's intellectual property, are provided herein.
 ---->
--- Retrieval info: <instance entity-name="altera_gpio_lite" version="20.1" >
+-- Retrieval info: <instance entity-name="altera_gpio_lite" version="23.1" >
 -- Retrieval info: 	<generic name="DEVICE_FAMILY" value="MAX 10" />
 -- Retrieval info: 	<generic name="PIN_TYPE" value="bidir" />
 -- Retrieval info: 	<generic name="SIZE" value="8" />
Index: atari_chips/pokeyv2/paddle_gpio_sim/mentor/msim_setup.tcl
===================================================================
--- atari_chips/pokeyv2/paddle_gpio_sim/mentor/msim_setup.tcl	(revision 1421)
+++ atari_chips/pokeyv2/paddle_gpio_sim/mentor/msim_setup.tcl	(revision 1422)
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 20.1 720 linux 2024.04.16.22:45:10
+# ACDS 23.1 993 linux 2024.08.31.14:44:44
 
 # ----------------------------------------
 # Initialize variables
@@ -113,7 +113,7 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/20.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
@@ -150,7 +150,7 @@
 ensure_lib          ./libraries/work/
 vmap       work     ./libraries/work/
 vmap       work_lib ./libraries/work/
-if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
   ensure_lib                  ./libraries/altera_ver/      
   vmap       altera_ver       ./libraries/altera_ver/      
   ensure_lib                  ./libraries/lpm_ver/         
@@ -183,7 +183,7 @@
 # Compile device library files
 alias dev_com {
   echo "\[exec\] dev_com"
-  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+  if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"               -work altera_ver      
     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                        -work lpm_ver         
     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                           -work sgate_ver       
Index: atari_chips/pokeyv2/pll.qip
===================================================================
--- atari_chips/pokeyv2/pll.qip	(revision 1421)
+++ atari_chips/pokeyv2/pll.qip	(revision 1422)
@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
Index: atari_chips/pokeyv2/pllv3.vhd
===================================================================
--- atari_chips/pokeyv2/pllv3.vhd	(revision 1421)
+++ atari_chips/pokeyv2/pllv3.vhd	(revision 1422)
@@ -9,16 +9,16 @@
 -- 			altpll
 --
 -- Simulation Library Files(s):
--- 			altera_mf
+-- 			
 -- ============================================================
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+-- 23.1std.1 Build 993 05/14/2024 SC Lite Edition
 -- ************************************************************
 
 
---Copyright (C) 2020  Intel Corporation. All rights reserved.
+--Copyright (C) 2024  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and any partner logic 
 --functions, and any output files from any of the foregoing 
@@ -454,5 +454,4 @@
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pllv3.cmp TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pllv3.bsf FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pllv3_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
 -- Retrieval info: CBX_MODULE_PREFIX: ON
