Revision 1422
Added by markw 12 months ago
| atari_chips/pokeyv2/flash_16/flash/flash_generation.rpt | ||
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Info: Starting: Create simulation model
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation --family="MAX 10" --part=10M16SCU169C8G
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Progress: Loading build_10M16_monov2/flash.qsys
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Progress: Reading input file
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Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
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Progress: Parameterizing module onchip_flash_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: flash: Generating flash "flash" for SIM_VHDL
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Info: onchip_flash_0: "flash" instantiated altera_onchip_flash "onchip_flash_0"
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Info: flash: Done "flash" with 2 modules, 5 files
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Info: qsys-generate succeeded.
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Info: Finished: Create simulation model
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Info: Starting: Create Modelsim Project.
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Info: sim-script-gen --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ --use-relative-paths=true
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Info: Doing: ip-make-simscript --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ --use-relative-paths=true
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Info: Generating the following file(s) for VCSMX simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ directory:
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Info: synopsys/vcsmx/synopsys_sim.setup
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Info: synopsys/vcsmx/vcsmx_setup.sh
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Info: Generating the following file(s) for MODELSIM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ directory:
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Info: mentor/msim_setup.tcl
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Info: Generating the following file(s) for XCELIUM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ directory:
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Info: xcelium/cds.lib
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Info: xcelium/hdl.var
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Info: xcelium/xcelium_setup.sh
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Info: 1 .cds.lib files in xcelium/cds_libs/ directory
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Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
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Info: Generating the following file(s) for RIVIERA simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/ directory:
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Info: aldec/rivierapro_setup.tcl
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Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/simulation/.
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Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
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Info: Finished: Create Modelsim Project.
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Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash --family="MAX 10" --part=10M16SCU169C8G
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Progress: Loading build_10M16_fullv2/flash.qsys
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash --family="MAX 10" --part=10M16SCU169C8G
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Progress: Loading build_10M16_monov2/flash.qsys
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Progress: Reading input file
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Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
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Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
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Progress: Parameterizing module onchip_flash_0
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Progress: Building connections
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Progress: Parameterizing connections
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| ... | ... | |
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Info: Finished: Create block symbol file (.bsf)
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Info:
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis --family="MAX 10" --part=10M16SCU169C8G
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Progress: Loading build_10M16_fullv2/flash.qsys
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis --family="MAX 10" --part=10M16SCU169C8G
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Progress: Loading build_10M16_monov2/flash.qsys
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Progress: Reading input file
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Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
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Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
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Progress: Parameterizing module onchip_flash_0
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Progress: Building connections
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Progress: Parameterizing connections
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| atari_chips/pokeyv2/flash_16/flash/synthesis/flash.vhd | ||
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-- flash.vhd
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-- Generated using ACDS version 19.1 670
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-- Generated using ACDS version 23.1 993
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library IEEE;
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use IEEE.std_logic_1164.all;
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| atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v | ||
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// (C) 2001-2019 Intel Corporation. All rights reserved.
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// (C) 2001-2024 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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| atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v | ||
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// (C) 2001-2020 Intel Corporation. All rights reserved.
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// (C) 2001-2024 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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| atari_chips/pokeyv2/flash_08/flash/synthesis/submodules/altera_onchip_flash_util.v | ||
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// (C) 2001-2020 Intel Corporation. All rights reserved.
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// (C) 2001-2024 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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| atari_chips/pokeyv2/flash_08/flash.qsys | ||
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<module
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name="onchip_flash_0"
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kind="altera_onchip_flash"
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version="20.1"
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version="23.1"
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enabled="1"
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autoexport="1">
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<parameter name="AUTO_CLOCK_RATE" value="0" />
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| atari_chips/pokeyv2/flash_16/flash/flash.bsf | ||
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2019 Intel Corporation. All rights reserved.
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Copyright (C) 2024 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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| atari_chips/pokeyv2/flash_16/flash/flash.xml | ||
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<?xml version="1.0" encoding="UTF-8"?>
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<deploy
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date="2020.11.14.09:21:06"
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outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/">
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date="2024.08.31.14:38:21"
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outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/">
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<perimeter>
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<parameter
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name="AUTO_GENERATION_ID"
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| ... | ... | |
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</perimeter>
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<entity
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path=""
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parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M16SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1605342065,AUTO_UNIQUE_ID=(altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=1024,ADDR_RANGE2_END_ADDR=104447,ADDR_RANGE2_OFFSET=39936,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=17,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=16,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=104447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M16SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=36863,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=104447,SECTOR4_MAP=5,SECTOR4_START_ADDR=36864,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x23fff,0x24000 - 0x65fff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
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parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M16SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1725107901,AUTO_UNIQUE_ID=(altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=1024,ADDR_RANGE2_END_ADDR=104447,ADDR_RANGE2_OFFSET=39936,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=17,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=16,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=104447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M16SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=36863,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=104447,SECTOR4_MAP=5,SECTOR4_START_ADDR=36864,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x23fff,0x24000 - 0x65fff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
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instancePathKey="flash"
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kind="flash"
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version="1.0"
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name="flash">
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<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
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<parameter name="AUTO_GENERATION_ID" value="1605342065" />
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<parameter name="AUTO_GENERATION_ID" value="1725107901" />
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<parameter name="AUTO_DEVICE" value="10M16SCU169C8G" />
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<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
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<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
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| ... | ... | |
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
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<generatedFiles>
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/flash.vhd"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/flash.vhd"
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type="VHDL" />
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</generatedFiles>
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<childGeneratedFiles>
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_util.v"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_util.v"
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type="VERILOG"
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attributes="" />
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash.v"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash.v"
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type="VERILOG"
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attributes="" />
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
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type="VERILOG"
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attributes="" />
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
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type="VERILOG"
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attributes="" />
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash.sdc"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash.sdc"
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type="SDC"
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attributes="" />
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
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type="VERILOG"
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attributes="" />
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</childGeneratedFiles>
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<sourceFiles>
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash.qsys" />
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash.qsys" />
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</sourceFiles>
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<childSourceFiles>
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<file
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path="/home/markw/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
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path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
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</childSourceFiles>
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<messages>
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<message level="Debug" culprit="flash">queue size: 0 starting:flash "flash"</message>
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| ... | ... | |
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</entity>
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<entity
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path="submodules/"
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||
|
parameterizationKey="altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=1024,ADDR_RANGE2_END_ADDR=104447,ADDR_RANGE2_OFFSET=39936,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=17,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=16,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=104447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M16SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=36863,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=104447,SECTOR4_MAP=5,SECTOR4_START_ADDR=36864,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x23fff,0x24000 - 0x65fff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
|
||
|
parameterizationKey="altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=1024,ADDR_RANGE2_END_ADDR=104447,ADDR_RANGE2_OFFSET=39936,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=17,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=16,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=104447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M16SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=36863,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=104447,SECTOR4_MAP=5,SECTOR4_START_ADDR=36864,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x23fff,0x24000 - 0x65fff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
|
||
|
instancePathKey="flash:.:onchip_flash_0"
|
||
|
kind="altera_onchip_flash"
|
||
|
version="19.1"
|
||
|
version="23.1"
|
||
|
name="altera_onchip_flash">
|
||
|
<parameter name="SECTOR_READ_PROTECTION_MODE" value="16" />
|
||
|
<parameter name="MIN_UFM_VALID_ADDR" value="0" />
|
||
| ... | ... | |
|
<parameter name="IS_DUAL_BOOT" value="False" />
|
||
|
<generatedFiles>
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
type="SDC"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_fullv2/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov2/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
</generatedFiles>
|
||
|
<childGeneratedFiles/>
|
||
|
<sourceFiles>
|
||
|
<file
|
||
|
path="/home/markw/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
</sourceFiles>
|
||
|
<childSourceFiles/>
|
||
|
<instantiator instantiator="flash" as="onchip_flash_0" />
|
||
| atari_chips/pokeyv2/flash_16/flash/synthesis/flash.qip | ||
|---|---|---|
|
set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_NAME "Qsys"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "19.1"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "23.1"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_ENV "Qsys"
|
||
|
set_global_assignment -library "flash" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../flash.sopcinfo"]
|
||
|
set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1605342065"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1725107901"
|
||
|
set_global_assignment -library "flash" -name MISC_FILE [file join $::quartus(qip_path) "../flash.cmp"]
|
||
|
set_global_assignment -library "flash" -name SLD_FILE [file join $::quartus(qip_path) "flash.debuginfo"]
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
|
||
| ... | ... | |
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_VERSION "MS4w"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYwNTM0MjA2NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyNTEwNzkwMQ==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMTZTQ1UxNjlDOEc=::QXV0byBERVZJQ0U="
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||
| ... | ... | |
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MTkuMQ=="
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MjMuMQ=="
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE9uLUNoaXAgRmxhc2ggTWVnYWZ1bmN0aW9uIHdpdGggQXZhbG9uLU1NIFNsYXZlIEludGVyZmFjZS4="
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "REFUQV9JTlRFUkZBQ0U=::UGFyYWxsZWw=::RGF0YSBpbnRlcmZhY2U="
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "UkVBRF9CVVJTVF9NT0RF::SW5jcmVtZW50aW5n::UmVhZCBidXJzdCBtb2Rl"
|
||
| ... | ... | |
|
set_global_assignment -library "flash" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rtl/altera_onchip_flash_block.v"]
|
||
|
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_NAME "altera_onchip_flash"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "19.1"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "23.1"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_ENV "Qsys"
|
||
| atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash.v | ||
|---|---|---|
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
|
||
|
// (C) 2001-2024 Intel Corporation. All rights reserved.
|
||
|
// Your use of Intel Corporation's design tools, logic functions and other
|
||
|
// software and tools, and its AMPP partner logic functions, and any output
|
||
|
// files from any of the foregoing (including device programming or simulation
|
||
| atari_chips/pokeyv2/flash_16/flash/synthesis/submodules/altera_onchip_flash_util.v | ||
|---|---|---|
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
|
||
|
// (C) 2001-2024 Intel Corporation. All rights reserved.
|
||
|
// Your use of Intel Corporation's design tools, logic functions and other
|
||
|
// software and tools, and its AMPP partner logic functions, and any output
|
||
|
// files from any of the foregoing (including device programming or simulation
|
||
| atari_chips/pokeyv2/flash_04/flash/flash.bsf | ||
|---|---|---|
|
the Block Editor! File corruption is VERY likely to occur.
|
||
|
*/
|
||
|
/*
|
||
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||
|
Copyright (C) 2024 Intel Corporation. All rights reserved.
|
||
|
Your use of Intel Corporation's design tools, logic functions
|
||
|
and other software and tools, and any partner logic
|
||
|
functions, and any output files from any of the foregoing
|
||
| atari_chips/pokeyv2/flash_04/flash/flash.html | ||
|---|---|---|
|
</table>
|
||
|
<table class="blueBar">
|
||
|
<tr>
|
||
|
<td class="l">2020.06.18.10:29:34</td>
|
||
|
<td class="l">2024.08.31.14:41:48</td>
|
||
|
<td class="r">Datasheet</td>
|
||
|
</tr>
|
||
|
</table>
|
||
| ... | ... | |
|
<br/>All Components
|
||
|
<br/>  
|
||
|
<a href="#module_onchip_flash_0"><b>onchip_flash_0</b>
|
||
|
</a> altera_onchip_flash 19.1</span>
|
||
|
</a> altera_onchip_flash 23.1</span>
|
||
|
</div>
|
||
|
</div>
|
||
|
<div style="width:100% ; height:10px"> </div>
|
||
| ... | ... | |
|
<a name="module_onchip_flash_0"> </a>
|
||
|
<div>
|
||
|
<hr/>
|
||
|
<h2>onchip_flash_0</h2>altera_onchip_flash v19.1
|
||
|
<h2>onchip_flash_0</h2>altera_onchip_flash v23.1
|
||
|
<br/>
|
||
|
<br/>
|
||
|
<br/>
|
||
| ... | ... | |
|
<table class="blueBar">
|
||
|
<tr>
|
||
|
<td class="l">generation took 0.00 seconds</td>
|
||
|
<td class="r">rendering took 0.01 seconds</td>
|
||
|
<td class="r">rendering took 0.00 seconds</td>
|
||
|
</tr>
|
||
|
</table>
|
||
|
</body>
|
||
| atari_chips/pokeyv2/flash_04/flash/flash.xml | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8"?>
|
||
|
<deploy
|
||
|
date="2020.06.18.10:29:34"
|
||
|
outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/">
|
||
|
date="2024.08.31.14:41:48"
|
||
|
outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/">
|
||
|
<perimeter>
|
||
|
<parameter
|
||
|
name="AUTO_GENERATION_ID"
|
||
| ... | ... | |
|
</perimeter>
|
||
|
<entity
|
||
|
path=""
|
||
|
parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M04SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1592468974,AUTO_UNIQUE_ID=(altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=4095,ADDR_RANGE1_OFFSET=4608,ADDR_RANGE2_END_ADDR=54783,ADDR_RANGE2_OFFSET=25600,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=04,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=4095,MAX_VALID_ADDR=54783,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M04SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=2,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=18943,SECTOR2_MAP=4,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=54783,SECTOR3_MAP=5,SECTOR3_START_ADDR=18944,SECTOR4_END_ADDR=0,SECTOR4_MAP=0,SECTOR4_START_ADDR=0,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=NA,0x00000 - 0x03fff,NA,0x04000 - 0x127ff,0x12800 - 0x357ff,SECTOR_ID=NA,1,NA,2,3,SECTOR_READ_PROTECTION_MODE=24,SECTOR_STORAGE_TYPE=NA,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
|
||
|
parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M04SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1725108108,AUTO_UNIQUE_ID=(altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=4095,ADDR_RANGE1_OFFSET=4608,ADDR_RANGE2_END_ADDR=54783,ADDR_RANGE2_OFFSET=25600,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=04,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=4095,MAX_VALID_ADDR=54783,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M04SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=2,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=18943,SECTOR2_MAP=4,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=54783,SECTOR3_MAP=5,SECTOR3_START_ADDR=18944,SECTOR4_END_ADDR=0,SECTOR4_MAP=0,SECTOR4_START_ADDR=0,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=NA,0x00000 - 0x03fff,NA,0x04000 - 0x127ff,0x12800 - 0x357ff,SECTOR_ID=NA,1,NA,2,3,SECTOR_READ_PROTECTION_MODE=24,SECTOR_STORAGE_TYPE=NA,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
|
||
|
instancePathKey="flash"
|
||
|
kind="flash"
|
||
|
version="1.0"
|
||
|
name="flash">
|
||
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||
|
<parameter name="AUTO_GENERATION_ID" value="1592468974" />
|
||
|
<parameter name="AUTO_GENERATION_ID" value="1725108108" />
|
||
|
<parameter name="AUTO_DEVICE" value="10M04SCU169C8G" />
|
||
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
||
|
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
|
||
| ... | ... | |
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
|
||
|
<generatedFiles>
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/flash.vhd"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/flash.vhd"
|
||
|
type="VHDL" />
|
||
|
</generatedFiles>
|
||
|
<childGeneratedFiles>
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
type="SDC"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
</childGeneratedFiles>
|
||
|
<sourceFiles>
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys" />
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash.qsys" />
|
||
|
</sourceFiles>
|
||
|
<childSourceFiles>
|
||
|
<file
|
||
|
path="/home/markw/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
</childSourceFiles>
|
||
|
<messages>
|
||
|
<message level="Debug" culprit="flash">queue size: 0 starting:flash "flash"</message>
|
||
| ... | ... | |
|
</entity>
|
||
|
<entity
|
||
|
path="submodules/"
|
||
|
parameterizationKey="altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=4095,ADDR_RANGE1_OFFSET=4608,ADDR_RANGE2_END_ADDR=54783,ADDR_RANGE2_OFFSET=25600,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=04,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=4095,MAX_VALID_ADDR=54783,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M04SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=2,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=18943,SECTOR2_MAP=4,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=54783,SECTOR3_MAP=5,SECTOR3_START_ADDR=18944,SECTOR4_END_ADDR=0,SECTOR4_MAP=0,SECTOR4_START_ADDR=0,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=NA,0x00000 - 0x03fff,NA,0x04000 - 0x127ff,0x12800 - 0x357ff,SECTOR_ID=NA,1,NA,2,3,SECTOR_READ_PROTECTION_MODE=24,SECTOR_STORAGE_TYPE=NA,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
|
||
|
parameterizationKey="altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=4095,ADDR_RANGE1_OFFSET=4608,ADDR_RANGE2_END_ADDR=54783,ADDR_RANGE2_OFFSET=25600,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=04,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=4095,MAX_VALID_ADDR=54783,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M04SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=4095,SECTOR1_MAP=2,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=18943,SECTOR2_MAP=4,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=54783,SECTOR3_MAP=5,SECTOR3_START_ADDR=18944,SECTOR4_END_ADDR=0,SECTOR4_MAP=0,SECTOR4_START_ADDR=0,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=NA,0x00000 - 0x03fff,NA,0x04000 - 0x127ff,0x12800 - 0x357ff,SECTOR_ID=NA,1,NA,2,3,SECTOR_READ_PROTECTION_MODE=24,SECTOR_STORAGE_TYPE=NA,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
|
||
|
instancePathKey="flash:.:onchip_flash_0"
|
||
|
kind="altera_onchip_flash"
|
||
|
version="19.1"
|
||
|
version="23.1"
|
||
|
name="altera_onchip_flash">
|
||
|
<parameter name="SECTOR_READ_PROTECTION_MODE" value="24" />
|
||
|
<parameter name="MIN_UFM_VALID_ADDR" value="0" />
|
||
| ... | ... | |
|
<parameter name="IS_DUAL_BOOT" value="False" />
|
||
|
<generatedFiles>
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
type="SDC"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
</generatedFiles>
|
||
|
<childGeneratedFiles/>
|
||
|
<sourceFiles>
|
||
|
<file
|
||
|
path="/home/markw/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
</sourceFiles>
|
||
|
<childSourceFiles/>
|
||
|
<instantiator instantiator="flash" as="onchip_flash_0" />
|
||
| atari_chips/pokeyv2/flash_04/flash/flash_generation.rpt | ||
|---|---|---|
|
Info: Starting: Create simulation model
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation --family="MAX 10" --part=10M04SCU169C8G
|
||
|
Progress: Loading build_10M04_quad_auto_v3/flash.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
|
||
|
Progress: Parameterizing module onchip_flash_0
|
||
|
Progress: Building connections
|
||
|
Progress: Parameterizing connections
|
||
|
Progress: Validating
|
||
|
Progress: Done reading input file
|
||
|
Info: flash: Generating flash "flash" for SIM_VHDL
|
||
|
Info: onchip_flash_0: "flash" instantiated altera_onchip_flash "onchip_flash_0"
|
||
|
Info: flash: Done "flash" with 2 modules, 5 files
|
||
|
Info: qsys-generate succeeded.
|
||
|
Info: Finished: Create simulation model
|
||
|
Info: Starting: Create Modelsim Project.
|
||
|
Info: sim-script-gen --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ --use-relative-paths=true
|
||
|
Info: Doing: ip-make-simscript --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ --use-relative-paths=true
|
||
|
Info: Generating the following file(s) for MODELSIM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ directory:
|
||
|
Info: mentor/msim_setup.tcl
|
||
|
Info: Generating the following file(s) for VCSMX simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ directory:
|
||
|
Info: synopsys/vcsmx/synopsys_sim.setup
|
||
|
Info: synopsys/vcsmx/vcsmx_setup.sh
|
||
|
Info: Generating the following file(s) for RIVIERA simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ directory:
|
||
|
Info: aldec/rivierapro_setup.tcl
|
||
|
Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
|
||
|
Info: Generating the following file(s) for XCELIUM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/ directory:
|
||
|
Info: xcelium/cds.lib
|
||
|
Info: xcelium/hdl.var
|
||
|
Info: xcelium/xcelium_setup.sh
|
||
|
Info: 1 .cds.lib files in xcelium/cds_libs/ directory
|
||
|
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/simulation/.
|
||
|
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
|
||
|
Info: Finished: Create Modelsim Project.
|
||
|
Info: Starting: Create block symbol file (.bsf)
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash --family="MAX 10" --part=10M04SCU169C8G
|
||
|
Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash --family="MAX 10" --part=10M04SCU169C8G
|
||
|
Progress: Loading build_10M04_quad_auto_v3/flash.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
|
||
|
Progress: Parameterizing module onchip_flash_0
|
||
|
Progress: Building connections
|
||
|
Progress: Parameterizing connections
|
||
| ... | ... | |
|
Info: Finished: Create block symbol file (.bsf)
|
||
|
Info:
|
||
|
Info: Starting: Create HDL design files for synthesis
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis --family="MAX 10" --part=10M04SCU169C8G
|
||
|
Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_quad_auto_v3/flash/synthesis --family="MAX 10" --part=10M04SCU169C8G
|
||
|
Progress: Loading build_10M04_quad_auto_v3/flash.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
|
||
|
Progress: Parameterizing module onchip_flash_0
|
||
|
Progress: Building connections
|
||
|
Progress: Parameterizing connections
|
||
| atari_chips/pokeyv2/flash_04/flash/flash_generation_previous.rpt | ||
|---|---|---|
|
Info: Starting: Create block symbol file (.bsf)
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_quad_sid/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_quad_sid/flash --family="MAX 10" --part=10M08SCU169C8G
|
||
|
Progress: Loading build_10M08_quad_sid/flash.qsys
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash --family="MAX 10" --part=10M04SCU169C8G
|
||
|
Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
|
||
|
Progress: Parameterizing module onchip_flash_0
|
||
| ... | ... | |
|
Info: Finished: Create block symbol file (.bsf)
|
||
|
Info:
|
||
|
Info: Starting: Create HDL design files for synthesis
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_quad_sid/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_quad_sid/flash/synthesis --family="MAX 10" --part=10M08SCU169C8G
|
||
|
Progress: Loading build_10M08_quad_sid/flash.qsys
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis --family="MAX 10" --part=10M04SCU169C8G
|
||
|
Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
|
||
|
Progress: Parameterizing module onchip_flash_0
|
||
| atari_chips/pokeyv2/flash_04/flash/synthesis/flash.debuginfo | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8"?>
|
||
|
<EnsembleReport name="flash" kind="system" version="19.1" fabric="QSYS">
|
||
|
<!-- Format version 19.1 670 (Future versions may contain additional information.) -->
|
||
|
<!-- 2020.06.18.10:29:34 -->
|
||
|
<EnsembleReport name="flash" kind="system" version="23.1" fabric="QSYS">
|
||
|
<!-- Format version 23.1 993 (Future versions may contain additional information.) -->
|
||
|
<!-- 2024.08.31.14:41:48 -->
|
||
|
<!-- A collection of modules and connections -->
|
||
|
<parameter name="clockCrossingAdapter">
|
||
|
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
|
||
| ... | ... | |
|
</parameter>
|
||
|
<parameter name="generationId">
|
||
|
<type>int</type>
|
||
|
<value>1592468974</value>
|
||
|
<value>1725108108</value>
|
||
|
<derived>false</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>true</visible>
|
||
| ... | ... | |
|
<module
|
||
|
name="onchip_flash_0"
|
||
|
kind="altera_onchip_flash"
|
||
|
version="19.1"
|
||
|
version="23.1"
|
||
|
path="onchip_flash_0">
|
||
|
<!-- Describes a single module. Module parameters are
|
||
|
the requested settings for a module instance. -->
|
||
| ... | ... | |
|
<visible>true</visible>
|
||
|
<valid>true</valid>
|
||
|
</parameter>
|
||
|
<interface name="clk" kind="clock_sink" version="19.1">
|
||
|
<interface name="clk" kind="clock_sink" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>clk</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="nreset" kind="reset_sink" version="19.1">
|
||
|
<interface name="nreset" kind="reset_sink" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>reset_n</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="data" kind="avalon_slave" version="19.1">
|
||
|
<interface name="data" kind="avalon_slave" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>burstcount</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="csr" kind="avalon_slave" version="19.1">
|
||
|
<interface name="csr" kind="avalon_slave" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||
|
<displayName>On-Chip Flash Intel FPGA IP</displayName>
|
||
|
<version>19.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>1</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Clock Input</displayName>
|
||
|
<version>19.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>1</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Reset Input</displayName>
|
||
|
<version>19.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>2</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Avalon Memory Mapped Slave</displayName>
|
||
|
<version>19.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<reportVersion>19.1 670</reportVersion>
|
||
|
<uniqueIdentifier>F44D30F4F5CE00000172C68C2D62</uniqueIdentifier>
|
||
|
<reportVersion>23.1 993</reportVersion>
|
||
|
<uniqueIdentifier>02424E4C123F00000191A874BC9A</uniqueIdentifier>
|
||
|
</EnsembleReport>
|
||
| atari_chips/pokeyv2/flash_04/flash/synthesis/flash.qip | ||
|---|---|---|
|
set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_NAME "Qsys"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "19.1"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_VERSION "23.1"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_TOOL_ENV "Qsys"
|
||
|
set_global_assignment -library "flash" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../flash.sopcinfo"]
|
||
|
set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1592468974"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name SLD_INFO "QSYS_NAME flash HAS_SOPCINFO 1 GENERATION_ID 1725108108"
|
||
|
set_global_assignment -library "flash" -name MISC_FILE [file join $::quartus(qip_path) "../flash.cmp"]
|
||
|
set_global_assignment -library "flash" -name SLD_FILE [file join $::quartus(qip_path) "flash.debuginfo"]
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
|
||
| ... | ... | |
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_VERSION "MS4w"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU5MjQ2ODk3NA==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyNTEwODEwOA==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDRTQ1UxNjlDOEc=::QXV0byBERVZJQ0U="
|
||
|
set_global_assignment -entity "flash" -library "flash" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||
| ... | ... | |
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_INTERNAL "Off"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MTkuMQ=="
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_VERSION "MjMuMQ=="
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE9uLUNoaXAgRmxhc2ggTWVnYWZ1bmN0aW9uIHdpdGggQXZhbG9uLU1NIFNsYXZlIEludGVyZmFjZS4="
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "REFUQV9JTlRFUkZBQ0U=::UGFyYWxsZWw=::RGF0YSBpbnRlcmZhY2U="
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_COMPONENT_PARAMETER "UkVBRF9CVVJTVF9NT0RF::SW5jcmVtZW50aW5n::UmVhZCBidXJzdCBtb2Rl"
|
||
| ... | ... | |
|
set_global_assignment -library "flash" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rtl/altera_onchip_flash_block.v"]
|
||
|
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_NAME "altera_onchip_flash"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "19.1"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_VERSION "23.1"
|
||
|
set_global_assignment -entity "altera_onchip_flash" -library "flash" -name IP_TOOL_ENV "Qsys"
|
||
| atari_chips/pokeyv2/flash_04/flash/synthesis/flash.vhd | ||
|---|---|---|
|
-- flash.vhd
|
||
|
|
||
|
-- Generated using ACDS version 19.1 670
|
||
|
-- Generated using ACDS version 23.1 993
|
||
|
|
||
|
library IEEE;
|
||
|
use IEEE.std_logic_1164.all;
|
||
| atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash.sdc | ||
|---|---|---|
|
# (C) 2001-2019 Intel Corporation. All rights reserved.
|
||
|
# (C) 2001-2024 Intel Corporation. All rights reserved.
|
||
|
# Your use of Intel Corporation's design tools, logic functions and other
|
||
|
# software and tools, and its AMPP partner logic functions, and any output
|
||
|
# files from any of the foregoing (including device programming or simulation
|
||
| atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash.v | ||
|---|---|---|
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
|
||
|
// (C) 2001-2024 Intel Corporation. All rights reserved.
|
||
|
// Your use of Intel Corporation's design tools, logic functions and other
|
||
|
// software and tools, and its AMPP partner logic functions, and any output
|
||
|
// files from any of the foregoing (including device programming or simulation
|
||
| atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v | ||
|---|---|---|
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
|
||
|
// (C) 2001-2024 Intel Corporation. All rights reserved.
|
||
|
// Your use of Intel Corporation's design tools, logic functions and other
|
||
|
// software and tools, and its AMPP partner logic functions, and any output
|
||
|
// files from any of the foregoing (including device programming or simulation
|
||
| atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v | ||
|---|---|---|
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
|
||
|
// (C) 2001-2024 Intel Corporation. All rights reserved.
|
||
|
// Your use of Intel Corporation's design tools, logic functions and other
|
||
|
// software and tools, and its AMPP partner logic functions, and any output
|
||
|
// files from any of the foregoing (including device programming or simulation
|
||
| ... | ... | |
|
reg flash_drdin_neg_reg;
|
||
|
reg [15:0] write_count;
|
||
|
reg [25:0] erase_count;
|
||
|
reg [2:0] read_count;
|
||
|
reg [2:0] read_ctrl_count;
|
||
|
reg [2:0] data_count;
|
||
|
reg write_timeout;
|
||
| ... | ... | |
|
generate // generate combi based on read burst mode
|
||
|
if (WRAPPING_BURST_MODE == 0) begin
|
||
|
// incrementing read
|
||
|
//assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
|
||
|
assign flash_read_addr = avmm_addr; // intel ufm read bug fix 'Is there a known issue with the MAX 10 On Chip Flash IP, for UFM read operations?'
|
||
|
assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
|
||
|
//assign flash_read_addr = avmm_addr; // intel ufm read bug fix 'Is there a known issue with the MAX 10 On Chip Flash IP, for UFM read operations?'
|
||
|
assign cur_e_addr = csr_sector_erase_addr;
|
||
|
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
|
||
|
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
|
||
| ... | ... | |
|
reset_n_reg2 = 0;
|
||
|
read_wait = 0;
|
||
|
read_wait_neg = 0;
|
||
|
read_count = 0;
|
||
|
is_sector1_writable_reg = 0;
|
||
|
is_sector2_writable_reg = 0;
|
||
|
is_sector3_writable_reg = 0;
|
||
| ... | ... | |
|
if (~reset_n_w) begin
|
||
|
write_state <= WRITE_STATE_IDLE;
|
||
|
write_wait <= 0;
|
||
|
csr_status_w_pass <= 1'b0;
|
||
|
end
|
||
|
else begin
|
||
|
case (write_state)
|
||
| ... | ... | |
|
if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
|
||
|
write_state <= WRITE_STATE_ADDR;
|
||
|
write_wait <= 1;
|
||
|
csr_status_w_pass <= 1'b0;
|
||
|
end
|
||
|
end
|
||
|
end
|
||
| ... | ... | |
|
always @ (posedge clock) begin
|
||
|
if (~reset_n_w) begin
|
||
|
erase_state <= ERASE_STATE_IDLE;
|
||
|
csr_status_e_pass <= 1'b0;
|
||
|
end
|
||
|
else begin
|
||
|
case (erase_state)
|
||
| ... | ... | |
|
// check command
|
||
|
if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
|
||
|
erase_state <= ERASE_STATE_ADDR;
|
||
|
csr_status_e_pass <= 1'b0;
|
||
|
end
|
||
|
end
|
||
|
|
||
| ... | ... | |
|
if (~reset_n_w) begin
|
||
|
read_state <= READ_STATE_IDLE;
|
||
|
read_wait <= 0;
|
||
|
csr_status_r_pass <= 0;
|
||
|
end
|
||
|
else begin
|
||
|
case (read_state)
|
||
| ... | ... | |
|
read_state <= READ_STATE_ADDR;
|
||
|
flash_seq_read_ardin <= avmm_addr;
|
||
|
avmm_burstcount_input_reg <= avmm_burstcount;
|
||
|
csr_status_r_pass <= 0;
|
||
|
end
|
||
|
end
|
||
|
end
|
||
| ... | ... | |
|
// -------------------------------------------------------------------
|
||
|
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
|
||
|
// -------------------------------------------------------------------
|
||
|
|
||
|
reg [2:0] read_count;
|
||
|
|
||
|
always @ (posedge clock) begin
|
||
|
if (~reset_n_w) begin
|
||
|
read_state <= READ_STATE_IDLE;
|
||
|
read_wait <= 0;
|
||
|
read_count <= 3'd0;
|
||
|
end
|
||
|
else begin
|
||
|
case (read_state)
|
||
| atari_chips/pokeyv2/flash_04/flash/synthesis/submodules/altera_onchip_flash_util.v | ||
|---|---|---|
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
|
||
|
// (C) 2001-2024 Intel Corporation. All rights reserved.
|
||
|
// Your use of Intel Corporation's design tools, logic functions and other
|
||
|
// software and tools, and its AMPP partner logic functions, and any output
|
||
|
// files from any of the foregoing (including device programming or simulation
|
||
| atari_chips/pokeyv2/flash_04/flash.qsys | ||
|---|---|---|
|
version="1.0"
|
||
|
description=""
|
||
|
tags="INTERNAL_COMPONENT=true"
|
||
|
categories="" />
|
||
|
categories="System" />
|
||
|
<parameter name="bonusData"><![CDATA[bonusData
|
||
|
{
|
||
|
element onchip_flash_0
|
||
| ... | ... | |
|
<module
|
||
|
name="onchip_flash_0"
|
||
|
kind="altera_onchip_flash"
|
||
|
version="19.1"
|
||
|
version="23.1"
|
||
|
enabled="1"
|
||
|
autoexport="1">
|
||
|
<parameter name="AUTO_CLOCK_RATE" value="0" />
|
||
| atari_chips/pokeyv2/flash_04/flash.sopcinfo | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8"?>
|
||
|
<EnsembleReport name="flash" kind="flash" version="1.0" fabric="QSYS">
|
||
|
<!-- Format version 19.1 670 (Future versions may contain additional information.) -->
|
||
|
<!-- 2020.06.18.10:30:08 -->
|
||
|
<!-- Format version 23.1 993 (Future versions may contain additional information.) -->
|
||
|
<!-- 2024.08.31.14:41:48 -->
|
||
|
<!-- A collection of modules and connections -->
|
||
|
<parameter name="AUTO_GENERATION_ID">
|
||
|
<type>java.lang.Integer</type>
|
||
|
<value>1592469008</value>
|
||
|
<value>1725108108</value>
|
||
|
<derived>false</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>false</visible>
|
||
| ... | ... | |
|
<module
|
||
|
name="onchip_flash_0"
|
||
|
kind="altera_onchip_flash"
|
||
|
version="19.1"
|
||
|
version="23.1"
|
||
|
path="onchip_flash_0">
|
||
|
<!-- Describes a single module. Module parameters are
|
||
|
the requested settings for a module instance. -->
|
||
| ... | ... | |
|
<visible>true</visible>
|
||
|
<valid>true</valid>
|
||
|
</parameter>
|
||
|
<interface name="clk" kind="clock_sink" version="19.1">
|
||
|
<interface name="clk" kind="clock_sink" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>clk</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="nreset" kind="reset_sink" version="19.1">
|
||
|
<interface name="nreset" kind="reset_sink" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>reset_n</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="data" kind="avalon_slave" version="19.1">
|
||
|
<interface name="data" kind="avalon_slave" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>burstcount</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="csr" kind="avalon_slave" version="19.1">
|
||
|
<interface name="csr" kind="avalon_slave" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||
|
<displayName>On-Chip Flash Intel FPGA IP</displayName>
|
||
|
<version>19.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>1</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Clock Input</displayName>
|
||
|
<version>19.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>1</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Reset Input</displayName>
|
||
|
<version>19.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>2</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Avalon Memory Mapped Slave</displayName>
|
||
|
<version>19.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<reportVersion>19.1 670</reportVersion>
|
||
|
<reportVersion>23.1 993</reportVersion>
|
||
|
<uniqueIdentifier></uniqueIdentifier>
|
||
|
</EnsembleReport>
|
||
| atari_chips/pokeyv2/flash_08/flash/flash.bsf | ||
|---|---|---|
|
the Block Editor! File corruption is VERY likely to occur.
|
||
|
*/
|
||
|
/*
|
||
|
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||
|
Copyright (C) 2024 Intel Corporation. All rights reserved.
|
||
|
Your use of Intel Corporation's design tools, logic functions
|
||
|
and other software and tools, and any partner logic
|
||
|
functions, and any output files from any of the foregoing
|
||
| atari_chips/pokeyv2/flash_08/flash/flash.html | ||
|---|---|---|
|
</table>
|
||
|
<table class="blueBar">
|
||
|
<tr>
|
||
|
<td class="l">2021.01.13.14:03:24</td>
|
||
|
<td class="l">2024.08.31.14:17:13</td>
|
||
|
<td class="r">Datasheet</td>
|
||
|
</tr>
|
||
|
</table>
|
||
| ... | ... | |
|
<br/>All Components
|
||
|
<br/>  
|
||
|
<a href="#module_onchip_flash_0"><b>onchip_flash_0</b>
|
||
|
</a> altera_onchip_flash 20.1</span>
|
||
|
</a> altera_onchip_flash 23.1</span>
|
||
|
</div>
|
||
|
</div>
|
||
|
<div style="width:100% ; height:10px"> </div>
|
||
| ... | ... | |
|
<a name="module_onchip_flash_0"> </a>
|
||
|
<div>
|
||
|
<hr/>
|
||
|
<h2>onchip_flash_0</h2>altera_onchip_flash v20.1
|
||
|
<h2>onchip_flash_0</h2>altera_onchip_flash v23.1
|
||
|
<br/>
|
||
|
<br/>
|
||
|
<br/>
|
||
| ... | ... | |
|
</tr>
|
||
|
<tr>
|
||
|
<td class="parametername">CLOCK_FREQUENCY</td>
|
||
|
<td class="parametervalue">80.0</td>
|
||
|
<td class="parametervalue">116.0</td>
|
||
|
</tr>
|
||
|
<tr>
|
||
|
<td class="parametername">CONFIGURATION_SCHEME</td>
|
||
| ... | ... | |
|
</tr>
|
||
|
<tr>
|
||
|
<td class="parametername">FLASH_RESET_CYCLE_MAX_INDEX</td>
|
||
|
<td class="parametervalue">20</td>
|
||
|
<td class="parametervalue">29</td>
|
||
|
</tr>
|
||
|
<tr>
|
||
|
<td class="parametername">FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX</td>
|
||
|
<td class="parametervalue">96</td>
|
||
|
<td class="parametervalue">139</td>
|
||
|
</tr>
|
||
|
<tr>
|
||
|
<td class="parametername">FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX</td>
|
||
|
<td class="parametervalue">28000000</td>
|
||
|
<td class="parametervalue">40600000</td>
|
||
|
</tr>
|
||
|
<tr>
|
||
|
<td class="parametername">FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX</td>
|
||
|
<td class="parametervalue">24400</td>
|
||
|
<td class="parametervalue">35380</td>
|
||
|
</tr>
|
||
|
<tr>
|
||
|
<td class="parametername">PARALLEL_MODE</td>
|
||
| ... | ... | |
|
<table class="blueBar">
|
||
|
<tr>
|
||
|
<td class="l">generation took 0.00 seconds</td>
|
||
|
<td class="r">rendering took 0.02 seconds</td>
|
||
|
<td class="r">rendering took 0.01 seconds</td>
|
||
|
</tr>
|
||
|
</table>
|
||
|
</body>
|
||
| atari_chips/pokeyv2/flash_08/flash/flash.xml | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8"?>
|
||
|
<deploy
|
||
|
date="2021.01.13.14:03:24"
|
||
|
outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/">
|
||
|
date="2024.08.31.14:17:13"
|
||
|
outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/">
|
||
|
<perimeter>
|
||
|
<parameter
|
||
|
name="AUTO_GENERATION_ID"
|
||
| ... | ... | |
|
</perimeter>
|
||
|
<entity
|
||
|
path=""
|
||
|
parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M08SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1610543004,AUTO_UNIQUE_ID=(altera_onchip_flash:20.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=512,ADDR_RANGE2_END_ADDR=58879,ADDR_RANGE2_OFFSET=21504,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=80.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=96,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=28000000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=20,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=24400,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=58879,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M08SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Wrapping,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=23039,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=58879,SECTOR4_MAP=5,SECTOR4_START_ADDR=23040,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=true,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
|
||
|
parameterizationKey="flash:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M08SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1725106633,AUTO_UNIQUE_ID=(altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=512,ADDR_RANGE2_END_ADDR=58879,ADDR_RANGE2_OFFSET=21504,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=58879,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M08SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Wrapping,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=23039,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=58879,SECTOR4_MAP=5,SECTOR4_START_ADDR=23040,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=true,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)"
|
||
|
instancePathKey="flash"
|
||
|
kind="flash"
|
||
|
version="1.0"
|
||
|
name="flash">
|
||
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||
|
<parameter name="AUTO_GENERATION_ID" value="1610543004" />
|
||
|
<parameter name="AUTO_GENERATION_ID" value="1725106633" />
|
||
|
<parameter name="AUTO_DEVICE" value="10M08SCU169C8G" />
|
||
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
||
|
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
|
||
| ... | ... | |
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
|
||
|
<generatedFiles>
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/flash.vhd"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/flash.vhd"
|
||
|
type="VHDL" />
|
||
|
</generatedFiles>
|
||
|
<childGeneratedFiles>
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
type="SDC"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
</childGeneratedFiles>
|
||
|
<sourceFiles>
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash.qsys" />
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash.qsys" />
|
||
|
</sourceFiles>
|
||
|
<childSourceFiles>
|
||
|
<file
|
||
|
path="/home/markw/intelFPGA_lite/20.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
</childSourceFiles>
|
||
|
<messages>
|
||
|
<message level="Debug" culprit="flash">queue size: 0 starting:flash "flash"</message>
|
||
| ... | ... | |
|
</entity>
|
||
|
<entity
|
||
|
path="submodules/"
|
||
|
parameterizationKey="altera_onchip_flash:20.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=512,ADDR_RANGE2_END_ADDR=58879,ADDR_RANGE2_OFFSET=21504,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=80.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=96,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=28000000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=20,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=24400,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=58879,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M08SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Wrapping,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=23039,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=58879,SECTOR4_MAP=5,SECTOR4_START_ADDR=23040,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=true,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
|
||
|
parameterizationKey="altera_onchip_flash:23.1:ADDR_RANGE1_END_ADDR=8191,ADDR_RANGE1_OFFSET=512,ADDR_RANGE2_END_ADDR=58879,ADDR_RANGE2_OFFSET=21504,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=0,AVMM_DATA_ADDR_WIDTH=16,AVMM_DATA_BURSTCOUNT_WIDTH=2,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=116.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,FLASH_ADDR_ALIGNMENT_BITS=1,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=139,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=40600000,FLASH_READ_CYCLE_MAX_INDEX=4,FLASH_RESET_CYCLE_MAX_INDEX=29,FLASH_SEQ_READ_DATA_COUNT=2,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=35380,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=8191,MAX_VALID_ADDR=58879,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M08SCU169C8G,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=2,READ_BURST_MODE=Wrapping,SECTOR1_END_ADDR=4095,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=8191,SECTOR2_MAP=2,SECTOR2_START_ADDR=4096,SECTOR3_END_ADDR=23039,SECTOR3_MAP=4,SECTOR3_START_ADDR=8192,SECTOR4_END_ADDR=58879,SECTOR4_MAP=5,SECTOR4_START_ADDR=23040,SECTOR5_END_ADDR=0,SECTOR5_MAP=0,SECTOR5_START_ADDR=0,SECTOR_ACCESS_MODE=Read and write,Read and write,Read only,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff,SECTOR_ID=1,2,NA,3,4,SECTOR_READ_PROTECTION_MODE=16,SECTOR_STORAGE_TYPE=UFM,UFM,NA,CFM,CFM,WRAPPING_BURST_MODE=true,autoInitializationFileName=flash_onchip_flash_0,initFlashContent=false,initializationFileName=altera_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
|
||
|
instancePathKey="flash:.:onchip_flash_0"
|
||
|
kind="altera_onchip_flash"
|
||
|
version="20.1"
|
||
|
version="23.1"
|
||
|
name="altera_onchip_flash">
|
||
|
<parameter name="SECTOR_READ_PROTECTION_MODE" value="16" />
|
||
|
<parameter name="MIN_UFM_VALID_ADDR" value="0" />
|
||
|
<parameter name="AVMM_DATA_ADDR_WIDTH" value="16" />
|
||
|
<parameter name="SECTOR3_START_ADDR" value="8192" />
|
||
|
<parameter name="AUTO_CLOCK_RATE" value="0" />
|
||
|
<parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX" value="28000000" />
|
||
|
<parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX" value="40600000" />
|
||
|
<parameter name="SECTOR1_END_ADDR" value="4095" />
|
||
|
<parameter name="SECTOR4_END_ADDR" value="58879" />
|
||
|
<parameter name="initializationFileNameForSim" value="altera_onchip_flash.dat" />
|
||
| ... | ... | |
|
<parameter name="WRAPPING_BURST_MODE" value="true" />
|
||
|
<parameter name="SECTOR5_MAP" value="0" />
|
||
|
<parameter name="FLASH_SEQ_READ_DATA_COUNT" value="2" />
|
||
|
<parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX" value="24400" />
|
||
|
<parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX" value="35380" />
|
||
|
<parameter name="autoInitializationFileName" value="flash_onchip_flash_0" />
|
||
|
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
||
|
<parameter name="ADDR_RANGE3_OFFSET" value="0" />
|
||
|
<parameter name="ADDR_RANGE2_OFFSET" value="21504" />
|
||
|
<parameter name="SECTOR2_END_ADDR" value="8191" />
|
||
|
<parameter name="SECTOR4_MAP" value="5" />
|
||
|
<parameter name="FLASH_RESET_CYCLE_MAX_INDEX" value="20" />
|
||
|
<parameter name="FLASH_RESET_CYCLE_MAX_INDEX" value="29" />
|
||
|
<parameter
|
||
|
name="SECTOR_ADDRESS_MAPPING"
|
||
|
value="0x00000 - 0x03fff,0x04000 - 0x07fff,NA,0x08000 - 0x167ff,0x16800 - 0x397ff" />
|
||
|
<parameter name="IS_ERAM_SKIP" value="True" />
|
||
|
<parameter name="READ_BURST_MODE" value="Wrapping" />
|
||
|
<parameter name="READ_AND_WRITE_MODE" value="true" />
|
||
|
<parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX" value="96" />
|
||
|
<parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX" value="139" />
|
||
|
<parameter name="SECTOR5_START_ADDR" value="0" />
|
||
|
<parameter name="PART_NAME" value="10M08SCU169C8G" />
|
||
|
<parameter name="ADDR_RANGE1_OFFSET" value="512" />
|
||
| ... | ... | |
|
<parameter name="READ_BURST_COUNT" value="2" />
|
||
|
<parameter name="FLASH_READ_CYCLE_MAX_INDEX" value="4" />
|
||
|
<parameter name="AVMM_DATA_BURSTCOUNT_WIDTH" value="2" />
|
||
|
<parameter name="CLOCK_FREQUENCY" value="80.0" />
|
||
|
<parameter name="CLOCK_FREQUENCY" value="116.0" />
|
||
|
<parameter name="SECTOR_STORAGE_TYPE" value="UFM,UFM,NA,CFM,CFM" />
|
||
|
<parameter name="ADDR_RANGE2_END_ADDR" value="58879" />
|
||
|
<parameter name="SECTOR5_END_ADDR" value="0" />
|
||
| ... | ... | |
|
<parameter name="IS_DUAL_BOOT" value="False" />
|
||
|
<generatedFiles>
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_util.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/altera_onchip_flash.sdc"
|
||
|
type="SDC"
|
||
|
attributes="" />
|
||
|
<file
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
||
|
type="VERILOG"
|
||
|
attributes="" />
|
||
|
</generatedFiles>
|
||
|
<childGeneratedFiles/>
|
||
|
<sourceFiles>
|
||
|
<file
|
||
|
path="/home/markw/intelFPGA_lite/20.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
||
|
</sourceFiles>
|
||
|
<childSourceFiles/>
|
||
|
<instantiator instantiator="flash" as="onchip_flash_0" />
|
||
| atari_chips/pokeyv2/flash_08/flash/flash_generation.rpt | ||
|---|---|---|
|
Info: Starting: Create simulation model
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation --family="MAX 10" --part=10M08SCU169C8G
|
||
|
Progress: Loading build_sidmax_10M08_full/flash.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
|
||
|
Progress: Parameterizing module onchip_flash_0
|
||
|
Progress: Building connections
|
||
|
Progress: Parameterizing connections
|
||
|
Progress: Validating
|
||
|
Progress: Done reading input file
|
||
|
Info: flash: Generating flash "flash" for SIM_VHDL
|
||
|
Info: onchip_flash_0: "flash" instantiated altera_onchip_flash "onchip_flash_0"
|
||
|
Info: flash: Done "flash" with 2 modules, 5 files
|
||
|
Info: qsys-generate succeeded.
|
||
|
Info: Finished: Create simulation model
|
||
|
Info: Starting: Create Modelsim Project.
|
||
|
Info: sim-script-gen --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ --use-relative-paths=true
|
||
|
Info: Doing: ip-make-simscript --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/flash.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ --use-relative-paths=true
|
||
|
Info: Generating the following file(s) for XCELIUM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ directory:
|
||
|
Info: xcelium/cds.lib
|
||
|
Info: xcelium/hdl.var
|
||
|
Info: xcelium/xcelium_setup.sh
|
||
|
Info: 1 .cds.lib files in xcelium/cds_libs/ directory
|
||
|
Info: Generating the following file(s) for RIVIERA simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ directory:
|
||
|
Info: aldec/rivierapro_setup.tcl
|
||
|
Info: Generating the following file(s) for VCSMX simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ directory:
|
||
|
Info: synopsys/vcsmx/synopsys_sim.setup
|
||
|
Info: synopsys/vcsmx/vcsmx_setup.sh
|
||
|
Info: Generating the following file(s) for MODELSIM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/ directory:
|
||
|
Info: mentor/msim_setup.tcl
|
||
|
Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
|
||
|
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/simulation/.
|
||
|
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
|
||
|
Info: Finished: Create Modelsim Project.
|
||
|
Info: Starting: Create block symbol file (.bsf)
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash --family="MAX 10" --part=10M08SCU169C8G
|
||
|
Progress: Loading build_burst/flash.qsys
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash --family="MAX 10" --part=10M08SCU169C8G
|
||
|
Progress: Loading build_sidmax_10M08_full/flash.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 20.1]
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
|
||
|
Progress: Parameterizing module onchip_flash_0
|
||
|
Progress: Building connections
|
||
|
Progress: Parameterizing connections
|
||
| ... | ... | |
|
Info: Finished: Create block symbol file (.bsf)
|
||
|
Info:
|
||
|
Info: Starting: Create HDL design files for synthesis
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/minimal_flash/build_burst/flash/synthesis --family="MAX 10" --part=10M08SCU169C8G
|
||
|
Progress: Loading build_burst/flash.qsys
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/flash/synthesis --family="MAX 10" --part=10M08SCU169C8G
|
||
|
Progress: Loading build_sidmax_10M08_full/flash.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 20.1]
|
||
|
Progress: Adding onchip_flash_0 [altera_onchip_flash 23.1]
|
||
|
Progress: Parameterizing module onchip_flash_0
|
||
|
Progress: Building connections
|
||
|
Progress: Parameterizing connections
|
||
| atari_chips/pokeyv2/flash_08/flash/synthesis/flash.debuginfo | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8"?>
|
||
|
<EnsembleReport name="flash" kind="system" version="20.1" fabric="QSYS">
|
||
|
<!-- Format version 20.1 720 (Future versions may contain additional information.) -->
|
||
|
<!-- 2021.01.13.14:03:24 -->
|
||
|
<EnsembleReport name="flash" kind="system" version="23.1" fabric="QSYS">
|
||
|
<!-- Format version 23.1 993 (Future versions may contain additional information.) -->
|
||
|
<!-- 2024.08.31.14:17:13 -->
|
||
|
<!-- A collection of modules and connections -->
|
||
|
<parameter name="clockCrossingAdapter">
|
||
|
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
|
||
| ... | ... | |
|
</parameter>
|
||
|
<parameter name="generationId">
|
||
|
<type>int</type>
|
||
|
<value>1610543004</value>
|
||
|
<value>1725106633</value>
|
||
|
<derived>false</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>true</visible>
|
||
| ... | ... | |
|
</parameter>
|
||
|
<parameter name="projectName">
|
||
|
<type>java.lang.String</type>
|
||
|
<value>minimal_flash.qpf</value>
|
||
|
<value>pokeymax.qpf</value>
|
||
|
<derived>false</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>false</visible>
|
||
| ... | ... | |
|
<module
|
||
|
name="onchip_flash_0"
|
||
|
kind="altera_onchip_flash"
|
||
|
version="20.1"
|
||
|
version="23.1"
|
||
|
path="onchip_flash_0">
|
||
|
<!-- Describes a single module. Module parameters are
|
||
|
the requested settings for a module instance. -->
|
||
| ... | ... | |
|
</parameter>
|
||
|
<parameter name="CLOCK_FREQUENCY">
|
||
|
<type>double</type>
|
||
|
<value>80.0</value>
|
||
|
<value>116.0</value>
|
||
|
<derived>false</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>true</visible>
|
||
| ... | ... | |
|
</parameter>
|
||
|
<parameter name="FLASH_RESET_CYCLE_MAX_INDEX">
|
||
|
<type>int</type>
|
||
|
<value>20</value>
|
||
|
<value>29</value>
|
||
|
<derived>true</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>false</visible>
|
||
| ... | ... | |
|
</parameter>
|
||
|
<parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX">
|
||
|
<type>int</type>
|
||
|
<value>96</value>
|
||
|
<value>139</value>
|
||
|
<derived>true</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>false</visible>
|
||
| ... | ... | |
|
</parameter>
|
||
|
<parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX">
|
||
|
<type>int</type>
|
||
|
<value>28000000</value>
|
||
|
<value>40600000</value>
|
||
|
<derived>true</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>false</visible>
|
||
| ... | ... | |
|
</parameter>
|
||
|
<parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX">
|
||
|
<type>int</type>
|
||
|
<value>24400</value>
|
||
|
<value>35380</value>
|
||
|
<derived>true</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>false</visible>
|
||
| ... | ... | |
|
<visible>true</visible>
|
||
|
<valid>true</valid>
|
||
|
</parameter>
|
||
|
<interface name="clk" kind="clock_sink" version="20.1">
|
||
|
<interface name="clk" kind="clock_sink" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>clk</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="nreset" kind="reset_sink" version="20.1">
|
||
|
<interface name="nreset" kind="reset_sink" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>reset_n</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="data" kind="avalon_slave" version="20.1">
|
||
|
<interface name="data" kind="avalon_slave" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>burstcount</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="csr" kind="avalon_slave" version="20.1">
|
||
|
<interface name="csr" kind="avalon_slave" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||
|
<displayName>On-Chip Flash Intel FPGA IP</displayName>
|
||
Also available in: Unified diff
Updated ip to quartus v23 version