Revision 10
Added by markw over 11 years ago
| common/components/generic_ram_infer.vhdl | ||
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ARCHITECTURE rtl OF generic_ram_infer IS
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TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0);
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SIGNAL ram_block : mem;
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SIGNAL ram_block : mem;
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SIGNAL q_ram : std_logic_vector(data_width-1 downto 0);
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SIGNAL we_ram : std_logic;
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BEGIN
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PROCESS (clock)
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BEGIN
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IF (clock'event AND clock = '1') THEN
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q<= (others=>'1');
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IF (to_integer(to_01(unsigned(address))) < space) THEN
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IF (we = '1') THEN
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ram_block(to_integer(to_01(unsigned(address)))) <= data;
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END IF;
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q <= ram_block(to_integer(to_01(unsigned(address))));
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END IF;
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END IF;
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IF (clock'event AND clock = '1') THEN
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IF (we_ram = '1') THEN
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ram_block(to_integer(to_01(unsigned(address)))) <= data;
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q_ram <= data;
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ELSE
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q_ram <= ram_block(to_integer(to_01(unsigned(address))));
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END IF;
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END IF;
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END PROCESS;
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PROCESS(address)
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begin
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q <= (others=>'1');
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we_ram <= '0';
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IF (to_integer(to_01(unsigned(address))) < space) THEN
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q <= q_ram;
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we_ram <= we;
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end if;
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end process;
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END rtl;
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Also available in: Unified diff
Split up into 2 sections. Quartus will not infer the ram block with it mixed