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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY reg_file IS
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generic
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(
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BYTES : natural := 1;
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WIDTH : natural := 1
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);
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PORT
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(
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CLK : IN STD_LOGIC;
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ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
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DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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WR_EN : IN STD_LOGIC;
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DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END reg_file;
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ARCHITECTURE vhdl OF reg_file IS
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component complete_address_decoder IS
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generic (width : natural := 1);
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PORT
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(
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addr_in : in std_logic_vector(width-1 downto 0);
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addr_decoded : out std_logic_vector((2**width)-1 downto 0)
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);
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END component;
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type reg_file_type is array(bytes-1 downto 0) of std_LOGIC_VECTOR(7 downto 0);
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signal digit_next : reg_file_type;
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signal digit_reg : reg_file_type;
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signal addr_decoded : std_logic_vector(2**width-1 downto 0);
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BEGIN
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complete_address_decoder1 : complete_address_decoder
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generic map (width => WIDTH)
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port map (addr_in => addr, addr_decoded => addr_decoded);
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-- next state logic
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process(digit_reg,addr_decoded,data_in,WR_EN)
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begin
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digit_next <= digit_reg;
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if (WR_EN = '1') then
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comp_gen:
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for i in 0 to (BYTES-1) loop
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if (addr_decoded(i) = '1') then
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digit_next(i) <= data_in;
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end if;
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end loop;
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end if;
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end process;
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-- register
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process(clk)
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begin
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if (clk'event and clk='1') then
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digit_reg <= digit_next;
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end if;
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end process;
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-- output
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process(addr_decoded,digit_reg)
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begin
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data_out <= X"FF";
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comp_gen:
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for i in 0 to (BYTES-1) loop
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if (addr_decoded(i) = '1') then
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data_out <= digit_reg(i);
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end if;
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end loop;
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end process;
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END vhdl;
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