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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY covox IS
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PORT
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(
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CLK : IN STD_LOGIC;
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ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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WR_EN : IN STD_LOGIC;
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covox_channel0 : out std_logic_vector(7 downto 0);
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covox_channel1 : out std_logic_vector(7 downto 0);
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covox_channel2 : out std_logic_vector(7 downto 0);
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covox_channel3 : out std_logic_vector(7 downto 0)
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);
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END covox;
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ARCHITECTURE vhdl OF covox IS
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component complete_address_decoder IS
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generic (width : natural := 1);
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PORT
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(
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addr_in : in std_logic_vector(width-1 downto 0);
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addr_decoded : out std_logic_vector((2**width)-1 downto 0)
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);
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END component;
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signal channel0_next : std_logic_vector(7 downto 0);
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signal channel1_next : std_logic_vector(7 downto 0);
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signal channel2_next : std_logic_vector(7 downto 0);
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signal channel3_next : std_logic_vector(7 downto 0);
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signal channel0_reg : std_logic_vector(7 downto 0);
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signal channel1_reg : std_logic_vector(7 downto 0);
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signal channel2_reg : std_logic_vector(7 downto 0);
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signal channel3_reg : std_logic_vector(7 downto 0);
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signal addr_decoded : std_logic_vector(3 downto 0);
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BEGIN
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complete_address_decoder1 : complete_address_decoder
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generic map (width => 2)
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port map (addr_in => addr, addr_decoded => addr_decoded);
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-- next state logic
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process(channel0_reg,channel1_reg,channel2_reg,channel3_reg,addr_decoded,data_in,WR_EN)
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begin
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channel0_next <= channel0_reg;
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channel1_next <= channel1_reg;
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channel2_next <= channel2_reg;
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channel3_next <= channel3_reg;
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if (WR_EN = '1') then
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if (addr_decoded(0) = '1') then
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channel0_next <= data_in;
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end if;
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if (addr_decoded(1) = '1') then
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channel1_next <= data_in;
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end if;
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if (addr_decoded(2) = '1') then
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channel2_next <= data_in;
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end if;
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if (addr_decoded(3) = '1') then
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channel3_next <= data_in;
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end if;
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end if;
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end process;
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-- register
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process(clk)
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begin
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if (clk'event and clk='1') then
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channel0_reg <= channel0_next;
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channel1_reg <= channel1_next;
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channel2_reg <= channel2_next;
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channel3_reg <= channel3_next;
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end if;
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end process;
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-- output
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covox_channel0 <= channel0_reg;
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covox_channel1 <= channel1_reg;
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covox_channel2 <= channel2_reg;
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covox_channel3 <= channel3_reg;
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END vhdl;
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