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`timescale 1 ns / 1 ps
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module sdram_ctrl /* verilator tracing_off */
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(
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//-----------------------------
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// Clock and reset
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//-----------------------------
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input rst, // Global reset
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input clk, // Master clock (72 MHz)
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output ram_rdy_n, // SDRAM ready
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output ram_ref, // SDRAM refresh
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output [3:0] ram_cyc, // SDRAM cycles
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output [3:0] ram_ph, // SDRAM phases
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output [8:0] ram_ph_ctr, // Phase counter
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//-----------------------------
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// Access bank #0
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//-----------------------------
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input rden_b0, // Read enable
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input wren_b0, // Write enable
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input [22:2] addr_b0, // Address (up to 8 MB)
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output valid_b0, // Read data valid
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output fetch_b0, // Write data fetch
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output [15:0] rdata_b0, // Read data
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input [15:0] wdata_b0, // Write data
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input [1:0] bena_b0, // Byte enable
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//-----------------------------
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// Access bank #1
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//-----------------------------
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input rden_b1, // Read enable
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input wren_b1, // Write enable
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input [22:2] addr_b1, // Address (up to 8 MB)
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output valid_b1, // Read data valid
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output fetch_b1, // Write data fetch
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output [15:0] rdata_b1, // Read data
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input [15:0] wdata_b1, // Write data
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input [1:0] bena_b1, // Byte enable
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//-----------------------------
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// Access bank #2
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//-----------------------------
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input rden_b2, // Read enable
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input wren_b2, // Write enable
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input [22:2] addr_b2, // Address (up to 8 MB)
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output valid_b2, // Read data valid
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output fetch_b2, // Write data fetch
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output [15:0] rdata_b2, // Read data
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input [15:0] wdata_b2, // Write data
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input [1:0] bena_b2, // Byte enable
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//-----------------------------
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// Access bank #3
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//-----------------------------
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input rden_b3, // Read enable
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input wren_b3, // Write enable
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input [22:2] addr_b3, // Address (up to 8 MB)
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output valid_b3, // Read data valid
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output fetch_b3, // Write data fetch
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output [15:0] rdata_b3, // Read data
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input [15:0] wdata_b3, // Write data
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input [1:0] bena_b3, // Byte enable
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//-----------------------------
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// SDRAM memory signals
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//-----------------------------
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output sdram_cs_n, // SDRAM chip select
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output reg sdram_ras_n, // SDRAM row address strobe
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output reg sdram_cas_n, // SDRAM column address strobe
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output reg sdram_we_n, // SDRAM write enable
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//
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output reg [1:0] sdram_ba, // SDRAM bank address
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output reg [12:0] sdram_addr, // SDRAM address
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//
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output reg [3:0] sdram_dqm_n, // SDRAM DQ masks
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output reg sdram_dq_oe, // SDRAM data output enable
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output reg [31:0] sdram_dq_o, // SDRAM data output
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input [31:0] sdram_dq_i // SDRAM data input
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);
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// SDRAM memory size (16 or 32 MB)
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parameter SDRAM_SIZE = 16;
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// SDRAM memory width (16 or 32 bits)
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parameter SDRAM_WIDTH = 16;
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// Clock-to-output delay (for simulation)
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parameter Tco_dly = 4.5;
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// SDRAM commands
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localparam [2:0]
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CMD_LMR = 3'b000,
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CMD_REF = 3'b001,
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CMD_PRE = 3'b010,
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CMD_ACT = 3'b011,
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CMD_WR = 3'b100,
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CMD_RD = 3'b101,
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CMD_BST = 3'b110,
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CMD_NOP = 3'b111;
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// ======================================================
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// SDRAM sequencer control
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// ======================================================
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reg [3:0] r_ram_cyc;
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reg [3:0] r_ram_ph;
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reg [1:0] r_ba0_ctr;
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reg [1:0] r_ba1_ctr;
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reg [8:0] r_ph_ctr;
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reg [2:0] r_ini_ctr;
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reg r_ref_ena;
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wire w_bus_eol;
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assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
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always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
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if (rst) begin
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r_ram_cyc <= 4'b1000;
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r_ram_ph <= 4'b1000;
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r_ba0_ctr <= 2'd0;
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r_ba1_ctr <= 2'd3;
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r_ph_ctr <= 9'd3;
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r_ini_ctr <= 3'd0;
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r_ref_ena <= 1'b0;
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end
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else begin
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r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
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if (r_ram_cyc[3]) begin
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r_ram_ph <= { r_ram_ph[2:0], r_ram_ph[3] };
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r_ba0_ctr <= r_ba0_ctr + 2'd1;
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r_ba1_ctr <= r_ba1_ctr + 2'd1;
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// Phase counter : 3 - 288
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if (r_ram_ph[3]) begin
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r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
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end
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// Initialization done after 4 scanlines
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if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
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r_ini_ctr <= r_ini_ctr + 3'd1;
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// Refreshes are enabled during phase 284 - 288
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//r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
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r_ref_ena <= r_ram_ph[1]; // r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
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end
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end
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end
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assign ram_ref = r_ref_ena;
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assign ram_cyc = r_ram_cyc;
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assign ram_ph = r_ram_ph;
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assign ram_ph_ctr = r_ph_ctr;
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assign ram_rdy_n = ~r_ini_ctr[2];
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// ======================================================
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// SDRAM phase generation
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// ======================================================
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reg [3:0] r_rd_act;
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reg [3:0] r_wr_act;
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reg r_act_ph; // Activate phase
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reg r_rd_ph; // Burst read phase
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reg r_wr_ph; // Burst write phase
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reg r_ref_ph; // Auto-refresh phase
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reg [3:0] r_ini_ph; // Initialization phases
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reg r_pre_ph; // Precharge phase
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reg r_lmr_ph; // Load mode register phase
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always@(posedge rst or posedge clk) begin : PHASE_GEN
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if (rst) begin
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r_rd_act <= 4'b0000;
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r_wr_act <= 4'b0000;
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r_act_ph <= 1'b0;
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r_rd_ph <= 1'b0;
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r_wr_ph <= 1'b0;
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r_ref_ph <= 1'b0;
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r_ini_ph <= 4'b0000;
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r_pre_ph <= 1'b0;
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r_lmr_ph <= 1'b0;
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end
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else begin
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if (r_ram_cyc[0]) begin
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// Access port #0 read/write
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if (r_ram_ph[0]) begin
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r_rd_act[0] <= rden_b0 & ~r_ref_ena;
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r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
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end
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else if (r_ram_ph[2]) begin
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r_rd_act[0] <= 1'b0;
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r_wr_act[0] <= 1'b0;
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end
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// Access port #1 read/write
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if (r_ram_ph[1]) begin
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r_rd_act[1] <= rden_b1 & ~r_ref_ena;
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r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
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end
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else if (r_ram_ph[3]) begin
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r_rd_act[1] <= 1'b0;
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r_wr_act[1] <= 1'b0;
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end
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// Access port #2 read/write
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if (r_ram_ph[2]) begin
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r_rd_act[2] <= rden_b2 & ~r_ref_ena;
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r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
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end
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else if (r_ram_ph[0]) begin
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r_rd_act[2] <= 1'b0;
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r_wr_act[2] <= 1'b0;
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end
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// Access port #3 read/write
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if (r_ram_ph[3]) begin
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r_rd_act[3] <= rden_b3 & ~r_ref_ena;
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r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
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end
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else if (r_ram_ph[1]) begin
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r_rd_act[3] <= 1'b0;
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r_wr_act[3] <= 1'b0;
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end
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end
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if (r_ram_cyc[0] & r_ini_ctr[2]) begin
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// Activate phase
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r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
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| (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
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| (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
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| (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
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end
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if (r_ram_cyc[3] & r_ini_ctr[2]) begin
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// Read phase
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r_rd_ph <= (r_ram_ph[0] & r_rd_act[0])
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| (r_ram_ph[1] & r_rd_act[1])
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| (r_ram_ph[2] & r_rd_act[2])
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| (r_ram_ph[3] & r_rd_act[3]);
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// Write phase
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r_wr_ph <= (r_ram_ph[0] & r_wr_act[0])
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| (r_ram_ph[1] & r_wr_act[1])
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| (r_ram_ph[2] & r_wr_act[2])
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| (r_ram_ph[3] & r_wr_act[3]);
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end
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// Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
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if (r_ram_cyc[3] & r_ram_ph[2]) begin
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if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
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r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
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end
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else begin
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r_ini_ph <= 4'b0000;
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end
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end
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// Precharge phase
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r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
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// Refresh phase
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//r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
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// | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0]; // Init
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r_ref_ph <= r_ref_ena & r_ini_ctr[2] // Normal
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| (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0]; // Init
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// Load mode register phase
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r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
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end
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end
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// ======================================================
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// SDRAM address generation
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// ======================================================
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reg [22:2] r_addr_mux;
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reg [10:2] r_addr_col;
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reg [12:0] r_addr_sdr;
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reg [1:0] r_ba_sdr;
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always@(posedge rst or posedge clk) begin : ADDRESS_GEN
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if (rst) begin
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r_addr_mux <= 21'd0;
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r_addr_col <= 9'd0;
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r_addr_sdr <= 13'd0;
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r_ba_sdr <= 2'b00;
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end
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else begin
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// Port address multiplexer
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if (r_ram_cyc[0]) begin
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r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
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| addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
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| addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
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| addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
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end
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// Column address (for read/write op.)
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if (r_ram_cyc[3]) begin
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r_addr_col <= r_addr_mux[10:2];
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end
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// Memories layouts :
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// ------------------
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// SDRAM 4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
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// SDRAM 8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
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// SDRAM 8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
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// SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
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// Row / col address
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if (SDRAM_WIDTH == 32) begin
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// 32-bit bus
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if (SDRAM_SIZE == 32) begin
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// 32 MB
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r_addr_sdr <= { 4'b0000, r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph & r_ram_cyc[0]}} // 512 cols
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| { 1'b0, r_addr_mux[22:11] } & {13{r_act_ph & r_ram_cyc[1]}} // 4096 rows
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| { 4'b0010, r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph & r_ram_cyc[2]}} // 512 cols
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| { 4'b0010, r_addr_col[10: 2] } & {13{r_wr_ph & r_ram_cyc[3]}} // 512 cols
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| { 3'b001, 10'b000000000 } & {13{r_ini_ph[0] }} // Init : precharge all
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| { 3'b000, 10'b1_00_010_0_000 } & {13{r_ini_ph[3] }}; // Init : load mode register (BL=1, CAS=2)
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end
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else begin
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// 16 MB
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r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph & r_ram_cyc[0]}} // 256 cols
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| { 1'b0, r_addr_mux[21:10] } & {13{r_act_ph & r_ram_cyc[1]}} // 4096 rows
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| { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph & r_ram_cyc[2]}} // 256 cols
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| { 5'b00100, r_addr_col[ 9: 2] } & {13{r_wr_ph & r_ram_cyc[3]}} // 256 cols
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| { 3'b001, 10'b000000000 } & {13{r_ini_ph[0] }} // Init : precharge all
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| { 3'b000, 10'b1_00_010_0_000 } & {13{r_ini_ph[3] }}; // Init : load mode register (BL=1, CAS=2)
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end
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end
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else begin
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// 16-bit bus
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if (SDRAM_SIZE == 32) begin
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// 32 MB
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r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph & r_ram_cyc[0]}} // 512 cols
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| r_addr_mux[22:10] & {13{r_act_ph & r_ram_cyc[1]}} // 8192 rows
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| { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph & r_ram_cyc[2]}} // 512 cols
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| { 4'b0010, r_addr_col[9:2], 1'b0 } & {13{r_wr_ph & r_ram_cyc[3]}} // 512 cols
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| { 3'b001, 10'b000000000 } & {13{r_ini_ph[0] }} // Init : precharge all
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| { 3'b000, 10'b1_00_010_0_001 } & {13{r_ini_ph[3] }}; // Init : load mode register (BL=2, CAS=2)
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end
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else begin
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// 16 MB
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r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph & r_ram_cyc[0]}} // 512 cols
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| { 1'b0, r_addr_mux[21:10] } & {13{r_act_ph & r_ram_cyc[1]}} // 4096 rows
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| { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph & r_ram_cyc[2]}} // 512 cols
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| { 4'b0010, r_addr_col[9:2], 1'b0 } & {13{r_wr_ph & r_ram_cyc[3]}} // 512 cols
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| { 3'b001, 10'b000000000 } & {13{r_ini_ph[0] }} // Init : precharge all
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| { 3'b000, 10'b0_00_010_0_001 } & {13{r_ini_ph[3] }}; // Init : load mode register (BL=2, CAS=2)
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end
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end
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// Bank address
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r_ba_sdr <= r_ba1_ctr & {2{r_rd_ph & r_ram_cyc[0]}} // 32-bit read
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| r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}} // Activate
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| r_ba1_ctr & {2{r_rd_ph & r_ram_cyc[2]}} // 32-bit read with auto-precharge
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| r_ba1_ctr & {2{r_wr_ph & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
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end
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end
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// ======================================================
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// SDRAM command generation
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// ======================================================
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reg [2:0] r_cmd_sdr;
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always@(posedge rst or posedge clk) begin : COMMAND_GEN
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reg [2:0] v_cmd_0;
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reg [2:0] v_cmd_1;
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reg [2:0] v_cmd_2;
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reg [2:0] v_cmd_3;
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reg [2:0] v_cmd_4;
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reg [2:0] v_cmd_5;
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reg [2:0] v_cmd_6;
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if (rst) begin
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r_cmd_sdr <= CMD_NOP;
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end
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else begin
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v_cmd_0 = CMD_RD | {3{~r_rd_ph }};
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v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
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v_cmd_2 = CMD_RD | {3{~r_rd_ph }};
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v_cmd_3 = CMD_WR | {3{~r_wr_ph }};
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v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
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v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
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v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
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r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
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& (v_cmd_1 | {3{~r_ram_cyc[1]}})
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& (v_cmd_2 | {3{~r_ram_cyc[2]}})
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& (v_cmd_3 | {3{~r_ram_cyc[3]}})
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& (v_cmd_4 | {3{~r_ram_cyc[3]}})
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& (v_cmd_5 | {3{~r_ram_cyc[3]}})
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& (v_cmd_6 | {3{~r_ram_cyc[3]}});
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end
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end
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assign sdram_cs_n = 1'b0;
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// Command and address
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/* verilator lint_off STMTDLY */
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always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
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always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
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always@(*) sdram_we_n = #Tco_dly r_cmd_sdr[0];
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always@(*) sdram_ba = #Tco_dly r_ba_sdr;
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always@(*) sdram_addr = #Tco_dly r_addr_sdr;
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/* verilator lint_on STMTDLY */
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// ======================================================
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// Data being read
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// ======================================================
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reg [3:0] r_data_vld;
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reg r_data_sel;
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reg [15:0] r_lrdata_p0;
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reg [15:0] r_hrdata_p0;
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reg [15:0] r_hrdata_p1;
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wire [15:0] w_rdata_p0;
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always@(posedge rst or posedge clk) begin : DATA_READ
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if (rst) begin
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r_data_vld <= 4'b0000;
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r_data_sel <= 1'b0;
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r_lrdata_p0 <= 16'h0000;
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r_hrdata_p0 <= 16'h0000;
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r_hrdata_p1 <= 16'h0000;
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end
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else begin
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if (r_ram_cyc[3]) begin
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r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
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r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
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r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
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r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
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end
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r_data_sel <= r_ram_cyc[1] | r_ram_cyc[3];
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r_lrdata_p0 <= sdram_dq_i[15:0];
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r_hrdata_p0 <= sdram_dq_i[31:16];
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r_hrdata_p1 <= r_hrdata_p0;
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end
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end
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// 32-bit to 16-bit multiplexer
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assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
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// Access Port #0
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assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
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assign valid_b0 = r_data_vld[0];
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// Access Port #1
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assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
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assign valid_b1 = r_data_vld[1];
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// Access Port #2
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assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
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assign valid_b2 = r_data_vld[2];
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// Access Port #3
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assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
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assign valid_b3 = r_data_vld[3];
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// ======================================================
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// Data being written
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// ======================================================
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reg [3:0] r_data_fe_p0;
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reg [3:0] r_data_fe_p1;
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reg r_data_oe;
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reg [15:0] r_wdata_p2a;
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reg [15:0] r_wdata_p2b;
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reg [31:0] r_wdata_p3;
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reg [1:0] r_bena_p2a;
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reg [1:0] r_bena_p2b;
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reg [3:0] r_bena_p3;
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always@(posedge rst or posedge clk) begin : DATA_WRITE
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if (rst) begin
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r_data_fe_p0 <= 4'b0000;
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r_data_fe_p1 <= 4'b0000;
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r_data_oe <= 1'b0;
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r_wdata_p2a <= 16'h0000;
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r_wdata_p2b <= 16'h0000;
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r_wdata_p3 <= 32'h0000_0000;
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r_bena_p2a <= 2'b00;
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r_bena_p2b <= 2'b00;
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r_bena_p3 <= 4'b00_00;
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end
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else begin
|
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if (r_ram_cyc[3]) begin
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r_data_fe_p0 <= r_wr_act & r_ram_ph;
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r_data_oe <= r_wr_ph;
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end
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else if (r_ram_cyc[1]) begin
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r_data_fe_p0 <= 4'b0000;
|
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r_data_oe <= 1'b0;
|
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end
|
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r_data_fe_p1 <= r_data_fe_p0;
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|
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if (SDRAM_WIDTH == 32) begin
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// 16-bit -> 32-bit bus
|
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if (r_data_sel) begin
|
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r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
|
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| wdata_b1 & {16{r_data_fe_p1[1]}}
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| wdata_b2 & {16{r_data_fe_p1[2]}}
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| wdata_b3 & {16{r_data_fe_p1[3]}};
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r_bena_p2b <= bena_b0 & {2{r_data_fe_p1[0]}}
|
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| bena_b1 & {2{r_data_fe_p1[1]}}
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| bena_b2 & {2{r_data_fe_p1[2]}}
|
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| bena_b3 & {2{r_data_fe_p1[3]}}
|
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| {2{~|r_data_fe_p1}};
|
|
end
|
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else begin
|
|
r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
|
|
| wdata_b1 & {16{r_data_fe_p1[1]}}
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| wdata_b2 & {16{r_data_fe_p1[2]}}
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| wdata_b3 & {16{r_data_fe_p1[3]}};
|
|
r_bena_p2a <= bena_b0 & {2{r_data_fe_p1[0]}}
|
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| bena_b1 & {2{r_data_fe_p1[1]}}
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| bena_b2 & {2{r_data_fe_p1[2]}}
|
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| bena_b3 & {2{r_data_fe_p1[3]}}
|
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| {2{~|r_data_fe_p1}};
|
|
end
|
|
r_wdata_p3 <= { r_wdata_p2b, r_wdata_p2a };
|
|
r_bena_p3 <= { r_bena_p2b, r_bena_p2a };
|
|
end
|
|
else begin
|
|
// 16-bit bus
|
|
r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
|
|
| wdata_b1 & {16{r_data_fe_p1[1]}}
|
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| wdata_b2 & {16{r_data_fe_p1[2]}}
|
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| wdata_b3 & {16{r_data_fe_p1[3]}};
|
|
r_wdata_p2b <= r_wdata_p2a;
|
|
r_wdata_p3 <= { 16'h0000, r_wdata_p2b };
|
|
|
|
r_bena_p2a <= bena_b0 & {2{r_data_fe_p1[0]}}
|
|
| bena_b1 & {2{r_data_fe_p1[1]}}
|
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| bena_b2 & {2{r_data_fe_p1[2]}}
|
|
| bena_b3 & {2{r_data_fe_p1[3]}}
|
|
| {2{~|r_data_fe_p1}};
|
|
r_bena_p2b <= r_bena_p2a;
|
|
r_bena_p3 <= { 2'b00, r_bena_p2b };
|
|
end
|
|
end
|
|
end
|
|
|
|
// Output mask, data & enable
|
|
/* verilator lint_off STMTDLY */
|
|
always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
|
|
always@(*) sdram_dq_o = #Tco_dly r_wdata_p3;
|
|
always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
|
|
/* verilator lint_on STMTDLY */
|
|
|
|
// Access Port #0
|
|
assign fetch_b0 = r_data_fe_p0[0];
|
|
|
|
// Access Port #1
|
|
assign fetch_b1 = r_data_fe_p0[1];
|
|
|
|
// Access Port #2
|
|
assign fetch_b2 = r_data_fe_p0[2];
|
|
|
|
// Access Port #3
|
|
assign fetch_b3 = r_data_fe_p0[3];
|
|
|
|
endmodule /* verilator tracing_on */
|