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//`include "arg_defs.vh"
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module sdram_ctrl /* verilator tracing_off */
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(
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//--------------------
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// Clocks and reset --
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//--------------------
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// Global reset
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input rst,
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// Controller clock
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input clk,
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// Sequencer cycles
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input [11:0] seq_cyc,
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// Sequencer phase
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input seq_ph,
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// Refresh cycle
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input refr_cyc,
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//------------------------
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// Access port #1 (CPU) --
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//------------------------
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// RAM select
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input ap1_ram_sel,
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// Address bus
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input [23:1] ap1_address,
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// Read enable
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input ap1_rden,
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// Write enable
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input ap1_wren,
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// Byte enable
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input [1:0] ap1_bena,
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// Data bus (read)
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output [15:0] ap1_rddata,
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// Data bus (write)
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input [15:0] ap1_wrdata,
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// Burst size
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input [2:0] ap1_bst_siz,
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// Read burst active
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output reg ap1_rd_bst_act,
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// Write burst active
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output ap1_wr_bst_act,
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//------------------------
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// Access port #2 (GPU) --
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//------------------------
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// RAM select
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input ap2_ram_sel,
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// Address bus
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input [23:1] ap2_address,
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// Read enable
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input ap2_rden,
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// Write enable
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input ap2_wren,
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// Byte enable
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input [1:0] ap2_bena,
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// Data bus (read)
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output [15:0] ap2_rddata,
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// Data bus (write)
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input [15:0] ap2_wrdata,
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// Burst size
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input [2:0] ap2_bst_siz,
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// Read burst active
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output reg ap2_rd_bst_act,
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// Write burst active
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output ap2_wr_bst_act,
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//------------------------
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// Access port #3 (CTL) --
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//------------------------
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// RAM select
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input ap3_ram_sel,
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// Address bus
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input [23:1] ap3_address,
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// Read enable
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input ap3_rden,
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// Write enable
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input ap3_wren,
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// Byte enable
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input [1:0] ap3_bena,
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// Data bus (read)
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output [15:0] ap3_rddata,
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// Data bus (write)
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input [15:0] ap3_wrdata,
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// Burst size
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input [2:0] ap3_bst_siz,
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// Read burst active
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output reg ap3_rd_bst_act,
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// Write burst active
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output ap3_wr_bst_act,
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//------------------------
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// SDRAM memory signals --
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//------------------------
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// SDRAM controller ready
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output reg sdram_rdy,
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// SDRAM chip select
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output reg sdram_cs_n,
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// SDRAM row address strobe
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output reg sdram_ras_n,
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// SDRAM column address strobe
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output reg sdram_cas_n,
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// SDRAM write enable
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output reg sdram_we_n,
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// SDRAM DQ masks
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output reg [1:0] sdram_dqm_n,
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// SDRAM bank address
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output reg [1:0] sdram_ba,
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// SDRAM address
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output reg [11:0] sdram_addr,
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// SDRAM data
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output reg sdram_dq_oe,
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output reg [15:0] sdram_dq_o,
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input [15:0] sdram_dq_i
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);
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// SDRAM memory size
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parameter SDRAM_SIZE = 16;
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// SDRAM operational frequency
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parameter SDRAM_FREQ = 85909090;
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// Hidden refresh mode
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parameter HIDDEN_REFRESH = 0;
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// MODE REGISTER SET value (RS = 00, WB = 0, OP = 00, CL = 010, BT = 0, BL = 011)
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parameter MRS_VALUE = 12'b000000100011;
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// Refresh period
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parameter REF_COUNT = ((SDRAM_FREQ / ((12 * 64000)))) - 1;
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// Clock-to-output delay
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parameter Tco_dly = 4.5;
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// Port select signals
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reg [2:0] r_psel; // Port select (one hot)
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reg [2:0] r_psel_dly; // Port select delayed
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// Refresh signals
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reg r_refr_req; // Refresh requested
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reg r_refr_act; // Refresh active
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reg r_refr_ack; // Refresh acknowledged
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reg [31:0] r_refr_ctr; // Refresh counter
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// Port multiplexer signals
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wire w_rden; // Read enable
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reg r_rd_reg; // Registered read enable
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reg r_rd_act; // Read active
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wire w_wren; // Write enable
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reg r_wr_reg; // Registered write enable
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reg r_wr_act; // Write active
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wire w_ram_sel; // RAM select
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reg [2:0] r_rd_bctr; // Read burst counter
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reg [2:0] r_wr_bctr; // Write burst counter
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wire [2:0] w_bst_siz; // Burst size (load value of burst counters)
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reg [2:0] r_bst_stp; // Burst stop
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wire [1:0] w_dqm; // Bytes masks
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wire [23:1] w_addr; // Address
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reg [15:0] r_rddata; // Data read
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wire [15:0] w_wrdata; // Data written
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// SDRAM speed adjustment
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wire w_rd_start; // Read start condition
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wire w_wr_start; // Write start condition
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wire [3:0] w_rd_cycle; // First read cycle number
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// Initialization signals
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reg [2:0] r_init_fsm; // SDRAM initialization state machine
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reg [10:0] r_init_tmr; // SDRAM initialization timer
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// Output registers
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reg r_sdram_cs_n; // SDRAM chip select
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reg r_sdram_ras_n; // SDRAM row address strobe
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reg r_sdram_cas_n; // SDRAM column address strobe
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reg r_sdram_we_n; // SDRAM write enable
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reg [1:0] r_sdram_dqm_n; // SDRAM DQ masks
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reg [1:0] r_sdram_ba; // SDRAM bank address
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reg [11:0] r_sdram_addr; // SDRAM address
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reg [15:0] r_sdram_dq_o; // SDRAM DQ output
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reg r_sdram_dq_oe; // SDRAM DQ output enable
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// Signal multiplexing based on the port select
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assign w_wren = (ap1_wren & r_psel[0])
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| (ap2_wren & r_psel[1])
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| (ap3_wren & r_psel[2]);
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assign w_rden = (ap1_rden & r_psel[0])
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| (ap2_rden & r_psel[1])
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| (ap3_rden & r_psel[2]);
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assign w_ram_sel = (HIDDEN_REFRESH == 1)
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? (r_psel[0] | r_psel[1] | r_psel[2])
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: (r_psel[0] | r_psel[1] | r_psel[2]) & ~r_refr_req;
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assign w_dqm[0] = (ap1_bena[0] & r_psel[0])
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| (ap2_bena[0] & r_psel[1])
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| (ap3_bena[0] & r_psel[2]);
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assign w_dqm[1] = (ap1_bena[1] & r_psel[0])
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| (ap2_bena[1] & r_psel[1])
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| (ap3_bena[1] & r_psel[2]);
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assign w_bst_siz[2] = (ap1_bst_siz[2] & r_psel[0])
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| (ap2_bst_siz[2] & r_psel[1])
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| (ap3_bst_siz[2] & r_psel[2]);
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assign w_bst_siz[1] = (ap1_bst_siz[1] & r_psel[0])
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| (ap2_bst_siz[1] & r_psel[1])
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| (ap3_bst_siz[1] & r_psel[2]);
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assign w_bst_siz[0] = (ap1_bst_siz[0] & r_psel[0])
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| (ap2_bst_siz[0] & r_psel[1])
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| (ap3_bst_siz[0] & r_psel[2]);
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assign w_addr[23:1] = (ap1_address[23:1] & {23{r_psel[0]}})
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| (ap2_address[23:1] & {23{r_psel[1]}})
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| (ap3_address[23:1] & {23{r_psel[2]}});
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assign w_wrdata[15:0] = (ap1_wrdata[15:0] & {16{r_psel[0]}})
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| (ap2_wrdata[15:0] & {16{r_psel[1]}})
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| (ap3_wrdata[15:0] & {16{r_psel[2]}});
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// SDRAM speed adjustment
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assign w_rd_cycle = (SDRAM_FREQ < 50000000) ? 4'd2 : 4'd3;
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assign w_rd_start = (SDRAM_FREQ < 50000000) ? (seq_cyc[2] & r_rd_reg) : (seq_cyc[4] & r_rd_reg);
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assign w_wr_start = (SDRAM_FREQ < 50000000) ? (seq_cyc[0] & w_wren & w_ram_sel) : (seq_cyc[1] & r_wr_reg);
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// Write burst active flags, one cycle before "r_wr_act"
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assign ap1_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[0];
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assign ap2_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[1];
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assign ap3_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[2];
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// SDRAM data read
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assign ap1_rddata = r_rddata;
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assign ap2_rddata = r_rddata;
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assign ap3_rddata = r_rddata;
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// Hidden refresh / port select :
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//-------------------------------
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// rst : Global reset
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// clk : SDRAM controller clock
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// seq_cyc : Sequencer cycle (0 to 11)
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// seq_ph : Sequencer phase (0 or 1)
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// r_refr_req : Internal refresh cycle request
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// r_refr_ack : Internal refresh cycle acknowledge
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// r_refr_ctr : Internal refresh counter
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// r_psel : Port select (one hot)
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// r_psel_dly : Delayed port select
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// ap1_ram_sel : Port #1 access
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// ap2_ram_sel : Port #2 access
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// ap3_ram_sel : Port #3 access
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always @(posedge rst or posedge clk) begin
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if (rst) begin
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// Refresh counter
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r_refr_ctr <= REF_COUNT;
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// Refresh cycle request
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r_refr_req <= 1'b0;
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end else begin
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// Hidden refresh case
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if (HIDDEN_REFRESH == 1) begin
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// Sequencer cycle #11
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if (seq_cyc[11]) begin
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// Internal refresh counter
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if (r_refr_ctr == 0) begin
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r_refr_req <= 1'b1;
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r_refr_ctr <= REF_COUNT;
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end
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else begin
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r_refr_ctr <= r_refr_ctr - 1;
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end
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end
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// When refresh cycle is acknowledged
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if (r_refr_ack == 1'b1) begin
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// Clear the refresh cycle request
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r_refr_req <= 1'b0;
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end
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end else begin
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// External refresh
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r_refr_req <= refr_cyc;
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end
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end
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if (rst) begin
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// Port select
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r_psel <= 3'b000;
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r_psel_dly <= 3'b000;
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end else begin
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// Access port select
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if (seq_cyc[11]) begin
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if (!seq_ph) begin
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// Phase #0 : select port #1 (CPU) -> #3 (CTL) -> none
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r_psel[0] <= ap1_ram_sel;
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r_psel[1] <= 1'b0;
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r_psel[2] <= ap3_ram_sel & ~ap1_ram_sel;
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end
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else begin
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// Phase #1 : select port #2 (GPU) -> #1 (CPU) -> #3 (CTL) -> none
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r_psel[0] <= ap1_ram_sel & ~ap2_ram_sel;
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r_psel[1] <= ap2_ram_sel;
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r_psel[2] <= ap3_ram_sel & ~(ap1_ram_sel | ap2_ram_sel);
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end
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end
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// Delayed port select for data read multiplexer
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if (seq_cyc[1]) begin
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r_psel_dly <= r_psel;
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end
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end
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end
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// Burst activities :
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//-------------------
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// rst : Global reset
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// clk : SDRAM controller clock
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// w_rd_start : Read start conditions
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// w_wr_start : Write start conditions
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// r_rd_reg : Read mode (registered)
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// r_rd_act : Read active
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// r_wr_act : Write active
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// r_rd_bctr : Burst read counter
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// r_wr_bctr : Burst write counter
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// r_psel_dly : Port select delayed
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always @(posedge rst or posedge clk) begin
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if (rst) begin
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// Burst signals
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r_rd_act <= 1'b0;
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r_wr_act <= 1'b0;
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r_rd_bctr <= 3'b000;
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r_wr_bctr <= 3'b000;
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ap1_rd_bst_act <= 1'b0;
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ap2_rd_bst_act <= 1'b0;
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ap3_rd_bst_act <= 1'b0;
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// Data bus
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r_rddata <= 16'h0000;
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r_sdram_dqm_n <= 2'b11;
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r_sdram_dq_oe <= 1'b0;
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r_sdram_dq_o <= 16'h0000;
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end else begin
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// Prepare write burst cycles
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if (w_wr_start) begin
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// Set the active bits
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r_wr_act <= 1'b1;
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// Start the burst counter
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r_wr_bctr <= w_bst_siz;
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end
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// Prepare read burst cycles
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if (w_rd_start) begin
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// Set the active bits
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r_rd_act <= 1'b1;
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// Start the burst counter
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r_rd_bctr <= r_bst_stp;
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end
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// Read burst counter management
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if (r_rd_act) begin
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if (r_rd_bctr == 0) begin
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// Burst finished : clear the active bit
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r_rd_act <= 1'b0;
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end
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else begin
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r_rd_bctr <= r_rd_bctr - 3'b1;
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end
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end
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// Write burst counter management
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if (r_wr_act) begin
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if (r_wr_bctr == 0) begin
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// Burst finished : clear the active bit
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r_wr_act <= 1'b0;
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end
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else begin
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r_wr_bctr <= r_wr_bctr - 3'b1;
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end
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end
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// Read burst active flags, one cycle after "r_rd_act"
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ap1_rd_bst_act <= r_rd_act & r_psel_dly[0];
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ap2_rd_bst_act <= r_rd_act & r_psel_dly[1];
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ap3_rd_bst_act <= r_rd_act & r_psel_dly[2];
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// Read SDRAM data
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r_rddata <= sdram_dq_i;
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// Write SDRAM data / DQM management
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if (r_wr_act) begin
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r_sdram_dqm_n[0] <= ~w_dqm[0];
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r_sdram_dqm_n[1] <= ~w_dqm[1];
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r_sdram_dq_oe <= 1'b1;
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r_sdram_dq_o <= w_wrdata;
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end
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else begin
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r_sdram_dqm_n[0] <= ~r_rd_reg;
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r_sdram_dqm_n[1] <= ~r_rd_reg;
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r_sdram_dq_oe <= 1'b0;
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r_sdram_dq_o <= 16'h0000;
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end
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end
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end
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// SDRAM controller state machine :
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//---------------------------------
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// rst : Global reset
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// clk : SDRAM controller clock
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// seq_cyc : Sequencer cycle
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// r_refr_req : Refresh cycle requested
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// r_refr_act : Refresh cycle active
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// r_refr_ack : Refresh cycle acknowledge
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// w_ram_sel : SDRAM selected
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// w_rden : Read enable flag
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// w_wren : Write enable flag
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// r_rd_reg : Read mode (registered)
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// r_wr_reg : Write mode (registered)
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// w_bst_siz : Burst size (1 to 8 words)
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// r_bst_stp : Burst stop cycle
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// r_init_fsm : SDRAM initialization state
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// r_init_tmr : SDRAM initialization timer (>100 us)
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always @(posedge rst or posedge clk) begin
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if (rst) begin
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// SDRAM outputs
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r_sdram_cs_n <= 1'b1;
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r_sdram_ras_n <= 1'b1;
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r_sdram_cas_n <= 1'b1;
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r_sdram_we_n <= 1'b1;
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r_sdram_ba <= 2'b00;
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r_sdram_addr <= 12'b000000000000;
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// Controller state
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r_rd_reg <= 1'b0;
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r_wr_reg <= 1'b0;
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r_bst_stp <= 3'b000;
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sdram_rdy <= 1'b0;
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r_refr_ack <= 1'b0;
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r_refr_act <= 1'b0;
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// 1024 * 12 cycles > 100 us
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r_init_tmr <= 11'd0; // 143 us
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r_init_fsm <= 3'b000;
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end else begin
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// Default : NOPs
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r_sdram_ras_n <= 1'b1;
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r_sdram_cas_n <= 1'b1;
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r_sdram_we_n <= 1'b1;
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if (r_init_fsm[2]) begin
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// Chip select management
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if (seq_cyc[0]) begin
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// RAM selected or refresh request
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r_sdram_cs_n <= ~(w_ram_sel | r_refr_req);
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end
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// If there is an active refresh
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if (r_refr_act) begin
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//------------------
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// Refresh cycles --
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//------------------
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// Cycle #0 : clear read/write enable signals
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r_rd_reg <= 1'b0;
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r_wr_reg <= 1'b0;
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// Cycle #2 : prepare AUTO REFRESH cmd for cycle #3
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if (seq_cyc[2]) begin
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r_sdram_ras_n <= 1'b0;
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r_sdram_cas_n <= 1'b0;
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end
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// Cycle #9 : acknowledge the refresh request
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if (seq_cyc[9]) begin
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// Hidden refresh case
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if (HIDDEN_REFRESH == 1) begin
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r_refr_ack <= 1'b1;
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end
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r_refr_act <= 1'b0;
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end
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end
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else begin
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//-----------------
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// Normal cycles --
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//-----------------
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// Hidden refresh case
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if (HIDDEN_REFRESH == 1) begin
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// Clear any refresh acknowledge
|
|
r_refr_ack <= 1'b0;
|
|
end
|
|
if (seq_cyc[0]) begin
|
|
// If no access, activate refresh
|
|
r_refr_act <= ~((w_rden | w_wren) & w_ram_sel) & r_refr_req;
|
|
// Register read/write enable signals
|
|
r_rd_reg <= w_rden & w_ram_sel;
|
|
r_wr_reg <= w_wren & w_ram_sel;
|
|
// Register the burst stop
|
|
r_bst_stp <= w_bst_siz;
|
|
end
|
|
// Cycle #0 : prepare ACTIVATE cmd for cycle #1
|
|
// set the row address and the bank number
|
|
if ((seq_cyc[0]) && (w_ram_sel) && ((w_rden) || (w_wren))) begin
|
|
r_sdram_ras_n <= 1'b0;
|
|
if (SDRAM_SIZE == 16) begin
|
|
// 4096 rows : 12 address lines
|
|
r_sdram_addr <= w_addr[23:12];
|
|
// 4 banks : 2 address lines
|
|
r_sdram_ba <= w_addr[11:10];
|
|
end else begin
|
|
// 4096 rows : 12 address lines
|
|
r_sdram_addr <= w_addr[22:11];
|
|
// 4 banks : 2 address lines
|
|
r_sdram_ba <= w_addr[10:9];
|
|
end
|
|
end
|
|
// Cycle #1/2 : prepare READ/WRITE cmd for next cycle
|
|
// set the column address and the bank number
|
|
if ((seq_cyc[w_rd_cycle - 1]) && ((r_rd_reg) || (r_wr_reg))) begin
|
|
r_sdram_cas_n <= 1'b0;
|
|
r_sdram_we_n <= ~r_wr_reg;
|
|
if (SDRAM_SIZE == 16)
|
|
// 512 columns : 9 address lines
|
|
r_sdram_addr <= {3'b010, w_addr[9:1]};
|
|
else
|
|
// 256 columns : 8 address lines
|
|
r_sdram_addr <= {4'b0100, w_addr[8:1]};
|
|
end
|
|
// Cycles #2/3+ : prepare the PRECHARGE cmd (burst stop)
|
|
//if ((seq_cyc[w_rd_cycle + r_bst_stp]) && ((r_rd_reg) || (r_wr_reg))) begin
|
|
// r_sdram_ras_n <= 1'b0;
|
|
// r_sdram_we_n <= 1'b0;
|
|
//end
|
|
end
|
|
end
|
|
else begin
|
|
//---------------
|
|
// Init cycles --
|
|
//---------------
|
|
if (r_init_tmr[10]) begin
|
|
// Select SDRAM
|
|
r_sdram_cs_n <= 1'b0;
|
|
case (r_init_fsm[1:0])
|
|
2'd0 : begin
|
|
// Prepare PRECHARGE ALL cmd
|
|
if (seq_cyc[3]) begin
|
|
r_sdram_ras_n <= 1'b0;
|
|
r_sdram_we_n <= 1'b0;
|
|
r_sdram_addr[10] <= 1'b1;
|
|
end
|
|
end
|
|
2'd1 : begin
|
|
// Prepare AUTO REFRESH cmd
|
|
if (seq_cyc[3]) begin
|
|
r_sdram_ras_n <= 1'b0;
|
|
r_sdram_cas_n <= 1'b0;
|
|
end
|
|
end
|
|
2'd2 : begin
|
|
// Prepare AUTO REFRESH cmd
|
|
if (seq_cyc[3]) begin
|
|
r_sdram_ras_n <= 1'b0;
|
|
r_sdram_cas_n <= 1'b0;
|
|
end
|
|
end
|
|
2'd3 : begin
|
|
// Prepare MODE REGISTER SET value
|
|
if (seq_cyc[1]) begin
|
|
r_sdram_addr <= MRS_VALUE;
|
|
end
|
|
// Prepare MODE REGISTER SET cmd
|
|
if (seq_cyc[3]) begin
|
|
r_sdram_ras_n <= 1'b0;
|
|
r_sdram_cas_n <= 1'b0;
|
|
r_sdram_we_n <= 1'b0;
|
|
end
|
|
// SDRAM is initialized
|
|
if (seq_cyc[10]) begin
|
|
sdram_rdy <= 1'b1;
|
|
end
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
// Cycle #11 : next state
|
|
if (seq_cyc[11]) begin
|
|
r_init_fsm <= r_init_fsm + 3'd1;
|
|
end
|
|
end
|
|
else begin
|
|
// Deselect SDRAM
|
|
r_sdram_cs_n <= 1'b1;
|
|
// Cycle #11 : timer management
|
|
if (seq_cyc[11]) begin
|
|
r_init_tmr <= r_init_tmr + 11'd1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
// TCO delay on all outputs
|
|
always@(r_sdram_cs_n or r_sdram_ras_n or r_sdram_cas_n or r_sdram_we_n or
|
|
r_sdram_dqm_n or r_sdram_ba or r_sdram_addr or r_sdram_dq_oe or r_sdram_dq_o) begin
|
|
`ifdef SIMULATION
|
|
|
|
`ifdef verilator3
|
|
// Cycle based simulation
|
|
sdram_cs_n = r_sdram_cs_n;
|
|
sdram_ras_n = r_sdram_ras_n;
|
|
sdram_cas_n = r_sdram_cas_n;
|
|
sdram_we_n = r_sdram_we_n;
|
|
sdram_dqm_n = r_sdram_dqm_n;
|
|
sdram_ba = r_sdram_ba;
|
|
sdram_addr = r_sdram_addr;
|
|
sdram_dq_oe = r_sdram_dq_oe;
|
|
sdram_dq_o = r_sdram_dq_o;
|
|
`else
|
|
// Timing based simulation
|
|
sdram_cs_n = #Tco_dly r_sdram_cs_n;
|
|
sdram_ras_n = #Tco_dly r_sdram_ras_n;
|
|
sdram_cas_n = #Tco_dly r_sdram_cas_n;
|
|
sdram_we_n = #Tco_dly r_sdram_we_n;
|
|
sdram_dqm_n = #Tco_dly r_sdram_dqm_n;
|
|
sdram_ba = #Tco_dly r_sdram_ba;
|
|
sdram_addr = #Tco_dly r_sdram_addr;
|
|
sdram_dq_oe = #Tco_dly r_sdram_dq_oe;
|
|
sdram_dq_o = #Tco_dly r_sdram_dq_o;
|
|
`endif
|
|
|
|
`else
|
|
// Synthesis
|
|
sdram_cs_n = r_sdram_cs_n;
|
|
sdram_ras_n = r_sdram_ras_n;
|
|
sdram_cas_n = r_sdram_cas_n;
|
|
sdram_we_n = r_sdram_we_n;
|
|
sdram_dqm_n = r_sdram_dqm_n;
|
|
sdram_ba = r_sdram_ba;
|
|
sdram_addr = r_sdram_addr;
|
|
sdram_dq_oe = r_sdram_dq_oe;
|
|
sdram_dq_o = r_sdram_dq_o;
|
|
`endif
|
|
end
|
|
|
|
`ifdef SIMULATION
|
|
|
|
`ifndef verilator3
|
|
// Setup and hold times check for DQ
|
|
reg r_dq_noti;
|
|
|
|
specify
|
|
specparam
|
|
Tsu_dly = 0.7, // Input setup time
|
|
Th_dly = -0.5; // Input hold time
|
|
$setuphold(posedge clk, sdram_dq_i, Tsu_dly, Th_dly, r_dq_noti);
|
|
endspecify
|
|
|
|
always @(r_dq_noti)
|
|
begin
|
|
$display($realtime, " ns : Setup/Hold time violation on DQ inputs");
|
|
end
|
|
`endif
|
|
|
|
`endif
|
|
|
|
endmodule
|
|
|
|
/* verilator tracing_off */
|