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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY mmu IS
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GENERIC
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(
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system : integer := 0 -- 0=Atari XL,1=Atari 800, 10=Atari5200 (space left for more systems)
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);
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PORT
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(
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ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 11);
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REF_N : IN STD_LOGIC;
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RD4 : IN STD_LOGIC;
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RD5 : IN STD_LOGIC;
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MPD_N : IN STD_LOGIC;
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REN : IN STD_LOGIC; --ROM ON on/off
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BE_N: IN STD_LOGIC; --BASIC ON on/off
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MAP_N : IN STD_LOGIC;
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S4_N : OUT STD_LOGIC;
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S5_N : OUT STD_LOGIC;
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BASIC : OUT STD_LOGIC;
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IO : OUT STD_LOGIC;
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OS : OUT STD_LOGIC;
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CI : OUT STD_LOGIC
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);
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END mmu;
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ARCHITECTURE vhdl of mmu is
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signal S4 : std_logic;
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signal S5 : std_logic;
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signal OSEN : std_logic;
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signal BASIC_INT : std_logic;
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signal OS_INT : std_logic;
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signal IO_INT : std_logic;
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BEGIN
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--CHIP MMU800XL GAL16V8 COMPLEX_MODE
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--
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--A11 A12 A13 A14 A15 MAP RD4 RD5 REN GND
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--REF S5 BASIC MPD OS CI IO BE S4 VCC
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--
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--/S4 = /A13 & /A14 & A15 & RD4 & REF;
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--/S5 = A13 & /A14 & A15 & RD5 & REF;
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--
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--/IO = A12 & /A11 & /A13 & A14 & A15 & REF;
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--
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--/OS = A13 & A14 & A15 & REN & REF
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--+ /A12 & /A13 & A14 & A15 & REN & REF
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--+ A12 & A11 & /A13 & A14 & A15 & MPD & REN & REF
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--+ A12 & /A11 & /A13 & A14 & /A15 & /MAP & REN & REF;
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--
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--/CI = /A13 & /A14 & A15 & RD4 & REF
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--+ A13 & /A14 & A15 & RD5 & REF
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--+ A13 & /BE & /A14 & A15 & /RD5 & REF
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--+ /OS
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--+ A12 & /A11 & /A13 & A14 & A15 & REF
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--+ /REF;
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--
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--/BASIC = A13 & /BE & /A14 & A15 & /RD5 & REF;
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S4 <= not(ADDR(13)) and NOT(ADDR(14)) and ADDR(15) and RD4 and REF_N; --100X (8000-9fff)
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S5 <= ADDR(13) and NOT(ADDR(14)) and ADDR(15) and RD5 and REF_N; --101x (A000-Bfff)
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IO_INT <= ADDR(12) and NOT(ADDR(11)) and NOT(ADDR(13)) and ADDR(14) and ADDR(15) and REF_N; --11010 (D000-D7ff)
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OSEN <= REN and REF_N;
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OS_INT <= (ADDR(13) and ADDR(14) and ADDR(15) and OSEN) --111x (E000-Ffff)
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or (not(ADDR(12)) and not(ADDR(13)) and ADDR(14) and ADDR(15) and OSEN) --1100 (C000-Cfff)
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or (ADDR(12) and ADDR(11) and not(ADDR(13)) and ADDR(14) and ADDR(15) and MPD_N and OSEN) --11011(D800-Dfff)
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or (ADDR(12) and NOT(ADDR(11)) and not(ADDR(13)) and ADDR(14) and NOT(ADDR(15)) and NOT(MAP_N) and OSEN); --01010(5000-5fff) self test
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CI <= S4
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or S5
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or BASIC_INT
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or OS_INT
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or IO_INT
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or not(REF_N); --Refresh cycle
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BASIC_INT <= ADDR(13) and not(BE_N) and not(ADDR(14)) and ADDR(15) and NOT(RD5) and REF_N; --101x (A000-Bfff) when no cart and basic on
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S4_N <= not(S4);
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S5_N <= not(S5);
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BASIC <= BASIC_INT;
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OS <= OS_INT;
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IO <= IO_INT;
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END vhdl;
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