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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY irq_glue IS
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PORT
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(
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pokey_irq : in std_logic;
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pia_irqa : in std_logic;
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pia_irqb : in std_logic;
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pbi_irq : in std_logic;
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combined_irq : out std_logic
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);
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end irq_glue;
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architecture vhdl of irq_glue is
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begin
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combined_irq <= pokey_irq and pia_irqa and pia_irqb and pbi_irq;
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end vhdl;
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