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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY wide_delay_line IS
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generic(COUNT : natural := 1; WIDTH : natural :=1);
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PORT
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(
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CLK : IN STD_LOGIC;
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SYNC_RESET : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
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RESET_N : IN STD_LOGIC;
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DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
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);
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END wide_delay_line;
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ARCHITECTURE vhdl OF wide_delay_line IS
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type shift_reg_type is array(COUNT-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
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signal shift_reg : shift_reg_type;
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signal shift_next : shift_reg_type;
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BEGIN
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-- register
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process(clk,reset_n)
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begin
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if (reset_N = '0') then
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shift_reg <= (others=>(others=>'0'));
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elsif (clk'event and clk='1') then
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shift_reg <= shift_next;
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end if;
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end process;
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-- shift on enable
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process(shift_reg,enable,data_in,sync_reset)
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begin
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shift_next <= shift_reg;
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if (enable = '1') then
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shift_next <= data_in&shift_reg(COUNT-1 downto 1);
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end if;
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if (sync_reset = '1') then
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shift_next <= (others=>(others=>'0'));
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end if;
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end process;
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-- output
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gen_output:
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for index in 0 to WIDTH-1 generate
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data_out(index) <= shift_reg(0)(index);
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end generate;
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END vhdl;
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