/aeon_lite/pll/coregen.cgp - EclaireXL - 64kib

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repo2/aeon_lite/pll/coregen.cgp

       SET busformat = BusFormatAngleBracketNotRipped
       SET designentry = VHDL
       SET device = xc6slx9
       SET devicefamily = spartan6
       SET flowvendor = Other
       SET package = tqg144
       SET speedgrade = -3
       SET verilogsim = false
       SET vhdlsim = true

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