repo2/aeon_lite/pll/coregen.cgp
| 149 | markw | SET busformat = BusFormatAngleBracketNotRipped
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SET designentry = VHDL
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SET device = xc6slx9
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET package = tqg144
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SET speedgrade = -3
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SET verilogsim = false
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SET vhdlsim = true
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