Feature #15
openImplement programmable PLL
0%
Description
See if the programmable PLL works. This will allow us to support different/custom VGA modes, once we have EDID/DDC working. For now I just want to find out if its alive.
Files
Updated by foft almost 7 years ago
- File Si5351-B.pdf Si5351-B.pdf added
Attaching PLL chip datasheet
Updated by foft about 6 years ago
- File Si5351A-RevB-Registers.h Si5351A-RevB-Registers.h added
Attached header file for programming clk0->10MHz and clk1->30MHz.
These are generated with clock builder pro, downloaded from ic vendor web site.
Updated by admin about 6 years ago
- Priority changed from Normal to Urgent
Going to power this up urgently before new boards made, to check hardware side is fine.
Updated by foft about 6 years ago
To do this I need to add i2c support to the ZPU. I'm out of ROM space without easy fixes. There is actually quite a lot space even on the EBA2, so adding 8K extra for now. Currently it was using bit 15 to decide rom/ram. I made it use 14 and 15 to choose ram. There is some hack I put in for the mist external sector buffer (it writes to ROM area!!) which might be broken by this.
Updated by foft about 6 years ago
Been adding i2c to the zpu. Mostly working I think, a few timing issues to solve.
Updated by foft about 6 years ago
- Priority changed from Urgent to Normal
OK, confirmed this chip is working. I programmed it over i2c and am now getting two different clocks output on CLK0 and CLK2 - 10MHz and 30MHz as I set up in the clk generator software.
Going to mark this back as normal priority since I now know the chip is connected ok and working.
Updated by sadosp about 6 years ago
foft wrote:
OK, confirmed this chip is working. I programmed it over i2c and am now getting two different clocks output on CLK0 and CLK2 - 10MHz and 30MHz as I set up in the clk generator software.
Going to mark this back as normal priority since I now know the chip is connected ok and working.
Congrats! ;-)