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/*
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* Si5351A Rev B Configuration Register Export Header File
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*
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* This file represents a series of Silicon Labs Si5351A Rev B
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* register writes that can be performed to load a single configuration
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* on a device. It was created by a Silicon Labs ClockBuilder Pro
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* export tool.
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*
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* Part: Si5351A Rev B
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* Design ID:
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* Includes Pre/Post Download Control Register Writes: Yes
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* Created By: ClockBuilder Pro v2.21 [2018-01-19]
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* Timestamp: 2018-02-04 22:19:44 GMT+01:00
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*
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* A complete design report corresponding to this export is included at the end
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* of this header file.
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*
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*/
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#ifndef SI5351A_REVB_REG_CONFIG_HEADER
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#define SI5351A_REVB_REG_CONFIG_HEADER
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#define SI5351A_REVB_REG_CONFIG_NUM_REGS 55
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typedef struct
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{
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unsigned int address; /* 16-bit register address */
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unsigned char value; /* 8-bit register data */
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} si5351a_revb_register_t;
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si5351a_revb_register_t const si5351a_revb_registers[SI5351A_REVB_REG_CONFIG_NUM_REGS] =
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{
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{ 0x0002, 0x53 },
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{ 0x0003, 0x00 },
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{ 0x0007, 0x00 },
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{ 0x000F, 0x00 },
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{ 0x0010, 0x0D },
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{ 0x0011, 0x8C },
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{ 0x0012, 0x0D },
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{ 0x0013, 0x8C },
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{ 0x0014, 0x8C },
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{ 0x0015, 0x8C },
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{ 0x0016, 0x8C },
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{ 0x0017, 0x8C },
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{ 0x001A, 0x00 },
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{ 0x001B, 0x03 },
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{ 0x001C, 0x00 },
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{ 0x001D, 0x0E },
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{ 0x001E, 0xAA },
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{ 0x001F, 0x00 },
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{ 0x0020, 0x00 },
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{ 0x0021, 0x02 },
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{ 0x002A, 0x00 },
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{ 0x002B, 0x01 },
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{ 0x002C, 0x00 },
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{ 0x002D, 0x2B },
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{ 0x002E, 0x00 },
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{ 0x002F, 0x00 },
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{ 0x0030, 0x00 },
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{ 0x0031, 0x00 },
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{ 0x003A, 0x00 },
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{ 0x003B, 0x01 },
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{ 0x003C, 0x00 },
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{ 0x003D, 0x0D },
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{ 0x003E, 0x00 },
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{ 0x003F, 0x00 },
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{ 0x0040, 0x00 },
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{ 0x0041, 0x00 },
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{ 0x005A, 0x00 },
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{ 0x005B, 0x00 },
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{ 0x0095, 0x81 },
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{ 0x0096, 0x46 },
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{ 0x0097, 0x7F },
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{ 0x0098, 0xFF },
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{ 0x0099, 0x00 },
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{ 0x009A, 0x00 },
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{ 0x009B, 0xD6 },
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{ 0x009C, 0x00 },
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{ 0x009D, 0x00 },
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{ 0x009E, 0x00 },
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{ 0x009F, 0x01 },
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{ 0x00A0, 0x00 },
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{ 0x00A1, 0x00 },
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{ 0x00A2, 0x00 },
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{ 0x00A3, 0x00 },
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{ 0x00A4, 0x00 },
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{ 0x00B7, 0x92 },
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};
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/*
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* Design Report
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*
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* Overview
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* ========
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* Part: Si5351A
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* Project File: C:\Users\Mark\Documents\Si5351A-RevB-Project.slabtimeproj
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* Created By: ClockBuilder Pro v2.21 [2018-01-19]
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* Timestamp: 2018-02-04 22:19:44 GMT+01:00
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*
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* Design Rule Check
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* =================
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* Errors:
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* - No errors
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*
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* Warnings:
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* - No warnings
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*
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* Design
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* ======
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* Inputs:
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* IN0: 27 MHz
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*
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* Outputs:
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* OUT0: 10 MHz
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* Enabled LVCMOS 4 mA
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* Offset 0.000 s
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* OUT1: Unused
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* OUT2: 30 MHz
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* Enabled LVCMOS 4 mA
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* Offset 0.000 s
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*
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* Frequency Plan
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* ==============
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* PLL_A:
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* Enabled Features = SpreadSpectrum
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* Fvco = 900 MHz
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* M = 33.3333333333333333... [ 33 + 1/3 ]
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* Input0:
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* Source = Crystal
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* Source Frequency = 27 MHz
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* Fpfd = 27 MHz
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* Load Capacitance = Load_08pF
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* Output0:
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* Features = SpreadSpectrum
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* Disabled State = StopLow
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* R = 1 (2^0)
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* Fout = 10 MHz
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* N = 90
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* Output2:
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* Features = SpreadSpectrum
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* Disabled State = StopLow
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* R = 1 (2^0)
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* Fout = 30 MHz
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* N = 30
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*
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* Settings
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* ========
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*
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* Location Setting Name Decimal Value Hex Value
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* ------------ ------------- ----------------- -----------------
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* 0x0002[3] XO_LOS_MASK 0 0x0
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* 0x0002[4] CLK_LOS_MASK 1 0x1
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* 0x0002[5] LOL_A_MASK 0 0x0
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* 0x0002[6] LOL_B_MASK 1 0x1
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* 0x0002[7] SYS_INIT_MASK 0 0x0
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* 0x0003[7:0] CLK_OEB 0 0x00
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* 0x0007[7:4] I2C_ADDR_CTRL 0 0x0
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* 0x000F[2] PLLA_SRC 0 0x0
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* 0x000F[3] PLLB_SRC 0 0x0
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* 0x000F[4] PLLA_INSELB 0 0x0
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* 0x000F[5] PLLB_INSELB 0 0x0
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* 0x000F[7:6] CLKIN_DIV 0 0x0
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* 0x0010[1:0] CLK0_IDRV 1 0x1
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* 0x0010[3:2] CLK0_SRC 3 0x3
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* 0x0010[4] CLK0_INV 0 0x0
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* 0x0010[5] MS0_SRC 0 0x0
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* 0x0010[6] MS0_INT 0 0x0
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* 0x0010[7] CLK0_PDN 0 0x0
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* 0x0011[1:0] CLK1_IDRV 0 0x0
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* 0x0011[3:2] CLK1_SRC 3 0x3
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* 0x0011[4] CLK1_INV 0 0x0
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* 0x0011[5] MS1_SRC 0 0x0
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* 0x0011[6] MS1_INT 0 0x0
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* 0x0011[7] CLK1_PDN 1 0x1
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* 0x0012[1:0] CLK2_IDRV 1 0x1
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* 0x0012[3:2] CLK2_SRC 3 0x3
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* 0x0012[4] CLK2_INV 0 0x0
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* 0x0012[5] MS2_SRC 0 0x0
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* 0x0012[6] MS2_INT 0 0x0
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* 0x0012[7] CLK2_PDN 0 0x0
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* 0x0013[1:0] CLK3_IDRV 0 0x0
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* 0x0013[3:2] CLK3_SRC 3 0x3
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* 0x0013[4] CLK3_INV 0 0x0
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* 0x0013[5] MS3_SRC 0 0x0
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* 0x0013[6] MS3_INT 0 0x0
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* 0x0013[7] CLK3_PDN 1 0x1
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* 0x0014[1:0] CLK4_IDRV 0 0x0
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* 0x0014[3:2] CLK4_SRC 3 0x3
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* 0x0014[4] CLK4_INV 0 0x0
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* 0x0014[5] MS4_SRC 0 0x0
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* 0x0014[6] MS4_INT 0 0x0
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* 0x0014[7] CLK4_PDN 1 0x1
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* 0x0015[1:0] CLK5_IDRV 0 0x0
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* 0x0015[3:2] CLK5_SRC 3 0x3
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* 0x0015[4] CLK5_INV 0 0x0
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* 0x0015[5] MS5_SRC 0 0x0
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* 0x0015[6] MS5_INT 0 0x0
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* 0x0015[7] CLK5_PDN 1 0x1
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* 0x0016[1:0] CLK6_IDRV 0 0x0
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* 0x0016[3:2] CLK6_SRC 3 0x3
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* 0x0016[4] CLK6_INV 0 0x0
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* 0x0016[5] MS6_SRC 0 0x0
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* 0x0016[6] FBA_INT 0 0x0
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* 0x0016[7] CLK6_PDN 1 0x1
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* 0x0017[1:0] CLK7_IDRV 0 0x0
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* 0x0017[3:2] CLK7_SRC 3 0x3
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* 0x0017[4] CLK7_INV 0 0x0
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* 0x0017[5] MS7_SRC 0 0x0
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* 0x0017[6] FBB_INT 0 0x0
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* 0x0017[7] CLK7_PDN 1 0x1
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* 0x001C[17:0] MSNA_P1 3754 0x00EAA
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* 0x001F[19:0] MSNA_P2 2 0x00002
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* 0x001F[23:4] MSNA_P3 3 0x00003
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* 0x002C[17:0] MS0_P1 11008 0x02B00
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* 0x002F[19:0] MS0_P2 0 0x00000
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* 0x002F[23:4] MS0_P4 1 0x00001
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* 0x003C[17:0] MS2_P1 3328 0x00D00
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* 0x003F[19:0] MS2_P2 0 0x00000
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* 0x003F[23:4] MS2_P4 1 0x00001
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* 0x005A[7:0] MS6_P2 0 0x00
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* 0x005B[7:0] MS7_P2 0 0x00
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* 0x0095[14:0] SSDN_P2 326 0x0146
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* 0x0095[7] SSC_EN 1 0x1
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* 0x0097[14:0] SSDN_P3 32767 0x7FFF
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* 0x0097[7] SSC_MODE 0 0x0
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* 0x0099[11:0] SSDN_P1 0 0x000
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* 0x009A[15:4] SSUDP 214 0x0D6
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* 0x009C[14:0] SSUP_P2 0 0x0000
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* 0x009E[14:0] SSUP_P3 1 0x0001
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* 0x00A0[11:0] SSUP_P1 0 0x000
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* 0x00A2[21:0] VCXO_PARAM 0 0x000000
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* 0x00B7[7:6] XTAL_CL 2 0x2
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*
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*
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*/
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#endif
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