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--Copyright (C) 2016 Intel Corporation. All rights reserved.
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--Your use of Intel Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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|
--(including device programming or simulation files), and any
|
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--associated documentation or information are expressly subject
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|
--to the terms and conditions of the Intel Program License
|
|
--Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
--the Intel MegaCore Function License Agreement, or other
|
|
--applicable license agreement, including, without limitation,
|
|
--that your use is for the sole purpose of programming logic
|
|
--devices manufactured by Intel and sold by Intel or its
|
|
--authorized distributors. Please refer to the applicable
|
|
--agreement for further details.
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|
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component pll_fifo
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|
PORT
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|
(
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data : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
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rdclk : IN STD_LOGIC ;
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|
rdreq : IN STD_LOGIC ;
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|
wrclk : IN STD_LOGIC ;
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|
wrreq : IN STD_LOGIC ;
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|
q : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
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|
rdempty : OUT STD_LOGIC
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|
);
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|
end component;
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