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Revision 983

Added by markw over 5 years ago

Split inout into in and out for i2c, better for internal use in fpga

View differences:

eclaireXL_ITX/hdmi/scandoubler_hdmi.vhdl
O_TMDS_L : OUT STD_LOGIC_VECTOR(7 downto 0);
-- I2C params
scl : inout std_logic;
sda : inout std_logic
scl_in : in std_logic;
sda_in : in std_logic;
scl_wen : out std_logic;
sda_wen : out std_logic
);
END scandoubler_hdmi;
......
signal shift_b_next : std_logic_vector(9 downto 0) := "0000000000";
signal shift_clk_next : std_logic_vector(9 downto 0) := "0000000000";
-- i2c
signal multiscale_sda_wen : std_logic;
signal crtc_sda_wen : std_logic;
signal multiscale_scl_wen : std_logic;
signal crtc_scl_wen : std_logic;
BEGIN
--------------------------------------------------------
......
vsync => vsync_next,
blank => blank_next,
sda => sda,
scl => scl
scl_in => scl_in,
sda_in => sda_in,
scl_wen => multiscale_scl_wen,
sda_wen => multiscale_sda_wen
);
-- Resynchronization logic
......
video_id_code => crtc_video_id_code,
scaler_select => crtc_scaler_select,
sda => sda,
scl => scl
scl_in => scl_in,
sda_in => sda_in,
scl_wen => crtc_scl_wen,
sda_wen => crtc_sda_wen
);
hdmiav_inst : entity work.hdmi
......
O_TMDS_H <= shift_r_reg(0) & nshift_r_reg(0) & shift_g_reg(0) & nshift_g_reg(0) & shift_b_reg(0) & nshift_b_reg(0) & shift_clk_reg(0) & nshift_clk_reg(0);
O_TMDS_L <= shift_r_reg(1) & nshift_r_reg(1) & shift_g_reg(1) & nshift_g_reg(1) & shift_b_reg(1) & nshift_b_reg(1) & shift_clk_reg(1) & nshift_clk_reg(1);
-- I2C outputs
sda_wen <= multiscale_sda_wen or crtc_sda_wen;
scl_wen <= multiscale_scl_wen or crtc_scl_wen;
end vhdl;
eclaireXL_ITX/scaler/areascale.vhd
blank : out std_logic;
-- to set up params
sda : inout std_logic;
scl : inout std_logic
scl_in : in std_logic;
sda_in : in std_logic;
scl_wen : out std_logic;
sda_wen : out std_logic
);
END areascale;
......
bits => 11
)
port map (
scl => scl,
sda => sda,
scl_in => scl_in,
sda_in => sda_in,
scl_wen => scl_wen,
sda_wen => sda_wen,
clk => clock,
rst => not(reset_n),
eclaireXL_ITX/scaler/crtc.vhdl
scaler_select : out std_logic;
-- to set up params
sda : inout std_logic;
scl : inout std_logic
scl_in : in std_logic;
sda_in : in std_logic;
scl_wen : out std_logic;
sda_wen : out std_logic
);
END crtc;
......
bits => 12
)
port map (
scl => scl,
sda => sda,
scl_in => scl_in,
sda_in => sda_in,
scl_wen => scl_wen,
sda_wen => sda_wen,
clk => clk_pixel,
rst => not(reset_n),
eclaireXL_ITX/scaler/multiscale.vhd
blank : out std_logic;
-- to set up params
sda : inout std_logic;
scl : inout std_logic
scl_in : in std_logic;
sda_in : in std_logic;
scl_wen : out std_logic;
sda_wen : out std_logic
);
END multiscale;
......
vsync => poly_vsync_next,
blank => poly_blank_next,
sda => sda,
scl => scl
scl_in => scl_in,
sda_in => sda_in,
scl_wen => scl_wen,
sda_wen => sda_wen
);
end generate gen_polyphasic_on;
......
vsync => area_vsync_next,
blank => area_blank_next,
sda => sda,
scl => scl
scl_in => scl_in,
sda_in => sda_in,
scl_wen => scl_wen,
sda_wen => sda_wen
);
end generate gen_area_on;
eclaireXL_ITX/scaler/polyphasicscale.vhd
blank : out std_logic;
-- to set up params
sda : inout std_logic;
scl : inout std_logic
scl_in : in std_logic;
sda_in : in std_logic;
scl_wen : out std_logic;
sda_wen : out std_logic
);
END polyphasicscale;
......
bits => 11
)
port map (
scl => scl,
sda => sda,
scl_in => scl_in,
sda_in => sda_in,
scl_wen => scl_wen,
sda_wen => sda_wen,
clk => clock,
rst => not(reset_n),

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