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-------------------------------------------------------------------------------
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-- Title : DAC_DSM3 - sigma-delta DAC converter with double loop
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-- Project :
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-------------------------------------------------------------------------------
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-- File : dac_dsm2.vhd
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-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl )
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-- Company :
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-- Created : 2009-04-28
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-- Last update: 2012-10-16
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-- Platform :
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-- Standard : VHDL'93c
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-------------------------------------------------------------------------------
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-- Description: Implementation with use of variables inside of process
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-- : and with one rising and falling slope for each output cycle
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-------------------------------------------------------------------------------
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-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!!
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2009-04-28 1.0 wzab Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dac_dsm3v is
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generic (
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nbits : integer := 16);
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port (
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din : in signed((nbits-1) downto 0);
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dout : out std_logic;
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clk : in std_logic;
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clk_ena : in std_logic;
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n_rst : in std_logic);
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end dac_dsm3v;
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architecture beh1 of dac_dsm3v is
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signal del1, del2, d_q : signed(nbits+2 downto 0) := (others => '0');
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constant c1 : signed(nbits+2 downto 0) := to_signed(1, nbits+3);
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constant c_1 : signed(nbits+2 downto 0) := to_signed(-1, nbits+3);
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begin -- beh1
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process (clk, n_rst)
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variable v1, v2 : signed(nbits+2 downto 0) := (others => '0');
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begin -- process
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if n_rst = '0' then -- asynchronous reset (active low)
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del1 <= (others => '0');
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del2 <= (others => '0');
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dout <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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if clk_ena = '1' then
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v1 := din - d_q + del1;
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v2 := v1 - d_q + del2;
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if v2 > 0 then
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d_q <= shift_left(c1, nbits);
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dout <= '1';
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else
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d_q <= shift_left(c_1, nbits);
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dout <= '0';
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end if;
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del1 <= v1;
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del2 <= v2;
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end if;
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end if;
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end process;
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end beh1;
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