Revision 981
Added by markw over 5 years ago
| eclaireXL_ITX/atari800core_eclaireXLv1.sdc | ||
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create_clock -period 50MHz [get_ports CLOCK_50]
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create_clock -period 27MHz -name CLKGEN_CLK2
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create_clock -period 74.25MHz -name CLKGEN_CLK2 -add
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#create_clock -period 27MHz -name CLKGEN_CLK2
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#create_clock -period 74.25MHz -name CLKGEN_CLK2 -add
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derive_pll_clocks
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derive_clock_uncertainty
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create_generated_clock -source {CLKGEN_CLK2} -multiply_by 5 -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}
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create_generated_clock -source {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 5 -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
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create_generated_clock -source {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
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#create_generated_clock -source {CLKGEN_CLK2} -multiply_by 5 -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}
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create_clock -period 371.25MHz -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}
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create_generated_clock -source {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 5 -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
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create_generated_clock -source {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
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#group { CLKGEN_CLK2 } \
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set_clock_groups -asynchronous \
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-group { CLOCK_50 } \
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-group { CLKGEN_CLK2 } \
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-group { \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] \
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} \
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-group { \
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SDC file correction for v1