repo2/common/components/I2C_regs.vhd @ 980
| 980 | markw | ---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY I2C_regs IS
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generic (
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SLAVE_ADDR : std_logic_vector(6 downto 0);
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regs : integer := 1; -- up to 16
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bits : integer := 1
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);
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port (
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scl : inout std_logic;
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sda : inout std_logic;
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clk : in std_logic;
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rst : in std_logic;
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-- User interface
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reg : out std_logic_vector((regs*bits)-1 downto 0)
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);
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END I2C_regs;
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ARCHITECTURE vhdl OF I2C_regs IS
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signal i2c_write : std_logic;
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signal i2c_read : std_logic;
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signal i2c_write_data : std_logic_vector(7 downto 0);
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signal i2c_read_data : std_logic_vector(7 downto 0);
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signal i2c_addr_next : std_logic_vector(3 downto 0);
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signal i2c_addr_reg : std_logic_vector(3 downto 0);
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signal i2c_state_next : std_logic_vector(2 downto 0);
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signal i2c_state_reg : std_logic_vector(2 downto 0);
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constant I2C_INIT : std_logic_vector(2 downto 0) := "000";
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constant I2C_READ1 : std_logic_vector(2 downto 0) := "001";
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constant I2C_READ2 : std_logic_vector(2 downto 0) := "010";
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constant I2C_WRITE1 : std_logic_vector(2 downto 0) := "011";
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constant I2C_WRITE2 : std_logic_vector(2 downto 0) := "100";
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signal reg_next : std_logic_vector((regs*bits)-1 downto 0);
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signal reg_reg : std_logic_vector((regs*bits)-1 downto 0);
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function MIN(LEFT, RIGHT: INTEGER) return INTEGER is
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begin
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if LEFT < RIGHT then return LEFT;
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else return RIGHT;
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end if;
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end;
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function IX(r,c : natural) return natural is
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begin
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return (r*bits + c);
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end;
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BEGIN
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process(clk,rst)
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begin
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if (rst='1') then
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reg_reg <= (others=>'0');
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-- i2c
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i2c_state_reg <= I2C_INIT;
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i2c_addr_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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reg_reg <= reg_next;
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-- i2c
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i2c_state_reg <= i2c_state_next;
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i2c_addr_reg <= i2c_addr_next;
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end if;
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end process;
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i2cslave : entity work.I2C_slave
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generic map (
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SLAVE_ADDR => SLAVE_ADDR
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)
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port map (
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scl => scl,
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sda => sda,
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clk => clk,
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rst => rst,
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read_req => i2c_read,
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data_to_master => i2c_read_data,
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data_valid => i2c_write,
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data_from_master => i2c_write_data
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);
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process(
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reg_reg,
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i2c_addr_reg,
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i2c_state_reg,
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i2c_read,
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i2c_write,
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i2c_write_data
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)
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variable low_max : integer;
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variable i2c_addr_int : integer;
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begin
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low_max := min(7,bits-1);
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i2c_addr_int := to_integer(unsigned(i2c_addr_reg));
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reg_next <= reg_reg;
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i2c_addr_next <= i2c_addr_reg;
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i2c_state_next <= i2c_state_reg;
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i2c_read_data <= (others=>'0');
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case(i2c_state_reg) is
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when I2C_INIT =>
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if (i2c_write='1' and i2c_write_data(7 downto 5)="111") then -- F= write, E= read, bottom 4 bits = reg
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i2c_addr_next <= i2c_write_data(3 downto 0);
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if (i2c_write_data(4)='1') then
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i2c_state_next <= I2C_WRITE1;
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else
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i2c_state_next <= I2C_READ1;
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end if;
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end if;
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when I2C_WRITE1 =>
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if (i2c_write='1') then
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for i in 0 to regs-1 loop
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if (i2c_addr_int=i) then
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reg_next(IX(i,low_max) downto IX(i,0)) <= i2c_write_data(low_max downto 0);
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end if;
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end loop;
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i2c_state_next <= I2C_WRITE2;
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end if;
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when I2C_WRITE2 =>
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if (i2c_write='1') then
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for i in 0 to regs-1 loop
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if (i2c_addr_int=i) then
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reg_next(ix(i,bits-1) downto ix(i, 8)) <= i2c_write_data(bits-9 downto 0);
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end if;
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end loop;
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i2c_state_next <= I2C_INIT;
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end if;
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when I2C_READ1 =>
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for i in 0 to regs-1 loop
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if (i2c_addr_int=i) then
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i2c_read_data(low_max downto 0) <= reg_reg(ix(i,low_max) downto ix(i,0));
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end if;
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end loop;
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if (i2c_read='1') then
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i2c_state_next <= I2C_READ2;
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end if;
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when I2C_READ2 =>
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for i in 0 to regs-1 loop
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if (i2c_addr_int=i) then
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i2c_read_data(bits-9 downto 0) <= reg_reg(ix(i,bits-1) downto ix(i,8));
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end if;
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end loop;
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if (i2c_read='1') then
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i2c_state_next <= I2C_INIT;
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end if;
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when others =>
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i2c_state_next <= I2C_INIT;
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end case;
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end process;
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reg <= reg_reg;
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end vhdl;
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