Revision 979
Added by markw over 5 years ago
| eclaireXL_ITX/atari800core_eclaireXLv1.qsf | ||
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#set_global_assignment -name QIP_FILE serial_loader/synthesis/serial_loader.qip
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set_global_assignment -name QIP_FILE zpu_rom.qip
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set_global_assignment -name QIP_FILE pll_hdmi.qip
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set_global_assignment -name QIP_FILE pll_hdmi2.qip
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set_global_assignment -name QIP_FILE pll_acore.qip
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set_global_assignment -name QIP_FILE pll_acore_reconfig.qip
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set_global_assignment -name QIP_FILE pll_usb.qip
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| ... | ... | |
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set_global_assignment -name QIP_FILE fifo_transmit.qip
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set_global_assignment -name QIP_FILE sfl.qip
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set_global_assignment -name QSYS_FILE clkctrl.qsys
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set_global_assignment -name QSYS_FILE clkctrl2.qsys
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set_global_assignment -name QSYS_FILE ddioclkctrl.qsys
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set_location_assignment PIN_H16 -to CLOCK_50
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| ... | ... | |
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[14]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[15]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[0]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_R[0]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_R[0]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[0]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_G[0]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_G[0]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[0]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_B[0]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_B[0]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[1]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_R[1]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_R[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[1]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_G[1]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_G[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[1]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_B[1]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_B[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[2]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_R[2]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_R[2]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[2]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_G[2]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_G[2]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[2]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_B[2]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_B[2]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[3]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_R[3]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_R[3]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[3]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_G[3]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_G[3]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[3]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_B[3]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_B[3]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[4]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_R[4]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_R[4]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[4]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_G[4]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_G[4]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[4]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_B[4]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_B[4]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[5]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_R[5]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_R[5]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[5]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_G[5]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_G[5]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[5]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_B[5]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_B[5]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[6]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_R[6]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_R[6]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[6]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_G[6]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_G[6]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[6]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_B[6]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_B[6]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[7]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_R[7]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_R[7]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[7]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_G[7]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_G[7]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[7]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to VGA_B[7]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to VGA_B[7]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_DAT2
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_DAT1
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| eclaireXL_ITX/atari800core_eclaireXLv1.sdc | ||
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create_clock -period 50MHz [get_ports CLOCK_50]
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create_clock -period 27MHz -name CLKGEN_CLK2
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create_clock -period 74.25MHz -name CLKGEN_CLK2 -add
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derive_pll_clocks
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derive_clock_uncertainty
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create_generated_clock -source {CLKGEN_CLK2} -multiply_by 5 -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}
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create_generated_clock -source {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 5 -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
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create_generated_clock -source {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
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set_clock_groups -asynchronous \
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-group { CLOCK_50 } \
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-group { CLKGEN_CLK2 } \
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-group { \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] \
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pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] \
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} \
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-group { \
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pll_hdmi_inst|pll_hdmi_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \
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pll_hdmi_inst|pll_hdmi_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \
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pll_hdmi_inst|pll_hdmi_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \
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pll_hdmi_inst|pll_hdmi_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
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} \
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-group { \
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pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \
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pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \
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pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \
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} \
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-group { \
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pllusbinstance|pll_usb_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \
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pllusbinstance|pll_usb_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \
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pllusbinstance|pll_usb_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \
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}
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#create_generated_clock -name sdram_clk -source pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk
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#set_output_delay -clock sdram_clk -max 6.0 [get_ports DRAM_DQ[*]]
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#set_output_delay -clock sdram_clk -min -1.0 [get_ports DRAM_DQ[*]]
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| eclaireXL_ITX/atari800core_eclaireXLv1.vhd | ||
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-- For initial port may help to have no
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internal_rom : integer := 1; -- if 0 expects it in sdram,is 1:16k os+basic, is 2:... TODO
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internal_ram : integer := 16384; -- at start of memory map
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sid : integer := 0
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sid : integer := 0;
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enable_area_scaler : integer := 1;
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enable_polyphasic_scaler : integer := 0
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);
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PORT
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(
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| ... | ... | |
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);
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end component;
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component pll_hdmi
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component pll_hdmi is
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port (
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refclk : in std_logic := '0'; -- refclk.clk
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rst : in std_logic := '0'; -- reset.reset
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outclk_0 : out std_logic; -- outclk0.clk
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locked : out std_logic -- locked.export
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);
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end component;
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component pll_hdmi2
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port (
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refclk : in std_logic := '0'; -- refclk.clk
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rst : in std_logic := '0'; -- reset.reset
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| ... | ... | |
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);
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end component;
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component ddioclkctrl is
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port (
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inclk3x : in std_logic := '0'; -- altclkctrl_input.inclk3x
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inclk2x : in std_logic := '0'; -- .inclk2x
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inclk1x : in std_logic := '0'; -- .inclk1x
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inclk0x : in std_logic := '0'; -- .inclk0x
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clkselect : in std_logic_vector(1 downto 0) := (others => '0'); -- .clkselect
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ena : in std_logic := '0'; -- .ena
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outclk : out std_logic -- altclkctrl_output.outclk
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);
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end component;
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component clkctrl is
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port (
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inclk : in std_logic := '0'; -- altclkctrl_input.inclk
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| ... | ... | |
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);
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end component;
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component ddioclkctrl is
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port (
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inclk3x : in std_logic := '0'; -- altclkctrl_input.inclk3x
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inclk2x : in std_logic := '0'; -- .inclk2x
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inclk1x : in std_logic := '0'; -- .inclk1x
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inclk0x : in std_logic := '0'; -- .inclk0x
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clkselect : in std_logic_vector(1 downto 0) := (others => '0'); -- .clkselect
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ena : in std_logic := '0'; -- .ena
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outclk : out std_logic -- altclkctrl_output.outclk
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);
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component clkctrl2 is
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port (
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inclk3x : in std_logic := 'X'; -- inclk3x
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inclk2x : in std_logic := 'X'; -- inclk2x
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inclk1x : in std_logic := 'X'; -- inclk1x
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inclk0x : in std_logic := 'X'; -- inclk0x
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clkselect : in std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
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outclk : out std_logic -- outclk
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);
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end component;
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component pll_usb is
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| ... | ... | |
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-- SYSTEM
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SIGNAL GCLOCK_50 : STD_LOGIC; -- Only 2 fplls can use the pin!
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SIGNAL GCLOCK_54 : STD_LOGIC; -- Only 2 fplls can use the pin!
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SIGNAL GCLOCK_148_5 : STD_LOGIC; -- Only 2 fplls can use the pin!
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SIGNAL CLK : STD_LOGIC;
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SIGNAL CLK_1x : STD_LOGIC;
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SIGNAL CLK_114 : STD_LOGIC;
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| ... | ... | |
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SIGNAL CLK_PIXEL_IN : STD_LOGIC;
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SIGNAL CLK_HDMI_IN : STD_LOGIC;
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signal CLK_PIXEL_SWITCH : STD_LOGIC;
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--SIGNAL CLK_7425_PIXEL_IN : STD_LOGIC;
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--SIGNAL CLK_7425_HDMI_IN : STD_LOGIC;
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--SIGNAL CLK_27_PIXEL_IN : STD_LOGIC;
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--SIGNAL CLK_27_HDMI_IN : STD_LOGIC;
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signal clk_hdmi_select : std_logic_vector(2 downto 0);
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SIGNAL CLK_raw : STD_LOGIC;
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SIGNAL CLK_1x_raw : STD_LOGIC;
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| ... | ... | |
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signal pll_acore_locked : std_logic;
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signal pll_hdmi_locked : std_logic;
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signal pll_hdmi1_locked : std_logic;
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signal pll_hdmi2_locked : std_logic;
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signal pll_pause_counter_reg : std_logic_vector(25 downto 0);
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signal pll_pause_counter_next : std_logic_vector(25 downto 0);
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| ... | ... | |
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signal spi_do : std_logic;
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signal spi_clk : std_logic;
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-- scaler
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signal scaler_sda : std_logic;
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signal scaler_scl : std_logic;
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function to_std_logic(i : in integer) return std_logic is
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begin
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if i = 0 then
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| ... | ... | |
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outclk => CLK_114
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);
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clkctrl2: clkctrl
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clkctrl2i: clkctrl
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port map (
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inclk => DRAM_CLK_raw,
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ena => pll_enable_reg,
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| ... | ... | |
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);
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pll_hdmi_inst : pll_hdmi
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PORT MAP(refclk => GCLOCK_50,
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outclk_0 => CLK_PIXEL_IN, -- 27MHz
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outclk_1 => CLK_HDMI_IN, -- 5*27MHz
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locked => PLL_HDMI_LOCKED);
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PORT MAP(refclk => GCLOCK_54,
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outclk_0 => GCLOCK_148_5,
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locked => open);
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u0 : clkctrl2
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port map (
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inclk3x => GCLOCK_54, -- altclkctrl_input.inclk3x
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inclk2x => GCLOCK_148_5, -- .inclk2x
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-- inclk1x => CLOCK_50, -- .inclk1x < builds/works
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-- inclk0x => CLOCK_50, -- .inclk0x
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-- inclk1x => CLKGEN_CLK2, -- .inclk1x < fails to build
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-- inclk0x => CLKGEN_CLK0, -- .inclk0x
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inclk1x => CLOCK_50, -- .inclk1x
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inclk0x => CLOCK_50, -- .inclk0x
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clkselect => clk_hdmi_select(1 downto 0), -- .clkselect
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outclk => CLK_PIXEL_SWITCH -- altclkctrl_output.outclk
|
||
|
);
|
||
|
|
||
|
--CLK_HDMI_IN <= CLK_PIXEL_IN;
|
||
|
|
||
|
|
||
|
|
||
|
pll_hdmi2_inst : pll_hdmi2
|
||
|
PORT MAP(refclk => CLK_PIXEL_SWITCH,
|
||
|
locked => PLL_HDMI_LOCKED,
|
||
|
outclk_0 => CLK_PIXEL_IN,
|
||
|
outclk_1 => CLK_HDMI_IN);
|
||
|
|
||
|
--PLL_HDMI_LOCKED <= PLL_HDMI1_LOCKED and PLL_HDMI2_LOCKED;
|
||
|
|
||
|
--CLK_PIXEL_IN <= CLK_7425_PIXEL_IN;
|
||
|
--CLK_HDMI_IN <= CLK_7425_HDMI_IN;
|
||
|
|
||
|
--clkctrl2_1: clkctrl2
|
||
|
--port map (
|
||
|
-- inclk0x => CLOCK_50,
|
||
|
-- inclk1x => '0',
|
||
|
-- => CLK_7425_PIXEL_IN,
|
||
|
-- inclk3x => CLK_27_PIXEL_IN,
|
||
|
-- clkselect => '1'&clk_hdmi_select,
|
||
|
-- ena => '1',
|
||
|
-- outclk => CLK_PIXEL_IN
|
||
|
--);
|
||
|
--
|
||
|
--clkctrl2_2: clkctrl2
|
||
|
--port map (
|
||
|
-- inclk0x => CLOCK_50,
|
||
|
-- inclk1x => '0',
|
||
|
-- inclk2x => ,
|
||
|
-- inclk3x => CLK_27_HDMI_IN,
|
||
|
-- clkselect => '1'&clk_hdmi_select,
|
||
|
-- ena => '1',
|
||
|
-- outclk => CLK_HDMI_IN
|
||
|
--);
|
||
|
--
|
||
|
--end generate;
|
||
|
|
||
|
|
||
| ... | ... | |
|
pllusbinstance : pll_usb
|
||
|
PORT MAP(refclk => CLOCK_50,
|
||
|
outclk_0 => CLK_USB,
|
||
|
outclk_1 => GCLOCK_50,
|
||
|
outclk_1 => GCLOCK_54,
|
||
|
locked => open);
|
||
|
|
||
|
|
||
| ... | ... | |
|
CLK => CLK,
|
||
|
RESET_N => RESET_N and sdram_reset_n,
|
||
|
|
||
|
-- dma bus master (with many waitstates...)
|
||
|
-- dma bus master (with manclk_hdmi_selecty waitstates...)
|
||
|
ZPU_ADDR_FETCH => dma_addr_fetch,
|
||
|
ZPU_DATA_OUT => dma_write_data,
|
||
|
ZPU_FETCH => dma_fetch,
|
||
| ... | ... | |
|
USBWireVMin => USBWireVMin,
|
||
|
USBWireVPout => USBWireVPout,
|
||
|
USBWireVMout => USBWireVMout,
|
||
|
USBWireOE_n => USBWireOE_n
|
||
|
USBWireOE_n => USBWireOE_n,
|
||
|
|
||
|
i2c0_sda => scaler_sda,
|
||
|
i2c0_scl => scaler_scl
|
||
|
);
|
||
|
|
||
|
pause_atari <= zpu_out1(0);
|
||
| ... | ... | |
|
|
||
|
-- HDMI
|
||
|
scandoubler_hdmi_int : work.scandoubler_hdmi
|
||
|
GENERIC MAP
|
||
|
(
|
||
|
enable_area_scaler => enable_area_scaler,
|
||
|
enable_polyphasic_scaler => enable_polyphasic_scaler
|
||
|
)
|
||
|
PORT MAP
|
||
|
(
|
||
|
CLK_ATARI_IN => CLK,
|
||
| ... | ... | |
|
--HDMI clock domain
|
||
|
CLK_HDMI_IN => clk_hdmi_in,
|
||
|
CLK_PIXEL_IN => clk_pixel_in,
|
||
|
CLK_HDMI_SELECT => clk_hdmi_select,
|
||
|
|
||
|
O_hsync => adj_hsync,
|
||
|
O_vsync => adj_vsync,
|
||
| ... | ... | |
|
|
||
|
-- TO TV...
|
||
|
O_TMDS_H => tmds_h,
|
||
|
O_TMDS_L => tmds_l
|
||
|
O_TMDS_L => tmds_l,
|
||
|
|
||
|
-- I2C
|
||
|
sda => scaler_sda,
|
||
|
scl => scaler_scl
|
||
|
);
|
||
|
|
||
|
END vhdl;
|
||
| eclaireXL_ITX/atari800core_eclaireXLv3.qpf | ||
|---|---|---|
|
# -------------------------------------------------------------------------- #
|
||
|
#
|
||
|
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
|
||
|
# Your use of Altera Corporation's design tools, logic functions
|
||
|
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||
|
# Your use of Intel Corporation's design tools, logic functions
|
||
|
# and other software and tools, and its AMPP partner logic
|
||
|
# functions, and any output files from any of the foregoing
|
||
|
# (including device programming or simulation files), and any
|
||
|
# associated documentation or information are expressly subject
|
||
|
# to the terms and conditions of the Altera Program License
|
||
|
# Subscription Agreement, the Altera Quartus II License Agreement,
|
||
|
# the Altera MegaCore Function License Agreement, or other
|
||
|
# applicable license agreement, including, without limitation,
|
||
|
# that your use is for the sole purpose of programming logic
|
||
|
# devices manufactured by Altera and sold by Altera or its
|
||
|
# authorized distributors. Please refer to the applicable
|
||
|
# agreement for further details.
|
||
|
# to the terms and conditions of the Intel Program License
|
||
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||
|
# agreement, including, without limitation, that your use is for
|
||
|
# the sole purpose of programming logic devices manufactured by
|
||
|
# Intel and sold by Intel or its authorized distributors. Please
|
||
|
# refer to the applicable agreement for further details.
|
||
|
#
|
||
|
# -------------------------------------------------------------------------- #
|
||
|
#
|
||
|
# Quartus II 64-Bit
|
||
|
# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
|
||
|
# Date created = 20:32:21 July 11, 2015
|
||
|
# Quartus Prime
|
||
|
# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
|
||
|
# Date created = 20:42:21 November 12, 2019
|
||
|
#
|
||
|
# -------------------------------------------------------------------------- #
|
||
|
|
||
|
QUARTUS_VERSION = "14.0"
|
||
|
DATE = "20:32:21 July 11, 2015"
|
||
|
QUARTUS_VERSION = "18.0"
|
||
|
DATE = "20:42:21 November 12, 2019"
|
||
|
|
||
|
# Revisions
|
||
|
|
||
|
PROJECT_REVISION = "atari800core_eclaireXLv3"
|
||
|
PROJECT_REVISION = "atari800core_eclaireXL"
|
||
| eclaireXL_ITX/atari800core_eclaireXLv3.qsf | ||
|---|---|---|
|
set_global_assignment -name TOP_LEVEL_ENTITY atari800core_eclaireXL
|
||
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
|
||
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:21 JULY 11, 2015"
|
||
|
set_global_assignment -name LAST_QUARTUS_VERSION 14.0
|
||
|
set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
|
||
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||
| ... | ... | |
|
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1"
|
||
|
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
|
||
|
|
||
|
set_global_assignment -name QIP_FILE pll_usb.qip
|
||
|
#set_global_assignment -name QIP_FILE serial_loader/synthesis/serial_loader.qip
|
||
|
set_global_assignment -name QIP_FILE zpu_rom.qip
|
||
|
set_global_assignment -name QIP_FILE pll_hdmi.qip
|
||
|
set_global_assignment -name QIP_FILE pll_hdmi2.qip
|
||
|
set_global_assignment -name QIP_FILE pll_acore.qip
|
||
|
set_global_assignment -name QIP_FILE pll_acore_reconfig.qip
|
||
|
set_global_assignment -name QIP_FILE pll_usb.qip
|
||
| ... | ... | |
|
set_global_assignment -name QIP_FILE fifo_transmit.qip
|
||
|
set_global_assignment -name QIP_FILE sfl.qip
|
||
|
set_global_assignment -name QSYS_FILE clkctrl.qsys
|
||
|
set_global_assignment -name QSYS_FILE clkctrl2.qsys
|
||
|
set_global_assignment -name VHDL_FILE adc084.vhdl
|
||
|
set_global_assignment -name VHDL_FILE gpio_debug.vhd
|
||
|
|
||
| ... | ... | |
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[14]
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[15]
|
||
|
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX2P
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX2P
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX2P
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX1P
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX1P
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX1P
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX0P
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX0P
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX0P
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_CLKP
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_CLKP
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_CLKP
|
||
|
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX2N
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX2N
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX2N
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX1N
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX1N
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX1N
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX0N
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX0N
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX0N
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_CLKN
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_CLKN
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_CLKN
|
||
|
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX2P
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX2P
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX2P
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX1P
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX1P
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX1P
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX0P
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX0P
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX0P
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_CLKP
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_CLKP
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_CLKP
|
||
|
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX2N
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX2N
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX2N
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX1N
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX1N
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX1N
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_TX0N
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_TX0N
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_TX0N
|
||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HD_CLKN
|
||
|
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HD_CLKN
|
||
|
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to HD_CLKN
|
||
|
|
||
|
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_DAT2
|
||
|
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_DAT1
|
||
|
|
||
|
|
||
|
|
||
|
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
|
||
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||
| eclaireXL_ITX/atari800core_eclaireXLv3.sdc | ||
|---|---|---|
|
create_clock -period 50MHz [get_ports CLOCK_50]
|
||
|
create_clock -period 27MHz -name CLKGEN_CLK2
|
||
|
create_clock -period 74.25MHz -name CLKGEN_CLK2 -add
|
||
|
derive_pll_clocks
|
||
|
derive_clock_uncertainty
|
||
|
|
||
|
create_generated_clock -source {CLKGEN_CLK2} -multiply_by 5 -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}
|
||
|
create_generated_clock -source {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 5 -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
|
||
|
create_generated_clock -source {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -duty_cycle 50.00 -name {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} {pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
|
||
|
|
||
|
set_clock_groups -asynchronous \
|
||
|
-group { CLOCK_50 } \
|
||
|
-group { CLKGEN_CLK2 } \
|
||
|
-group { \
|
||
|
pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk \
|
||
|
pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk \
|
||
|
pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk \
|
||
|
pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk \
|
||
|
pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] \
|
||
|
pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] \
|
||
|
} \
|
||
|
-group { \
|
||
|
pll_hdmi_inst|pll_hdmi_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \
|
||
|
pll_hdmi_inst|pll_hdmi_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \
|
||
|
pll_hdmi_inst|pll_hdmi_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \
|
||
|
pll_hdmi_inst|pll_hdmi_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
|
||
|
} \
|
||
|
-group { \
|
||
|
pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \
|
||
|
pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \
|
||
|
pll_hdmi2_inst|pll_hdmi2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \
|
||
|
} \
|
||
|
-group { \
|
||
|
pllusbinstance|pll_usb_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \
|
||
|
pllusbinstance|pll_usb_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \
|
||
|
pllusbinstance|pll_usb_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \
|
||
|
}
|
||
|
|
||
|
|
||
|
|
||
|
#create_generated_clock -name sdram_clk -source pll_acore_inst|pll_acore_inst|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk
|
||
|
#set_output_delay -clock sdram_clk -max 6.0 [get_ports DRAM_DQ[*]]
|
||
|
#set_output_delay -clock sdram_clk -min -1.0 [get_ports DRAM_DQ[*]]
|
||
| eclaireXL_ITX/atari800core_eclaireXLv3.vhd | ||
|---|---|---|
|
-- For initial port may help to have no
|
||
|
internal_rom : integer := 1; -- if 0 expects it in sdram,is 1:16k os+basic, is 2:... TODO
|
||
|
internal_ram : integer := 16384; -- at start of memory map
|
||
|
sid : integer := 0
|
||
|
sid : integer := 0;
|
||
|
enable_area_scaler : integer := 1;
|
||
|
enable_polyphasic_scaler : integer := 0
|
||
|
);
|
||
|
PORT
|
||
|
(
|
||
| ... | ... | |
|
);
|
||
|
end component;
|
||
|
|
||
|
component pll_hdmi
|
||
|
component pll_hdmi is
|
||
|
port (
|
||
|
refclk : in std_logic := '0'; -- refclk.clk
|
||
|
rst : in std_logic := '0'; -- reset.reset
|
||
|
outclk_0 : out std_logic; -- outclk0.clk
|
||
|
locked : out std_logic -- locked.export
|
||
|
);
|
||
|
end component;
|
||
|
|
||
|
|
||
|
component pll_hdmi2
|
||
|
port (
|
||
|
refclk : in std_logic := '0'; -- refclk.clk
|
||
|
rst : in std_logic := '0'; -- reset.reset
|
||
| ... | ... | |
|
);
|
||
|
end component;
|
||
|
|
||
|
component ddioclkctrl is
|
||
|
port (
|
||
|
inclk3x : in std_logic := '0'; -- altclkctrl_input.inclk3x
|
||
|
inclk2x : in std_logic := '0'; -- .inclk2x
|
||
|
inclk1x : in std_logic := '0'; -- .inclk1x
|
||
|
inclk0x : in std_logic := '0'; -- .inclk0x
|
||
|
clkselect : in std_logic_vector(1 downto 0) := (others => '0'); -- .clkselect
|
||
|
ena : in std_logic := '0'; -- .ena
|
||
|
outclk : out std_logic -- altclkctrl_output.outclk
|
||
|
);
|
||
|
component clkctrl2 is
|
||
|
port (
|
||
|
inclk3x : in std_logic := 'X'; -- inclk3x
|
||
|
inclk2x : in std_logic := 'X'; -- inclk2x
|
||
|
inclk1x : in std_logic := 'X'; -- inclk1x
|
||
|
inclk0x : in std_logic := 'X'; -- inclk0x
|
||
|
clkselect : in std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
|
||
|
outclk : out std_logic -- outclk
|
||
|
);
|
||
|
end component;
|
||
|
|
||
|
component pll_usb is
|
||
| ... | ... | |
|
|
||
|
|
||
|
-- SYSTEM
|
||
|
SIGNAL GCLOCK_50 : STD_LOGIC; -- Only 2 fplls can use the pin!
|
||
|
SIGNAL GCLOCK_54 : STD_LOGIC; -- Only 2 fplls can use the pin!
|
||
|
SIGNAL GCLOCK_148_5 : STD_LOGIC; -- Only 2 fplls can use the pin!
|
||
|
SIGNAL CLK : STD_LOGIC;
|
||
|
SIGNAL CLK_1x : STD_LOGIC;
|
||
|
SIGNAL CLK_114 : STD_LOGIC;
|
||
| ... | ... | |
|
|
||
|
SIGNAL CLK_PIXEL_IN : STD_LOGIC;
|
||
|
SIGNAL CLK_HDMI_IN : STD_LOGIC;
|
||
|
|
||
|
signal CLK_PIXEL_SWITCH : STD_LOGIC;
|
||
|
--SIGNAL CLK_7425_PIXEL_IN : STD_LOGIC;
|
||
|
--SIGNAL CLK_7425_HDMI_IN : STD_LOGIC;
|
||
|
--SIGNAL CLK_27_PIXEL_IN : STD_LOGIC;
|
||
|
--SIGNAL CLK_27_HDMI_IN : STD_LOGIC;
|
||
|
signal clk_hdmi_select : std_logic_vector(2 downto 0);
|
||
|
|
||
|
SIGNAL CLK_raw : STD_LOGIC;
|
||
|
SIGNAL CLK_1x_raw : STD_LOGIC;
|
||
| ... | ... | |
|
signal pll_acore_locked : std_logic;
|
||
|
|
||
|
signal pll_hdmi_locked : std_logic;
|
||
|
signal pll_hdmi1_locked : std_logic;
|
||
|
signal pll_hdmi2_locked : std_logic;
|
||
|
|
||
|
signal pll_pause_counter_reg : std_logic_vector(25 downto 0);
|
||
|
signal pll_pause_counter_next : std_logic_vector(25 downto 0);
|
||
| ... | ... | |
|
signal spi_do : std_logic;
|
||
|
signal spi_clk : std_logic;
|
||
|
|
||
|
-- scaler
|
||
|
signal scaler_sda : std_logic;
|
||
|
signal scaler_scl : std_logic;
|
||
|
|
||
|
function to_std_logic(i : in integer) return std_logic is
|
||
|
begin
|
||
|
if i = 0 then
|
||
| ... | ... | |
|
outclk => CLK_114
|
||
|
);
|
||
|
|
||
|
clkctrl2: clkctrl
|
||
|
clkctrl2i: clkctrl
|
||
|
port map (
|
||
|
inclk => DRAM_CLK_raw,
|
||
|
ena => pll_enable_reg,
|
||
| ... | ... | |
|
);
|
||
|
|
||
|
pll_hdmi_inst : pll_hdmi
|
||
|
PORT MAP(refclk => GCLOCK_50,
|
||
|
outclk_0 => CLK_PIXEL_IN, -- 27MHz
|
||
|
outclk_1 => CLK_HDMI_IN, -- 5*27MHz
|
||
|
locked => PLL_HDMI_LOCKED);
|
||
|
PORT MAP(refclk => GCLOCK_54,
|
||
|
outclk_0 => GCLOCK_148_5,
|
||
|
locked => open);
|
||
|
|
||
|
|
||
|
|
||
|
u0 : clkctrl2
|
||
|
port map (
|
||
|
inclk3x => GCLOCK_54, -- altclkctrl_input.inclk3x
|
||
|
inclk2x => GCLOCK_148_5, -- .inclk2x
|
||
|
-- inclk1x => CLOCK_50, -- .inclk1x < builds/works
|
||
|
-- inclk0x => CLOCK_50, -- .inclk0x
|
||
|
-- inclk1x => CLKGEN_CLK2, -- .inclk1x < fails to build
|
||
|
-- inclk0x => CLKGEN_CLK0, -- .inclk0x
|
||
|
inclk1x => CLOCK_50, -- .inclk1x
|
||
|
inclk0x => CLOCK_50, -- .inclk0x
|
||
|
clkselect => clk_hdmi_select(1 downto 0), -- .clkselect
|
||
|
outclk => CLK_PIXEL_SWITCH -- altclkctrl_output.outclk
|
||
|
);
|
||
|
|
||
|
--CLK_HDMI_IN <= CLK_PIXEL_IN;
|
||
|
|
||
|
|
||
|
|
||
|
pll_hdmi2_inst : pll_hdmi2
|
||
|
PORT MAP(refclk => CLK_PIXEL_SWITCH,
|
||
|
locked => PLL_HDMI_LOCKED,
|
||
|
outclk_0 => CLK_PIXEL_IN,
|
||
|
outclk_1 => CLK_HDMI_IN);
|
||
|
|
||
|
--PLL_HDMI_LOCKED <= PLL_HDMI1_LOCKED and PLL_HDMI2_LOCKED;
|
||
|
|
||
|
--CLK_PIXEL_IN <= CLK_7425_PIXEL_IN;
|
||
|
--CLK_HDMI_IN <= CLK_7425_HDMI_IN;
|
||
|
|
||
|
--clkctrl2_1: clkctrl2
|
||
|
--port map (
|
||
|
-- inclk0x => CLOCK_50,
|
||
|
-- inclk1x => '0',
|
||
|
-- => CLK_7425_PIXEL_IN,
|
||
|
-- inclk3x => CLK_27_PIXEL_IN,
|
||
|
-- clkselect => '1'&clk_hdmi_select,
|
||
|
-- ena => '1',
|
||
|
-- outclk => CLK_PIXEL_IN
|
||
|
--);
|
||
|
--
|
||
|
--clkctrl2_2: clkctrl2
|
||
|
--port map (
|
||
|
-- inclk0x => CLOCK_50,
|
||
|
-- inclk1x => '0',
|
||
|
-- inclk2x => ,
|
||
|
-- inclk3x => CLK_27_HDMI_IN,
|
||
|
-- clkselect => '1'&clk_hdmi_select,
|
||
|
-- ena => '1',
|
||
|
-- outclk => CLK_HDMI_IN
|
||
|
--);
|
||
|
--
|
||
|
--end generate;
|
||
|
|
||
|
|
||
| ... | ... | |
|
pllusbinstance : pll_usb
|
||
|
PORT MAP(refclk => CLOCK_50,
|
||
|
outclk_0 => CLK_USB,
|
||
|
outclk_1 => GCLOCK_50,
|
||
|
outclk_1 => GCLOCK_54,
|
||
|
locked => open);
|
||
|
|
||
|
|
||
| ... | ... | |
|
CLK => CLK,
|
||
|
RESET_N => RESET_N and sdram_reset_n,
|
||
|
|
||
|
-- dma bus master (with many waitstates...)
|
||
|
-- dma bus master (with manclk_hdmi_selecty waitstates...)
|
||
|
ZPU_ADDR_FETCH => dma_addr_fetch,
|
||
|
ZPU_DATA_OUT => dma_write_data,
|
||
|
ZPU_FETCH => dma_fetch,
|
||
| ... | ... | |
|
USBWireVMin => USBWireVMin,
|
||
|
USBWireVPout => USBWireVPout,
|
||
|
USBWireVMout => USBWireVMout,
|
||
|
USBWireOE_n => USBWireOE_n
|
||
|
USBWireOE_n => USBWireOE_n,
|
||
|
|
||
|
i2c0_sda => scaler_sda,
|
||
|
i2c0_scl => scaler_scl
|
||
|
);
|
||
|
|
||
|
pause_atari <= zpu_out1(0);
|
||
| ... | ... | |
|
|
||
|
-- HDMI
|
||
|
scandoubler_hdmi_int : work.scandoubler_hdmi
|
||
|
GENERIC MAP
|
||
|
(
|
||
|
enable_area_scaler => enable_area_scaler,
|
||
|
enable_polyphasic_scaler => enable_polyphasic_scaler
|
||
|
)
|
||
|
PORT MAP
|
||
|
(
|
||
|
CLK_ATARI_IN => CLK,
|
||
| ... | ... | |
|
--HDMI clock domain
|
||
|
CLK_HDMI_IN => clk_hdmi_in,
|
||
|
CLK_PIXEL_IN => clk_pixel_in,
|
||
|
CLK_HDMI_SELECT => clk_hdmi_select,
|
||
|
|
||
|
O_hsync => adj_hsync,
|
||
|
O_vsync => adj_vsync,
|
||
| ... | ... | |
|
|
||
|
-- TO TV...
|
||
|
O_TMDS_H => tmds_h,
|
||
|
O_TMDS_L => tmds_l
|
||
|
O_TMDS_L => tmds_l,
|
||
|
|
||
|
-- I2C
|
||
|
sda => scaler_sda,
|
||
|
scl => scaler_scl
|
||
|
);
|
||
|
|
||
|
END vhdl;
|
||
| eclaireXL_ITX/build.sh | ||
|---|---|---|
|
(
|
||
|
"A2EBAv3rom" =>
|
||
|
{
|
||
|
"internal_ram" => 32768,
|
||
|
"internal_ram" => 65536,
|
||
|
"internal_rom" => 1,
|
||
|
"fpga" => "5CEBA2F23C8",
|
||
|
"postfix" => "v3",
|
||
|
"convert" => "v3a",
|
||
|
"sid" => 1
|
||
|
"sid" => 0,
|
||
|
"enable_polyphasic_scaler" => 0,
|
||
|
"enable_area_scaler" => 1
|
||
|
},
|
||
|
"A4EBAv3rom" =>
|
||
|
{
|
||
| ... | ... | |
|
"fpga" => "5CEBA4F23C8",
|
||
|
"postfix" => "v3",
|
||
|
"convert" => "v3b",
|
||
|
"sid" => 1
|
||
|
"sid" => 1,
|
||
|
"enable_polyphasic_scaler" => 0,
|
||
|
"enable_area_scaler" => 1
|
||
|
},
|
||
|
"A2EBArom" =>
|
||
|
{
|
||
|
"internal_ram" => 32768,
|
||
|
"internal_ram" => 65536,
|
||
|
"internal_rom" => 1,
|
||
|
"fpga" => "5CEBA2F23C8",
|
||
|
"postfix" => "v1",
|
||
|
"sid" => 0
|
||
|
"sid" => 0,
|
||
|
"enable_polyphasic_scaler" => 0,
|
||
|
"enable_area_scaler" => 1
|
||
|
},
|
||
|
"A4EBArom" =>
|
||
|
{
|
||
| eclaireXL_ITX/zpu_romv1.mif | ||
|---|---|---|
|
009e : 00000000;
|
||
|
009f : 00000000;
|
||
|
00a0 : 71fc0608;
|
||
|
00a1 : 0b0b829e;
|
||
|
00a2 : c0738306;
|
||
|
00a1 : 0b0b82a3;
|
||
|
00a2 : e0738306;
|
||
|
00a3 : 10100508;
|
||
|
00a4 : 060b0b0b;
|
||
|
00a5 : 88a20400;
|
||
| ... | ... | |
|
00cd : 00000000;
|
||
|
00ce : 00000000;
|
||
|
00cf : 00000000;
|
||
|
00d0 : 810b82b1;
|
||
|
00d0 : 810b82b7;
|
||
|
00d1 : a00c5104;
|
||
|
00d2 : 00000000;
|
||
|
00d3 : 00000000;
|
||
| ... | ... | |
|
0116 : 83c08008;
|
||
|
0117 : 83c08408;
|
||
|
0118 : 83c08808;
|
||
|
0119 : 757581ac;
|
||
|
011a : 892d5050;
|
||
|
0119 : 757581ae;
|
||
|
011a : d52d5050;
|
||
|
011b : 83c08008;
|
||
|
011c : 5683c088;
|
||
|
011d : 0c83c084;
|
||
| ... | ... | |
|
0120 : c0800883;
|
||
|
0121 : c0840883;
|
||
|
0122 : c0880875;
|
||
|
0123 : 7581abc8;
|
||
|
0123 : 7581ae94;
|
||
|
0124 : 2d505083;
|
||
|
0125 : c0800856;
|
||
|
0126 : 83c0880c;
|
||
| ... | ... | |
|
0129 : 51040000;
|
||
|
012a : 800489aa;
|
||
|
012b : 0489aa0b;
|
||
|
012c : 80eda804;
|
||
|
012c : 80ee9504;
|
||
|
012d : fd3d0d75;
|
||
|
012e : 705254ae;
|
||
|
012f : c83f83c0;
|
||
| ... | ... | |
|
0221 : 0d7b7d5a;
|
||
|
0222 : 5a82d052;
|
||
|
0223 : 83c2d408;
|
||
|
0224 : 51819a94;
|
||
|
0224 : 51819ce0;
|
||
|
0225 : 3f83c080;
|
||
|
0226 : 0857f9aa;
|
||
|
0227 : 3f795283;
|
||
| ... | ... | |
|
022d : 81068283;
|
||
|
022e : 3883c0b8;
|
||
|
022f : 080b0b82;
|
||
|
0230 : a9905370;
|
||
|
0230 : aee45370;
|
||
|
0231 : 5256a6a1;
|
||
|
0232 : 3f0b0b82;
|
||
|
0233 : a9905280;
|
||
|
0233 : aee45280;
|
||
|
0234 : c01651a6;
|
||
|
0235 : 943f75bc;
|
||
|
0236 : 170c7382;
|
||
| ... | ... | |
|
0344 : ffab3976;
|
||
|
0345 : 982b5574;
|
||
|
0346 : 80258738;
|
||
|
0347 : 829dd017;
|
||
|
0347 : 82a2f017;
|
||
|
0348 : 3357ff9f;
|
||
|
0349 : 17557499;
|
||
|
034a : 268938e0;
|
||
| ... | ... | |
|
0408 : 842a903d;
|
||
|
0409 : 33547171;
|
||
|
040a : 31535656;
|
||
|
040b : 818af93f;
|
||
|
040b : 818dc53f;
|
||
|
040c : 83c08008;
|
||
|
040d : 82057088;
|
||
|
040e : 1c0c83c0;
|
||
| ... | ... | |
|
04a8 : 5376802e;
|
||
|
04a9 : b7387452;
|
||
|
04aa : ff165181;
|
||
|
04ab : 85fa3f83;
|
||
|
04ab : 88c63f83;
|
||
|
04ac : c08008ff;
|
||
|
04ad : 18765470;
|
||
|
04ae : 53585381;
|
||
|
04af : 85ea3f83;
|
||
|
04af : 88b63f83;
|
||
|
04b0 : c0800873;
|
||
|
04b1 : 26963874;
|
||
|
04b2 : 30707806;
|
||
| ... | ... | |
|
0585 : 902e0981;
|
||
|
0586 : 0680cd38;
|
||
|
0587 : 02ab0533;
|
||
|
0588 : 82b1a80b;
|
||
|
0589 : 82b1a833;
|
||
|
0588 : 82b7a80b;
|
||
|
0589 : 82b7a833;
|
||
|
058a : 5758568c;
|
||
|
058b : 3974762e;
|
||
|
058c : 8a388417;
|
||
| ... | ... | |
|
05cf : 800880d0;
|
||
|
05d0 : 387451e5;
|
||
|
05d1 : c33f83c0;
|
||
|
05d2 : 800882a9;
|
||
|
05d3 : 9c5383c0;
|
||
|
05d2 : 800882ae;
|
||
|
05d3 : f05383c0;
|
||
|
05d4 : 80085253;
|
||
|
05d5 : fea33f83;
|
||
|
05d6 : c08008b0;
|
||
|
05d7 : 3882a9a0;
|
||
|
05d7 : 3882aef4;
|
||
|
05d8 : 527251fe;
|
||
|
05d9 : 943f83c0;
|
||
|
05da : 8008a138;
|
||
|
05db : 82a9a452;
|
||
|
05db : 82aef852;
|
||
|
05dc : 7251fe85;
|
||
|
05dd : 3f83c080;
|
||
|
05de : 08923882;
|
||
|
05df : a9a85272;
|
||
|
05df : aefc5272;
|
||
|
05e0 : 51fdf63f;
|
||
|
05e1 : 83c08008;
|
||
|
05e2 : 802e8338;
|
||
| ... | ... | |
|
05f7 : 2e85cf38;
|
||
|
05f8 : 86537a52;
|
||
|
05f9 : 83c09451;
|
||
|
05fa : a9913f7e;
|
||
|
05fa : a9eb3f7e;
|
||
|
05fb : 51daae3f;
|
||
|
05fc : 83c08008;
|
||
|
05fd : 33973d56;
|
||
|
05fe : 54737b2e;
|
||
|
05ff : 09810696;
|
||
|
0600 : 3882b5c8;
|
||
|
0600 : 3882bbc8;
|
||
|
0601 : 52745187;
|
||
|
0602 : e03f9a39;
|
||
|
0603 : 7e527851;
|
||
| ... | ... | |
|
0626 : 55577380;
|
||
|
0627 : 24ed3874;
|
||
|
0628 : 602e8638;
|
||
|
0629 : a9cc3f74;
|
||
|
0629 : aaa63f74;
|
||
|
062a : 4078ff1b;
|
||
|
062b : 70585e58;
|
||
|
062c : 807a2595;
|
||
| ... | ... | |
|
0632 : 38800b83;
|
||
|
0633 : c7dc0c81;
|
||
|
0634 : 800b83c8;
|
||
|
0635 : b80c82a9;
|
||
|
0636 : ac518be4;
|
||
|
0635 : b80c82af;
|
||
|
0636 : 80518be4;
|
||
|
0637 : 3f800b83;
|
||
|
0638 : c8b80c83;
|
||
|
0639 : c0945282;
|
||
|
063a : a9b4518b;
|
||
|
063a : af88518b;
|
||
|
063b : d33fa80b;
|
||
|
063c : 83c7dc0c;
|
||
|
063d : 76802e80;
|
||
| ... | ... | |
|
0645 : 56e29b3f;
|
||
|
0646 : 83c08008;
|
||
|
0647 : 802e8838;
|
||
|
0648 : 82a9c051;
|
||
|
0648 : 82af9451;
|
||
|
0649 : 8b9a3f76;
|
||
|
064a : 51e1dd3f;
|
||
|
064b : 83c08008;
|
||
|
064c : 5282adb8;
|
||
|
064c : 5282b38c;
|
||
|
064d : 518b893f;
|
||
|
064e : 7651e1e5;
|
||
|
064f : 3f83c080;
|
||
| ... | ... | |
|
065b : 9b3f83c0;
|
||
|
065c : 80087852;
|
||
|
065d : 55e1bb3f;
|
||
|
065e : 82a9c854;
|
||
|
065e : 82af9c54;
|
||
|
065f : 83c08008;
|
||
|
0660 : 853882ac;
|
||
|
0661 : bc547453;
|
||
|
0662 : 735282a9;
|
||
|
0663 : 94518ab0;
|
||
|
0660 : 853882b2;
|
||
|
0661 : 90547453;
|
||
|
0662 : 735282ae;
|
||
|
0663 : e8518ab0;
|
||
|
0664 : 3f805482;
|
||
|
0665 : ac98518a;
|
||
|
0665 : b1ec518a;
|
||
|
0666 : a73f8114;
|
||
|
0667 : 5473a82e;
|
||
|
0668 : 098106ef;
|
||
|
0669 : 38868da0;
|
||
|
066a : 51a5ca3f;
|
||
|
066a : 51a6a43f;
|
||
|
066b : 8052913d;
|
||
|
066c : 70525780;
|
||
|
066d : fc893f83;
|
||
|
066d : fed53f83;
|
||
|
066e : 52765180;
|
||
|
066f : fc813f64;
|
||
|
066f : fecd3f64;
|
||
|
0670 : 5473ff2e;
|
||
|
0671 : 09810697;
|
||
|
0672 : 38ff1b70;
|
||
| ... | ... | |
|
067a : 81069138;
|
||
|
067b : 86538052;
|
||
|
067c : 83c09451;
|
||
|
067d : a5853f80;
|
||
|
067d : a5df3f80;
|
||
|
067e : 5b81a539;
|
||
|
067f : 7383c094;
|
||
|
0680 : 1c34811b;
|
||
| ... | ... | |
|
0691 : 2efbc538;
|
||
|
0692 : 7851dfbc;
|
||
|
0693 : 3f83c080;
|
||
|
0694 : 085282a9;
|
||
|
0695 : 905181ea;
|
||
|
0694 : 085282ae;
|
||
|
0695 : e45181ea;
|
||
|
0696 : 3f83c080;
|
||
|
0697 : 08a3387d;
|
||
|
0698 : 5183a23f;
|
||
| ... | ... | |
|
06a7 : 5afbc539;
|
||
|
06a8 : 63802efb;
|
||
|
06a9 : 88388052;
|
||
|
06aa : 765180fa;
|
||
|
06ab : 923fa53d;
|
||
|
06aa : 765180fc;
|
||
|
06ab : de3fa53d;
|
||
|
06ac : 0d04ff3d;
|
||
|
06ad : 0d028f05;
|
||
|
06ae : 33701081;
|
||
| ... | ... | |
|
06b5 : 2a708106;
|
||
|
06b6 : 51515170;
|
||
|
06b7 : 802e8738;
|
||
|
06b8 : 80cef53f;
|
||
|
06b8 : 80d1c13f;
|
||
|
06b9 : e9397190;
|
||
|
06ba : 88800c83;
|
||
|
06bb : 3d0d0480;
|
||
| ... | ... | |
|
06be : 2a708106;
|
||
|
06bf : 51515170;
|
||
|
06c0 : 802e8738;
|
||
|
06c1 : 80ced13f;
|
||
|
06c1 : 80d19d3f;
|
||
|
06c2 : e9399088;
|
||
|
06c3 : 880883c0;
|
||
|
06c4 : 800c823d;
|
||
| ... | ... | |
|
06c9 : 54548073;
|
||
|
06ca : 25943873;
|
||
|
06cb : 70810555;
|
||
|
06cc : 335282a9;
|
||
|
06cd : cc518788;
|
||
|
06cc : 335282af;
|
||
|
06cd : a0518788;
|
||
|
06ce : 3fff1353;
|
||
|
06cf : e939853d;
|
||
|
06d0 : 0d04fd3d;
|
||
| ... | ... | |
|
070d : 80598155;
|
||
|
070e : 8539747a;
|
||
|
070f : 29557452;
|
||
|
0710 : 755180f2;
|
||
|
0711 : e33f83c0;
|
||
|
0710 : 755180f5;
|
||
|
0711 : af3f83c0;
|
||
|
0712 : 80087a27;
|
||
|
0713 : ed387480;
|
||
|
0714 : 2e80e038;
|
||
|
0715 : 74527551;
|
||
|
0716 : 80f2cd3f;
|
||
|
0716 : 80f5993f;
|
||
|
0717 : 83c08008;
|
||
|
0718 : 75537652;
|
||
|
0719 : 5480f2d0;
|
||
|
0719 : 5480f59c;
|
||
|
071a : 3f83c080;
|
||
|
071b : 087a5375;
|
||
|
071c : 525680f2;
|
||
|
071d : b33f83c0;
|
||
|
071c : 525680f4;
|
||
|
071d : ff3f83c0;
|
||
|
071e : 80087930;
|
||
|
071f : 707b079f;
|
||
|
0720 : 2a707780;
|
||
| ... | ... | |
|
0885 : 547281aa;
|
||
|
0886 : 2e8d3881;
|
||
|
0887 : c73980e4;
|
||
|
0888 : 5194d23f;
|
||
|
0888 : 5195ac3f;
|
||
|
0889 : ff145473;
|
||
|
088a : 802e81b8;
|
||
|
088b : 38820a52;
|
||
| ... | ... | |
|
08a8 : 38735580;
|
||
|
08a9 : c15680ce;
|
||
|
08aa : 90548a39;
|
||
|
08ab : 80e45193;
|
||
|
08ac : c43fff14;
|
||
|
08ab : 80e45194;
|
||
|
08ac : 9e3fff14;
|
||
|
08ad : 5473802e;
|
||
|
08ae : a9388052;
|
||
|
08af : 7551fca0;
|
||
| ... | ... | |
|
08f9 : a7885472;
|
||
|
08fa : 852e8c38;
|
||
|
08fb : 9e3980e4;
|
||
|
08fc : 5191823f;
|
||
|
08fc : 5191dc3f;
|
||
|
08fd : ff1454f9;
|
||
|
08fe : bf3f83c0;
|
||
|
08ff : 800881ff;
|
||
| ... | ... | |
|
090c : 863d0d04;
|
||
|
090d : fd3d0d75;
|
||
|
090e : 78547753;
|
||
|
090f : 70525490;
|
||
|
0910 : ba3f7383;
|
||
|
090f : 70525491;
|
||
|
0910 : 943f7383;
|
||
|
0911 : c0800c85;
|
||
|
0912 : 3d0d04eb;
|
||
|
0913 : 3d0d6769;
|
||
| ... | ... | |
|
0916 : 80448043;
|
||
|
0917 : 80428070;
|
||
|
0918 : 71405b5c;
|
||
|
0919 : 928c3f80;
|
||
|
0919 : 92e63f80;
|
||
|
091a : 0b83c7dc;
|
||
|
091b : 0c800b83;
|
||
|
091c : c8b80c60;
|
||
| ... | ... | |
|
093a : 5973802e;
|
||
|
093b : 903883c7;
|
||
|
093c : e0335473;
|
||
|
093d : 883882a9;
|
||
|
093e : d451f3c4;
|
||
|
093d : 883882af;
|
||
|
093e : a851f3c4;
|
||
|
093f : 3f7583c7;
|
||
|
0940 : dc0c7717;
|
||
|
0941 : 8c163370;
|
||
| ... | ... | |
|
0944 : 57738738;
|
||
|
0945 : 901555fe;
|
||
|
0946 : ea39868d;
|
||
|
0947 : a0518ed5;
|
||
|
0947 : a0518faf;
|
||
|
0948 : 3f805292;
|
||
|
0949 : 3d70525b;
|
||
|
094a : 80e5943f;
|
||
|
094a : 80e7e03f;
|
||
|
094b : 83527a51;
|
||
|
094c : 80e58c3f;
|
||
|
094c : 80e7d83f;
|
||
|
094d : 64547382;
|
||
|
094e : a4386555;
|
||
|
094f : 80752583;
|
||
| ... | ... | |
|
0958 : 2c720652;
|
||
|
0959 : 555a767a;
|
||
|
095a : 248438ff;
|
||
|
095b : 175ab9e8;
|
||
|
095b : 175abcb4;
|
||
|
095c : 3f80608c;
|
||
|
095d : 055757fc;
|
||
|
095e : 16085574;
|
||
| ... | ... | |
|
09bc : 8b3fa053;
|
||
|
09bd : 805283c7;
|
||
|
09be : d40883a0;
|
||
|
09bf : 8005518a;
|
||
|
09c0 : fa3fa053;
|
||
|
09bf : 8005518b;
|
||
|
09c0 : d43fa053;
|
||
|
09c1 : 805283c7;
|
||
|
09c2 : d40883a4;
|
||
|
09c3 : 8005518a;
|
||
|
09c4 : ea3f9053;
|
||
|
09c3 : 8005518b;
|
||
|
09c4 : c43f9053;
|
||
|
09c5 : 805283c7;
|
||
|
09c6 : d40883a8;
|
||
|
09c7 : 8005518a;
|
||
|
09c8 : da3fff76;
|
||
|
09c7 : 8005518b;
|
||
|
09c8 : b43fff76;
|
||
|
09c9 : 3483a080;
|
||
|
09ca : 54805383;
|
||
|
09cb : c7d00852;
|
||
| ... | ... | |
|
09d0 : 83c7d008;
|
||
|
09d1 : 5283c7d4;
|
||
|
09d2 : 0851feb0;
|
||
|
09d3 : 3f8ca33f;
|
||
|
09d3 : 3f8cfd3f;
|
||
|
09d4 : a2548053;
|
||
|
09d5 : 83c7d408;
|
||
|
09d6 : 8c800552;
|
||
|
09d7 : 82b29c51;
|
||
|
09d7 : 82b89c51;
|
||
|
09d8 : fe9a3f86;
|
||
|
09d9 : 0b87a883;
|
||
|
09da : 34800b87;
|
||
| ... | ... | |
|
0abe : 0c525283;
|
||
|
0abf : 3d0d0480;
|
||
|
0ac0 : 3d0d9080;
|
||
|
0ac1 : d00883ff;
|
||
|
0ac2 : ff0683c0;
|
||
|
0ac3 : 800c823d;
|
||
|
0ac4 : 0d04ff3d;
|
||
|
0ac5 : 0d9080d0;
|
||
|
0ac6 : 700870fc;
|
||
|
0ac7 : 80800676;
|
||
|
0ac8 : 07720c52;
|
||
|
0ac9 : 52833d0d;
|
||
|
0aca : 04803d0d;
|
||
|
0acb : 9080d008;
|
||
|
0acc : 70902c81;
|
||
|
0acd : ff0683c0;
|
||
|
0ace : 800c5182;
|
||
|
0acf : 3d0d04ff;
|
||
|
0ad0 : 3d0d9080;
|
||
|
0ad1 : d0700870;
|
||
|
0ad2 : f883ffff;
|
||
|
0ad3 : 0676902b;
|
||
|
0ac1 : bc087087;
|
||
|
0ac2 : 2c870683;
|
||
|
0ac3 : c0800c51;
|
||
|
0ac4 : 823d0d04;
|
||
|
0ac5 : ff3d0d90;
|
||
|
0ac6 : 80bc7008;
|
||
|
0ac7 : 70f8ff06;
|
||
|
0ac8 : 76872b07;
|
||
|
0ac9 : 720c5252;
|
||
|
0aca : 833d0d04;
|
||
|
0acb : 803d0d90;
|
||
|
0acc : 80bc0870;
|
||
|
0acd : 8a2c8706;
|
||
|
0ace : 83c0800c;
|
||
|
0acf : 51823d0d;
|
||
|
0ad0 : 04ff3d0d;
|
||
|
0ad1 : 9080bc70;
|
||
|
0ad2 : 0870c7ff;
|
||
|
0ad3 : 06768a2b;
|
||
|
0ad4 : 07720c52;
|
||
|
0ad5 : 52833d0d;
|
||
|
0ad6 : 04803d0d;
|
||
|
0ad7 : 9080d008;
|
||
|
0ad8 : 70982c81;
|
||
|
0ad9 : 0683c080;
|
||
|
0ada : 0c51823d;
|
||
|
0adb : 0d04ff3d;
|
||
|
0adc : 0d9080d0;
|
||
|
0add : 700870fe;
|
||
|
0ade : ff0a0676;
|
||
|
0adf : 982b0772;
|
||
|
0ae0 : 0c525283;
|
||
|
0ae1 : 3d0d0480;
|
||
|
0ae2 : 3d0d9080;
|
||
|
0ae3 : d0087099;
|
||
|
0ae4 : 2c810683;
|
||
|
0ae5 : c0800c51;
|
||
|
0ae6 : 823d0d04;
|
||
|
0ae7 : ff3d0d90;
|
||
|
0ae8 : 80d07008;
|
||
|
0ae9 : 70ffbf0a;
|
||
|
0aea : 0676992b;
|
||
|
0aeb : 07720c52;
|
||
|
0aec : 52833d0d;
|
||
|
0aed : 04803d0d;
|
||
|
0aee : 9080d008;
|
||
|
0aef : 709a2c81;
|
||
|
0af0 : 0683c080;
|
||
|
0af1 : 0c51823d;
|
||
|
0af2 : 0d04ff3d;
|
||
|
0af3 : 0d9080d0;
|
||
|
0af4 : 700870df;
|
||
|
0af5 : 0a06769a;
|
||
|
0af6 : 2b07720c;
|
||
|
0af7 : 5252833d;
|
||
|
0af8 : 0d04803d;
|
||
|
0af9 : 0d908080;
|
||
|
0afa : 0870882c;
|
||
|
0afb : 810683c0;
|
||
|
0afc : 800c5182;
|
||
|
0afd : 3d0d0480;
|
||
|
0afe : 3d0d9080;
|
||
|
0aff : 80087089;
|
||
|
0b00 : 2c810683;
|
||
|
0b01 : c0800c51;
|
||
|
0b02 : 823d0d04;
|
||
|
0b03 : 803d0d90;
|
||
|
0b04 : 80800870;
|
||
|
0b05 : 8a2c8106;
|
||
|
0b06 : 83c0800c;
|
||
|
0b07 : 51823d0d;
|
||
|
0b08 : 04803d0d;
|
||
|
0b09 : 90808008;
|
||
|
0b0a : 708b2c81;
|
||
|
0b0b : 0683c080;
|
||
|
0b0c : 0c51823d;
|
||
|
0b0d : 0d04803d;
|
||
|
0b0e : 0d908080;
|
||
|
0b0f : 08708c2c;
|
||
|
0b10 : bf0683c0;
|
||
|
0b11 : 800c5182;
|
||
|
0b12 : 3d0d0480;
|
||
|
0b13 : 3d0d9080;
|
||
|
0b14 : 80087092;
|
||
|
0b15 : 2c810683;
|
||
|
0b16 : c0800c51;
|
||
|
0b17 : 823d0d04;
|
||
|
0b18 : 803d0d90;
|
||
|
0b19 : 80800870;
|
||
|
0b1a : 932c8106;
|
||
|
0b1b : 83c0800c;
|
||
|
0b1c : 51823d0d;
|
||
|
0b1d : 04719080;
|
||
|
0b1e : a00c04fe;
|
||
|
0b1f : 3d0d7575;
|
||
|
0b20 : ff195353;
|
||
|
0b21 : 5370ff2e;
|
||
|
0b22 : 8d387272;
|
||
|
0b23 : 70810554;
|
||
|
0b24 : 34ff1151;
|
||
|
0b25 : f039843d;
|
||
|
0b26 : 0d04fe3d;
|
||
|
0b27 : 0d7575ff;
|
||
|
0b28 : 19535353;
|
||
|
0b29 : 70ff2e8d;
|
||
|
0b2a : 38727270;
|
||
|
0b2b : 8405540c;
|
||
|
0b2c : ff1151f0;
|
||
|
0b2d : 39843d0d;
|
||
|
0b2e : 04fe3d0d;
|
||
|
0b2f : 88805380;
|
||
|
0b30 : 5288800a;
|
||
|
0b31 : 51ffb43f;
|
||
|
0b32 : 82805380;
|
||
|
0b33 : 5282800a;
|
||
|
0b34 : 51c83f80;
|
||
|
0b35 : 0b87aa80;
|
||
|
0b36 : 34843d0d;
|
||
|
0b37 : 04803d0d;
|
||
|
0b38 : 8151f7c5;
|
||
|
0b39 : 3f72802e;
|
||
|
0b3a : 90388051;
|
||
|
0b3b : f9c63fc9;
|
||
|
0b3c : 3f83c7d8;
|
||
|
0b3d : 3351f9bc;
|
||
|
0b3e : 3f8151f7;
|
||
|
0b3f : d63f8051;
|
||
|
0b40 : f7d13f80;
|
||
|
0b41 : 51f7a23f;
|
||
|
0b42 : 823d0d04;
|
||
|
0b43 : fd3d0d75;
|
||
|
0b44 : 52805480;
|
||
|
0b45 : ff722588;
|
||
Also available in: Unified diff
Add area scaler to A2 v1 and v3 boards. Add both scalers to the A4 v3 board.