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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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--USE ieee.std_logic_arith.all;
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--USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.all;
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use work.pixels.all;
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--TODO: scanlines!!
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--out_colour(7 downto 4) <= out_colour_raw(7 downto 4);
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--out_colour(3 downto 0) <= out_colour_raw(3 downto 0) when (not(out_scanlines) or vcnt(0))='1' else '0'&out_colour_raw(3 downto 1);
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ENTITY polyphasicscale IS
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PORT(
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clock : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --asynchronous reset
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-- input pixels
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pixels : in t_Pixel4x4;
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-- next output line
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next_y_in : in std_logic;
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next_frame_in : in std_logic;
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field2 : in std_logic;
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-- sync/blank from crtc -> need to be delayed in line with pipeline
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hsync_in : in std_logic;
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vsync_in : in std_logic;
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blank_in : in std_logic;
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-- need to provide control signals:
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next_x : OUT STD_LOGIC;
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next_x_size : out std_logic_vector(1 downto 0);
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next_y : OUT STD_LOGIC;
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-- need to output
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-- current pixel
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r : out std_logic_vector(7 downto 0);
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g : out std_logic_vector(7 downto 0);
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b : out std_logic_vector(7 downto 0);
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hsync : out std_logic;
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vsync : out std_logic;
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blank : out std_logic;
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-- to set up params
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sda : inout std_logic;
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scl : inout std_logic
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);
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END polyphasicscale;
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-- customscalex:568 customscaley:256 xdelta:640 ydelta:102 TA:65536
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ARCHITECTURE vhdl OF polyphasicscale IS
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signal fixed_xthreshold_reg : unsigned(10 downto 0);
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signal fixed_ythreshold_reg : unsigned(10 downto 0);
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signal param_xdelta_reg : unsigned(10 downto 0);
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signal param_ydeltaeach_reg : unsigned(10 downto 0);
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signal param_xaddrskip_reg : unsigned(1 downto 0);-- We only support upscaling, so for some cases need to skip 2 pixels
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signal params : std_logic_vector((11*3)-1 downto 0);
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-- stage 1:5 Delay syncs in line with pipeline
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signal hsync_next : std_logic_vector(6 downto 1);
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signal hsync_reg : std_logic_vector(6 downto 1);
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signal vsync_next : std_logic_vector(6 downto 1);
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signal vsync_reg : std_logic_vector(6 downto 1);
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signal blank_next : std_logic_vector(6 downto 1);
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signal blank_reg : std_logic_vector(6 downto 1);
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-- stage 1 : Accumulators/ data request
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signal xacc_next : unsigned(11 downto 0);
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signal xacc_reg : unsigned(11 downto 0);
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signal yacc_next : unsigned(11 downto 0);
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signal yacc_reg : unsigned(11 downto 0);
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signal next_x_delay1_next : std_logic;
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signal next_x_delay1_reg : std_logic;
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-- stage 2 : Coefs calc
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type t_Coef is record
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c1 : signed(8 downto 0);
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c2 : signed(8 downto 0);
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c3 : signed(8 downto 0);
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c4 : signed(8 downto 0);
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end record t_Coef;
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signal coefx_next: t_Coef;
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signal coefx_reg : t_Coef;
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signal coefx3_next: t_Coef;
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signal coefx3_reg : t_Coef;
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signal coefx4_next: t_Coef;
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signal coefx4_reg : t_Coef;
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signal coefy_next: t_Coef;
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signal coefy_reg : t_Coef;
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signal next_x_delay2_next : std_logic;
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signal next_x_delay2_reg : std_logic;
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-- stage 3 : Y mult
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signal ry1_next : signed(17 downto 0);
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signal ry1_reg : signed(17 downto 0);
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signal ry2_next : signed(17 downto 0);
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signal ry2_reg : signed(17 downto 0);
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signal ry3_next : signed(17 downto 0);
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signal ry3_reg : signed(17 downto 0);
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signal ry4_next : signed(17 downto 0);
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signal ry4_reg : signed(17 downto 0);
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signal gy1_next : signed(17 downto 0);
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signal gy1_reg : signed(17 downto 0);
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signal gy2_next : signed(17 downto 0);
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signal gy2_reg : signed(17 downto 0);
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signal gy3_next : signed(17 downto 0);
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signal gy3_reg : signed(17 downto 0);
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signal gy4_next : signed(17 downto 0);
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signal gy4_reg : signed(17 downto 0);
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signal by1_next : signed(17 downto 0);
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signal by1_reg : signed(17 downto 0);
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signal by2_next : signed(17 downto 0);
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signal by2_reg : signed(17 downto 0);
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signal by3_next : signed(17 downto 0);
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signal by3_reg : signed(17 downto 0);
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signal by4_next : signed(17 downto 0);
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signal by4_reg : signed(17 downto 0);
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signal next_x_delay3_next : std_logic;
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signal next_x_delay3_reg : std_logic;
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-- stage 4: X pixels
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signal pixel_rx1_next : signed(8 downto 0);
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signal pixel_rx1_reg : signed(8 downto 0);
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signal pixel_rx2_next : signed(8 downto 0);
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signal pixel_rx2_reg : signed(8 downto 0);
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signal pixel_rx3_next : signed(8 downto 0);
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signal pixel_rx3_reg : signed(8 downto 0);
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signal pixel_rx4_next : signed(8 downto 0);
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signal pixel_rx4_reg : signed(8 downto 0);
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signal pixel_gx1_next : signed(8 downto 0);
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signal pixel_gx1_reg : signed(8 downto 0);
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signal pixel_gx2_next : signed(8 downto 0);
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signal pixel_gx2_reg : signed(8 downto 0);
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signal pixel_gx3_next : signed(8 downto 0);
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signal pixel_gx3_reg : signed(8 downto 0);
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signal pixel_gx4_next : signed(8 downto 0);
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signal pixel_gx4_reg : signed(8 downto 0);
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signal pixel_bx1_next : signed(8 downto 0);
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signal pixel_bx1_reg : signed(8 downto 0);
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signal pixel_bx2_next : signed(8 downto 0);
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signal pixel_bx2_reg : signed(8 downto 0);
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signal pixel_bx3_next : signed(8 downto 0);
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signal pixel_bx3_reg : signed(8 downto 0);
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signal pixel_bx4_next : signed(8 downto 0);
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signal pixel_bx4_reg : signed(8 downto 0);
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-- stage 5: X mult
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signal rx1_next : signed(17 downto 0);
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signal rx1_reg : signed(17 downto 0);
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signal rx2_next : signed(17 downto 0);
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signal rx2_reg : signed(17 downto 0);
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signal rx3_next : signed(17 downto 0);
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signal rx3_reg : signed(17 downto 0);
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signal rx4_next : signed(17 downto 0);
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signal rx4_reg : signed(17 downto 0);
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signal gx1_next : signed(17 downto 0);
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signal gx1_reg : signed(17 downto 0);
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signal gx2_next : signed(17 downto 0);
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signal gx2_reg : signed(17 downto 0);
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signal gx3_next : signed(17 downto 0);
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signal gx3_reg : signed(17 downto 0);
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signal gx4_next : signed(17 downto 0);
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signal gx4_reg : signed(17 downto 0);
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signal bx1_next : signed(17 downto 0);
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signal bx1_reg : signed(17 downto 0);
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signal bx2_next : signed(17 downto 0);
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signal bx2_reg : signed(17 downto 0);
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signal bx3_next : signed(17 downto 0);
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signal bx3_reg : signed(17 downto 0);
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signal bx4_next : signed(17 downto 0);
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signal bx4_reg : signed(17 downto 0);
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-- stage 6: Pixel output (sum)
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signal r_reg : std_logic_vector(7 downto 0);
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signal r_next : std_logic_vector(7 downto 0);
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signal g_reg : std_logic_vector(7 downto 0);
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signal g_next : std_logic_vector(7 downto 0);
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signal b_reg : std_logic_vector(7 downto 0);
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signal b_next : std_logic_vector(7 downto 0);
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BEGIN
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process(clock,reset_n)
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begin
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if (reset_n='0') then
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-- multi stage 1-5
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hsync_reg <= (others=>'0');
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vsync_reg <= (others=>'0');
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blank_reg <= (others=>'0');
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-- stage 1
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xacc_reg <= (others=>'0');
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yacc_reg <= (others=>'0');
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next_x_delay1_reg <= '0';
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-- stage 2
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coefx_reg.c1 <= (others=>'0');
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coefx_reg.c2 <= (others=>'0');
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coefx_reg.c3 <= (others=>'0');
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coefx_reg.c4 <= (others=>'0');
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coefy_reg.c1 <= (others=>'0');
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coefy_reg.c2 <= (others=>'0');
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coefy_reg.c3 <= (others=>'0');
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coefy_reg.c4 <= (others=>'0');
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next_x_delay2_reg <= '0';
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-- stage 3
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ry1_reg <= (others=>'0');
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ry2_reg <= (others=>'0');
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ry3_reg <= (others=>'0');
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ry4_reg <= (others=>'0');
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gy1_reg <= (others=>'0');
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gy2_reg <= (others=>'0');
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gy3_reg <= (others=>'0');
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gy4_reg <= (others=>'0');
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by1_reg <= (others=>'0');
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by2_reg <= (others=>'0');
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by3_reg <= (others=>'0');
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by4_reg <= (others=>'0');
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coefx3_reg.c1 <= (others=>'0');
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coefx3_reg.c2 <= (others=>'0');
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coefx3_reg.c3 <= (others=>'0');
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coefx3_reg.c4 <= (others=>'0');
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next_x_delay3_reg <= '0';
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-- stage 4
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pixel_rx1_reg <= (others=>'0');
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pixel_gx1_reg <= (others=>'0');
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pixel_bx1_reg <= (others=>'0');
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pixel_rx2_reg <= (others=>'0');
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pixel_gx2_reg <= (others=>'0');
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pixel_bx2_reg <= (others=>'0');
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pixel_rx3_reg <= (others=>'0');
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pixel_gx3_reg <= (others=>'0');
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pixel_bx3_reg <= (others=>'0');
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pixel_rx4_reg <= (others=>'0');
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pixel_gx4_reg <= (others=>'0');
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pixel_bx4_reg <= (others=>'0');
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coefx4_reg.c1 <= (others=>'0');
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coefx4_reg.c2 <= (others=>'0');
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coefx4_reg.c3 <= (others=>'0');
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coefx4_reg.c4 <= (others=>'0');
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-- stage 5
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rx1_reg <= (others=>'0');
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rx2_reg <= (others=>'0');
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rx3_reg <= (others=>'0');
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rx4_reg <= (others=>'0');
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gx1_reg <= (others=>'0');
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gx2_reg <= (others=>'0');
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gx3_reg <= (others=>'0');
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gx4_reg <= (others=>'0');
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bx1_reg <= (others=>'0');
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bx2_reg <= (others=>'0');
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bx3_reg <= (others=>'0');
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bx4_reg <= (others=>'0');
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-- stage 6
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r_reg <= (others=>'0');
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g_reg <= (others=>'0');
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b_reg <= (others=>'0');
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elsif (clock'event and clock='1') then
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-- multi stage 1-5
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hsync_reg <= hsync_next;
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vsync_reg <= vsync_next;
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blank_reg <= blank_next;
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-- stage 1
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xacc_reg <= xacc_next;
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yacc_reg <= yacc_next;
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next_x_delay1_reg <= next_x_delay1_next;
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-- stage 2
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coefx_reg <= coefx_next;
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coefy_reg <= coefy_next;
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next_x_delay2_reg <= next_x_delay2_next;
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-- stage 3
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ry1_reg <= ry1_next;
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ry2_reg <= ry2_next;
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ry3_reg <= ry3_next;
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ry4_reg <= ry4_next;
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gy1_reg <= gy1_next;
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gy2_reg <= gy2_next;
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gy3_reg <= gy3_next;
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gy4_reg <= gy4_next;
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by1_reg <= by1_next;
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by2_reg <= by2_next;
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by3_reg <= by3_next;
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by4_reg <= by4_next;
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coefx3_reg <= coefx3_next;
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next_x_delay3_reg <= next_x_delay3_next;
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-- stage 4
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pixel_rx1_reg <= pixel_rx1_next;
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pixel_gx1_reg <= pixel_gx1_next;
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pixel_bx1_reg <= pixel_bx1_next;
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pixel_rx2_reg <= pixel_rx2_next;
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pixel_gx2_reg <= pixel_gx2_next;
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pixel_bx2_reg <= pixel_bx2_next;
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pixel_rx3_reg <= pixel_rx3_next;
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pixel_gx3_reg <= pixel_gx3_next;
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pixel_bx3_reg <= pixel_bx3_next;
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pixel_rx4_reg <= pixel_rx4_next;
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pixel_gx4_reg <= pixel_gx4_next;
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pixel_bx4_reg <= pixel_bx4_next;
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coefx4_reg <= coefx4_next;
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-- stage 5
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rx1_reg <= rx1_next;
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rx2_reg <= rx2_next;
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rx3_reg <= rx3_next;
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rx4_reg <= rx4_next;
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gx1_reg <= gx1_next;
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gx2_reg <= gx2_next;
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gx3_reg <= gx3_next;
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gx4_reg <= gx4_next;
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bx1_reg <= bx1_next;
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bx2_reg <= bx2_next;
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bx3_reg <= bx3_next;
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bx4_reg <= bx4_next;
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-- stage 6
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r_reg <= r_next;
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g_reg <= g_next;
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b_reg <= b_next;
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end if;
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end process;
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-- temporary params, until i2c implemented
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-- 720p
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-- param_xthreshold_next <= to_unsigned(699,10); -- these need to be inputs
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-- param_xdelta_next <= to_unsigned(393,10);
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-- param_ythreshold_next <= to_unsigned(400,9);
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-- param_ydelta_next <= to_unsigned(166,9);
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-- param_ydeltaeach_next <= to_unsigned(166,9);
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-- param_xaddrskip_next <= "10";
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-- 1080i
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-- param_xthreshold_next <= to_unsigned(400,11); -- these need to be inputs
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-- param_xdelta_next <= to_unsigned(300,11);
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-- param_ythreshold_next <= to_unsigned(786,11);
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-- param_ydelta_next <= to_unsigned(218,11);
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-- param_ydeltaeach_next <= to_unsigned(437,11); --interlace, need to skip a line
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-- param_xaddrskip_next <= "01";
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-- param_xthreshold_next <= to_unsigned(1024,11); -- these need to be inputs
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-- param_xdelta_next <= to_unsigned(768,11);
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-- --param_xdelta_next <= to_unsigned(64,11);
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-- param_ythreshold_next <= to_unsigned(1024,11);
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-- --param_ydelta_next <= to_unsigned(284,11);
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-- param_ydeltaeach_next <= to_unsigned(569,11); --interlace, need to skip a line
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-- param_xaddrskip_next <= "01";
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-- params set from i2c
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i2cregs : entity work.I2C_regs
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generic map (
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SLAVE_ADDR => "0000011", --will we activate this and areascale at once? i.e. do I give it another address?
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regs => 3,
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bits => 11
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)
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port map (
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scl => scl,
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sda => sda,
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clk => clock,
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rst => not(reset_n),
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reg => params
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);
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fixed_xthreshold_reg <= to_unsigned(1024,11);
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fixed_ythreshold_reg <= to_unsigned(1024,11);
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param_xdelta_reg <= unsigned(params(11*1-1 downto 11*0));
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param_ydeltaeach_reg <= unsigned(params(11*2-1 downto 11*1));
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param_xaddrskip_reg <= unsigned(params(11*2+2-1 downto 11*2));
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-- TODO: how about filter params too?
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-- Delay sync in line with pipeline: multi stage 1-5
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process(hsync_reg,vsync_reg,blank_reg,hsync_in,vsync_in,blank_in)
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begin
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hsync_next <= hsync_reg(5 downto 1)&hsync_in;
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vsync_next <= vsync_reg(5 downto 1)&vsync_in;
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blank_next <= blank_reg(5 downto 1)&blank_in;
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end process;
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-- Compute accumulator - pipeline stage 1
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process(xacc_reg,param_xdelta_reg,fixed_xthreshold_reg,next_y_in)
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begin
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next_x <= '0';
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next_x_delay1_next <= '0';
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xacc_next <= xacc_reg+param_xdelta_reg;
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if ((xacc_reg+param_xdelta_reg)>=fixed_xthreshold_reg) then
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next_x <= '1'; -- when I ask for data, its on p1 in 2 cycles, i.e. pipeline stage 3
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next_x_delay1_next <= '1';
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xacc_next <= xacc_reg+param_xdelta_reg-fixed_xthreshold_reg;
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end if;
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if (next_y_in ='1') then
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xacc_next <= (others=>'0');
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end if;
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end process;
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process(yacc_reg,param_ydeltaeach_reg,fixed_ythreshold_reg,next_y_in,next_frame_in,field2)
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begin
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yacc_next <= yacc_reg;
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next_y <= '0';
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if (next_y_in='1') then
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yacc_next <= yacc_reg+param_ydeltaeach_reg;
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if ((yacc_reg+param_ydeltaeach_reg)>=fixed_ythreshold_reg) then
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next_y <= '1';
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yacc_next <= yacc_reg+param_ydeltaeach_reg-fixed_ythreshold_reg;
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end if;
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end if;
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|
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if (next_frame_in='1') then
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yacc_next <= (others=>'0');
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if (field2='1') then --slightly lower on interlace field 2
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yacc_next(9 downto 0) <= fixed_ythreshold_reg(10 downto 1);
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end if;
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end if;
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end process;
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-- Coef computation - pipeline stage 2
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process(
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xacc_reg,
|
|
yacc_reg)
|
|
variable xphase : std_logic_vector(3 downto 0);
|
|
variable yphase : std_logic_vector(3 downto 0);
|
|
begin
|
|
coefx_next.c1 <= (others=>'0');
|
|
coefx_next.c2 <= (others=>'0');
|
|
coefx_next.c3 <= (others=>'0');
|
|
coefx_next.c4 <= (others=>'0');
|
|
coefy_next.c1 <= (others=>'0');
|
|
coefy_next.c2 <= (others=>'0');
|
|
coefy_next.c3 <= (others=>'0');
|
|
coefy_next.c4 <= (others=>'0');
|
|
|
|
xphase := std_logic_vector(xacc_reg(9 downto 6));
|
|
yphase := std_logic_vector(yacc_reg(9 downto 6));
|
|
|
|
-- case xphase is
|
|
-- when "0000" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "0001" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "0010" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "0011" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "0100" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "0101" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "0110" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "0111" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "1000" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "1001" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "1010" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "1011" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "1100" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "1101" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "1110" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when "1111" =>
|
|
-- coefx_next <= x"7f000000";
|
|
-- when others=>
|
|
-- coefx_next <= (others=>'0');
|
|
-- end case;
|
|
--
|
|
-- case yphase is
|
|
-- when "0000" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "0001" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "0010" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "0011" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "0100" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "0101" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "0110" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "0111" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "1000" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "1001" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "1010" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "1011" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "1100" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "1101" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "1110" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when "1111" =>
|
|
-- coefy_next <= x"7f000000";
|
|
-- when others=>
|
|
-- coefy_next <= (others=>'0');
|
|
-- end case;
|
|
case xphase is
|
|
when "0000" =>
|
|
coefx_next.c1 <= to_signed(-8,9);
|
|
coefx_next.c2 <= to_signed(147,9);
|
|
coefx_next.c3 <= to_signed(-8,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "0001" =>
|
|
coefx_next.c1 <= to_signed(-6,9);
|
|
coefx_next.c2 <= to_signed(148,9);
|
|
coefx_next.c3 <= to_signed(-11,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "0010" =>
|
|
coefx_next.c1 <= to_signed(-3,9);
|
|
coefx_next.c2 <= to_signed(147,9);
|
|
coefx_next.c3 <= to_signed(-13,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "0011" =>
|
|
coefx_next.c1 <= to_signed(-1,9);
|
|
coefx_next.c2 <= to_signed(145,9);
|
|
coefx_next.c3 <= to_signed(-13,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "0100" =>
|
|
coefx_next.c1 <= to_signed(0,9);
|
|
coefx_next.c2 <= to_signed(141,9);
|
|
coefx_next.c3 <= to_signed(-10,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "0101" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(133,9);
|
|
coefx_next.c3 <= to_signed(-3,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "0110" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(118,9);
|
|
coefx_next.c3 <= to_signed(12,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "0111" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(95,9);
|
|
coefx_next.c3 <= to_signed(35,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "1000" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(65,9);
|
|
coefx_next.c3 <= to_signed(65,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "1001" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(35,9);
|
|
coefx_next.c3 <= to_signed(95,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "1010" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(12,9);
|
|
coefx_next.c3 <= to_signed(118,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "1011" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(-3,9);
|
|
coefx_next.c3 <= to_signed(133,9);
|
|
coefx_next.c4 <= to_signed(1,9);
|
|
when "1100" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(-10,9);
|
|
coefx_next.c3 <= to_signed(141,9);
|
|
coefx_next.c4 <= to_signed(0,9);
|
|
when "1101" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(-13,9);
|
|
coefx_next.c3 <= to_signed(145,9);
|
|
coefx_next.c4 <= to_signed(-1,9);
|
|
when "1110" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(-13,9);
|
|
coefx_next.c3 <= to_signed(147,9);
|
|
coefx_next.c4 <= to_signed(-3,9);
|
|
when "1111" =>
|
|
coefx_next.c1 <= to_signed(1,9);
|
|
coefx_next.c2 <= to_signed(-11,9);
|
|
coefx_next.c3 <= to_signed(148,9);
|
|
coefx_next.c4 <= to_signed(-6,9);
|
|
when others =>
|
|
coefx_next.c1 <= (others=>'0');
|
|
coefx_next.c2 <= (others=>'0');
|
|
coefx_next.c3 <= (others=>'0');
|
|
coefx_next.c4 <= (others=>'0');
|
|
end case;
|
|
case yphase is
|
|
when "0000" =>
|
|
coefy_next.c1 <= to_signed(-8,9);
|
|
coefy_next.c2 <= to_signed(147,9);
|
|
coefy_next.c3 <= to_signed(-8,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "0001" =>
|
|
coefy_next.c1 <= to_signed(-6,9);
|
|
coefy_next.c2 <= to_signed(148,9);
|
|
coefy_next.c3 <= to_signed(-11,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "0010" =>
|
|
coefy_next.c1 <= to_signed(-3,9);
|
|
coefy_next.c2 <= to_signed(147,9);
|
|
coefy_next.c3 <= to_signed(-13,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "0011" =>
|
|
coefy_next.c1 <= to_signed(-1,9);
|
|
coefy_next.c2 <= to_signed(145,9);
|
|
coefy_next.c3 <= to_signed(-13,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "0100" =>
|
|
coefy_next.c1 <= to_signed(0,9);
|
|
coefy_next.c2 <= to_signed(141,9);
|
|
coefy_next.c3 <= to_signed(-10,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "0101" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(133,9);
|
|
coefy_next.c3 <= to_signed(-3,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "0110" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(118,9);
|
|
coefy_next.c3 <= to_signed(12,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "0111" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(95,9);
|
|
coefy_next.c3 <= to_signed(35,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "1000" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(65,9);
|
|
coefy_next.c3 <= to_signed(65,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "1001" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(35,9);
|
|
coefy_next.c3 <= to_signed(95,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "1010" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(12,9);
|
|
coefy_next.c3 <= to_signed(118,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "1011" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(-3,9);
|
|
coefy_next.c3 <= to_signed(133,9);
|
|
coefy_next.c4 <= to_signed(1,9);
|
|
when "1100" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(-10,9);
|
|
coefy_next.c3 <= to_signed(141,9);
|
|
coefy_next.c4 <= to_signed(0,9);
|
|
when "1101" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(-13,9);
|
|
coefy_next.c3 <= to_signed(145,9);
|
|
coefy_next.c4 <= to_signed(-1,9);
|
|
when "1110" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(-13,9);
|
|
coefy_next.c3 <= to_signed(147,9);
|
|
coefy_next.c4 <= to_signed(-3,9);
|
|
when "1111" =>
|
|
coefy_next.c1 <= to_signed(1,9);
|
|
coefy_next.c2 <= to_signed(-11,9);
|
|
coefy_next.c3 <= to_signed(148,9);
|
|
coefy_next.c4 <= to_signed(-6,9);
|
|
when others =>
|
|
coefy_next.c1 <= (others=>'0');
|
|
coefy_next.c2 <= (others=>'0');
|
|
coefy_next.c3 <= (others=>'0');
|
|
coefy_next.c4 <= (others=>'0');
|
|
end case;
|
|
|
|
|
|
end process;
|
|
|
|
next_x_delay2_next <= next_x_delay1_reg;
|
|
|
|
-- YMult - pipeline stage 3
|
|
process(pixels, coefy_reg)
|
|
variable p1 : t_pixel;
|
|
variable p2 : t_pixel;
|
|
variable p3 : t_pixel;
|
|
variable p4 : t_pixel;
|
|
begin
|
|
p1 := pixels(pixel4x4_idx(0,0));
|
|
p2 := pixels(pixel4x4_idx(0,1));
|
|
p3 := pixels(pixel4x4_idx(0,2));
|
|
p4 := pixels(pixel4x4_idx(0,3));
|
|
|
|
-- dsp blocks 9x9 multipliers
|
|
-- 3 per block -> 4 blocks
|
|
ry1_next <= signed('0'&p1.red)*coefy_reg.c1;
|
|
ry2_next <= signed('0'&p2.red)*coefy_reg.c2;
|
|
ry3_next <= signed('0'&p3.red)*coefy_reg.c3;
|
|
ry4_next <= signed('0'&p4.red)*coefy_reg.c4;
|
|
|
|
gy1_next <= signed('0'&p1.green)*coefy_reg.c1;
|
|
gy2_next <= signed('0'&p2.green)*coefy_reg.c2;
|
|
gy3_next <= signed('0'&p3.green)*coefy_reg.c3;
|
|
gy4_next <= signed('0'&p4.green)*coefy_reg.c4;
|
|
|
|
by1_next <= signed('0'&p1.blue)*coefy_reg.c1;
|
|
by2_next <= signed('0'&p2.blue)*coefy_reg.c2;
|
|
by3_next <= signed('0'&p3.blue)*coefy_reg.c3;
|
|
by4_next <= signed('0'&p4.blue)*coefy_reg.c4;
|
|
end process;
|
|
|
|
next_x_delay3_next <= next_x_delay2_reg;
|
|
coefx3_next <= coefx_reg;
|
|
|
|
-- X pixels - pipeline stage 4
|
|
process(
|
|
pixel_rx1_reg,pixel_rx2_reg,pixel_rx3_reg,pixel_rx4_reg,
|
|
pixel_gx1_reg,pixel_gx2_reg,pixel_gx3_reg,pixel_gx4_reg,
|
|
pixel_bx1_reg,pixel_bx2_reg,pixel_bx3_reg,pixel_bx4_reg,
|
|
ry1_reg,ry2_reg,ry3_reg,ry4_reg,
|
|
gy1_reg,gy2_reg,gy3_reg,gy4_reg,
|
|
by1_reg,by2_reg,by3_reg,by4_reg,
|
|
next_x_delay3_reg
|
|
)
|
|
variable ry_sum : signed (17 downto 0);
|
|
variable gy_sum : signed (17 downto 0);
|
|
variable by_sum : signed (17 downto 0);
|
|
begin
|
|
pixel_rx1_next <= pixel_rx1_reg;
|
|
pixel_rx2_next <= pixel_rx2_reg;
|
|
pixel_rx3_next <= pixel_rx3_reg;
|
|
pixel_rx4_next <= pixel_rx4_reg;
|
|
|
|
pixel_gx1_next <= pixel_gx1_reg;
|
|
pixel_gx2_next <= pixel_gx2_reg;
|
|
pixel_gx3_next <= pixel_gx3_reg;
|
|
pixel_gx4_next <= pixel_gx4_reg;
|
|
|
|
pixel_bx1_next <= pixel_bx1_reg;
|
|
pixel_bx2_next <= pixel_bx2_reg;
|
|
pixel_bx3_next <= pixel_bx3_reg;
|
|
pixel_bx4_next <= pixel_bx4_reg;
|
|
|
|
if (next_x_delay3_reg='1') then
|
|
-- ry_sum := ry1_reg+ry2_reg+ry3_reg+ry4_reg;
|
|
-- pixel_rx1_next <= ry_sum(17)&ry_sum(15 downto 8);
|
|
-- pixel_rx2_next <= pixel_rx1_reg;
|
|
-- pixel_rx3_next <= pixel_rx2_reg;
|
|
-- pixel_rx4_next <= pixel_rx3_reg;
|
|
--
|
|
-- gy_sum := gy1_reg+gy2_reg+gy3_reg+gy4_reg;
|
|
-- pixel_gx1_next <= gy_sum(17)&gy_sum(15 downto 8);
|
|
-- pixel_gx2_next <= pixel_gx1_reg;
|
|
-- pixel_gx3_next <= pixel_gx2_reg;
|
|
-- pixel_gx4_next <= pixel_gx3_reg;
|
|
--
|
|
-- by_sum := by1_reg+by2_reg+by3_reg+by4_reg;
|
|
-- pixel_bx1_next <= by_sum(17)&by_sum(15 downto 8);
|
|
-- pixel_bx2_next <= pixel_bx1_reg;
|
|
-- pixel_bx3_next <= pixel_bx2_reg;
|
|
-- pixel_bx4_next <= pixel_bx3_reg;
|
|
|
|
ry_sum := ry1_reg+ry2_reg+ry3_reg+ry4_reg;
|
|
pixel_rx4_next <= ry_sum(17)&ry_sum(15 downto 8);
|
|
pixel_rx3_next <= pixel_rx4_reg;
|
|
pixel_rx2_next <= pixel_rx3_reg;
|
|
pixel_rx1_next <= pixel_rx2_reg;
|
|
|
|
gy_sum := gy1_reg+gy2_reg+gy3_reg+gy4_reg;
|
|
pixel_gx4_next <= gy_sum(17)&gy_sum(15 downto 8);
|
|
pixel_gx3_next <= pixel_gx4_reg;
|
|
pixel_gx2_next <= pixel_gx3_reg;
|
|
pixel_gx1_next <= pixel_gx2_reg;
|
|
|
|
by_sum := by1_reg+by2_reg+by3_reg+by4_reg;
|
|
pixel_bx4_next <= by_sum(17)&by_sum(15 downto 8);
|
|
pixel_bx3_next <= pixel_bx4_reg;
|
|
pixel_bx2_next <= pixel_bx3_reg;
|
|
pixel_bx1_next <= pixel_bx2_reg;
|
|
end if;
|
|
end process;
|
|
|
|
coefx4_next <= coefx3_reg;
|
|
|
|
-- X mult - pipeline stage 5
|
|
process(
|
|
pixel_rx1_reg,pixel_rx2_reg,pixel_rx3_reg,pixel_rx4_reg,
|
|
pixel_gx1_reg,pixel_gx2_reg,pixel_gx3_reg,pixel_gx4_reg,
|
|
pixel_bx1_reg,pixel_bx2_reg,pixel_bx3_reg,pixel_bx4_reg,
|
|
coefx4_reg)
|
|
begin
|
|
-- dsp blocks 9x9 multipliers
|
|
-- 3 per block -> 4 blocks
|
|
rx1_next <= pixel_rx1_reg*coefx4_reg.c1;
|
|
rx2_next <= pixel_rx2_reg*coefx4_reg.c2;
|
|
rx3_next <= pixel_rx3_reg*coefx4_reg.c3;
|
|
rx4_next <= pixel_rx4_reg*coefx4_reg.c4;
|
|
|
|
gx1_next <= pixel_gx1_reg*coefx4_reg.c1;
|
|
gx2_next <= pixel_gx2_reg*coefx4_reg.c2;
|
|
gx3_next <= pixel_gx3_reg*coefx4_reg.c3;
|
|
gx4_next <= pixel_gx4_reg*coefx4_reg.c4;
|
|
|
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bx1_next <= pixel_bx1_reg*coefx4_reg.c1;
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bx2_next <= pixel_bx2_reg*coefx4_reg.c2;
|
|
bx3_next <= pixel_bx3_reg*coefx4_reg.c3;
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|
bx4_next <= pixel_bx4_reg*coefx4_reg.c4;
|
|
end process;
|
|
|
|
|
|
-- Pixel scaling computation - pipeline stage 6
|
|
-- Compute output
|
|
-- (p1*A1 + p2*A2 + p3*A3 + p4*A4)/65536
|
|
process(
|
|
rx1_reg,rx2_reg,rx3_reg,rx4_reg,
|
|
gx1_reg,gx2_reg,gx3_reg,gx4_reg,
|
|
bx1_reg,bx2_reg,bx3_reg,bx4_reg)
|
|
variable sum_r : signed(17 downto 0);
|
|
variable sum_g : signed(17 downto 0);
|
|
variable sum_b : signed(17 downto 0);
|
|
begin
|
|
sum_r := (rx1_reg+rx2_reg)+(rx3_reg+rx4_reg);
|
|
sum_g := (gx1_reg+gx2_reg)+(gx3_reg+gx4_reg);
|
|
sum_b := (bx1_reg+bx2_reg)+(bx3_reg+bx4_reg);
|
|
|
|
if (sum_r(17)='1') then
|
|
sum_r := (others=>'0');
|
|
elsif (sum_r(15) or sum_r(14))='1' then
|
|
sum_r := to_signed(16383,18);
|
|
end if;
|
|
if (sum_g(17)='1') then
|
|
sum_g := (others=>'0');
|
|
elsif (sum_g(15) or sum_g(14))='1' then
|
|
sum_g := to_signed(16383,18);
|
|
end if;
|
|
if (sum_b(17)='1') then
|
|
sum_b := (others=>'0');
|
|
elsif (sum_b(15) or sum_b(14))='1' then
|
|
sum_b := to_signed(16383,18);
|
|
end if;
|
|
r_next <= std_logic_vector(sum_r(13 downto 6));
|
|
g_next <= std_logic_vector(sum_g(13 downto 6));
|
|
b_next <= std_logic_vector(sum_b(13 downto 6));
|
|
end process;
|
|
|
|
-- outputnext_x_size
|
|
r<=r_reg;
|
|
g<=g_reg;
|
|
b<=b_reg;
|
|
hsync<=hsync_reg(6); -- TODO: why 6 and not 5?
|
|
vsync<=vsync_reg(6);
|
|
blank<=blank_reg(6);
|
|
|
|
next_x_size <= std_logic_vector(param_xaddrskip_reg);
|
|
|
|
END vhdl;
|
|
|
|
-- h_pixels_across <= 720 - 1;
|
|
-- h_sync_on <= 732 - 1;
|
|
-- h_sync_off <= 795 - 1;
|
|
-- h_end_count <= 864 - 1;
|
|
-- v_pixels_down <= 576 - 1;
|
|
-- v_sync_on <= 581 - 1;
|
|
-- v_sync_off <= 586 - 1;
|
|
-- v_end_count <= 625 - 1;
|
|
|
|
-- --PAL
|
|
-- h_pixels_across <= 1280 - 1;
|
|
-- h_sync_on <= 1720 - 1;
|
|
-- h_sync_off <= 1760 - 1;
|
|
-- h_end_count <= 1980 - 1;
|
|
-- v_pixels_down <= 720 - 1;
|
|
-- v_sync_on <= 725 - 1;
|
|
-- v_sync_off <= 730 - 1;
|
|
-- v_end_count <= 750 - 1;
|
|
|
|
|
|
|