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Revision 960

Added by markw almost 6 years ago

Experimental sid support

View differences:

common/a8core/address_decoder.vhdl
GENERIC
(
low_memory : integer := 0; -- if 0, we assume 8MB SDRAM, if 1, we assume 1MB 'SDRAM', if 2 we assume 512KB 'SDRAM'.
stereo : integer := 1;
system : integer := 0; -- 0=Atari XL/XE, 10=Atari5200 (space left for more systems)
--sdram_start_bank : integer := 0 -- 0=sdram only, 5=512k ram. (2^n*16)
internal_ram : integer := 0 -- must be power of 2...
......
CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
PIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
......
-- these all take 1 cycle, so fine to leave device selected in general
GTIA_WR_ENABLE : OUT STD_LOGIC;
POKEY_WR_ENABLE : OUT STD_LOGIC;
POKEY2_WR_ENABLE : OUT STD_LOGIC;
ANTIC_WR_ENABLE : OUT STD_LOGIC;
PIA_WR_ENABLE : OUT STD_LOGIC;
PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
......
pbi_mpd_n,
-- input data from n sources
GTIA_DATA,POKEY_DATA,POKEY2_DATA,PIA_DATA,ANTIC_DATA,PBI_DATA,ROM_DATA,RAM_DATA,SDRAM_DATA,
CACHE_GTIA_DATA,CACHE_POKEY_DATA,CACHE_POKEY2_DATA,CACHE_ANTIC_DATA,
GTIA_DATA,POKEY_DATA,PIA_DATA,ANTIC_DATA,PBI_DATA,ROM_DATA,RAM_DATA,SDRAM_DATA,
CACHE_GTIA_DATA,CACHE_POKEY_DATA,CACHE_ANTIC_DATA,
LAST_BUS_REG,
-- input data from n sources complete?
......
GTIA_WR_ENABLE <= '0';
POKEY_WR_ENABLE <= '0';
POKEY2_WR_ENABLE <= '0';
ANTIC_WR_ENABLE <= '0';
PIA_WR_ENABLE <= '0';
PIA_RD_ENABLE <= '0';
......
-- POKEY
when X"D2" =>
if (stereo=0 or addr_next(4) = '0') then
POKEY_WR_ENABLE <= write_enable_next;
MEMORY_DATA_INT(7 downto 0) <= POKEY_DATA;
MEMORY_DATA_INT(15 downto 8) <= CACHE_POKEY_DATA;
else
POKEY2_WR_ENABLE <= write_enable_next;
MEMORY_DATA_INT(7 downto 0) <= POKEY2_DATA;
MEMORY_DATA_INT(15 downto 8) <= CACHE_POKEY2_DATA;
end if;
POKEY_WR_ENABLE <= write_enable_next;
MEMORY_DATA_INT(7 downto 0) <= POKEY_DATA;
MEMORY_DATA_INT(15 downto 8) <= CACHE_POKEY_DATA;
request_complete <= '1';
sdram_chip_select <= '0';
ram_chip_select <= '0';
common/a8core/atari5200core.vhd
GTIA_DATA => GTIA_DO,
CACHE_GTIA_DATA => CACHE_GTIA_DO,
PIA_DATA => (others=>'0'),
POKEY2_DATA => (others=>'0'),
CACHE_POKEY2_DATA => (others=>'0'),
POKEY_DATA => POKEY_DO,
CACHE_POKEY_DATA => CACHE_POKEY_DO,
PORTB => (others=>'0'),
......
MEMORY_READY_CPU => MEMORY_READY_CPU,
GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
POKEY2_WR_ENABLE => open,
ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
PIA_WR_ENABLE => open,
PIA_RD_ENABLE => open,
common/a8core/atari800core.vhd
palette : integer :=0; -- 0:gtia colour on VIDEO_B, 1:on
low_memory : integer := 0; -- 0:8MB memory map, 1:1MB memory map
stereo : integer := 1;
sid : integer := 0; -- 0(none),1(on, only when stereo enabled too)
covox : integer := 1;
internal_ram : integer := 0;
freezer_debug : integer := 0 --trigger nmi + freezer on addr/data match
......
-- POKEY
SIGNAL POKEY_IRQ : STD_LOGIC;
SIGNAL POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CACHE_POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL POKEY_WRITE_ENABLE : STD_LOGIC;
SIGNAL POKEY1_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CACHE_POKEY1_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL POKEY1_WRITE_ENABLE : STD_LOGIC;
signal POKEY1_CHANNEL0 : std_logic_vector(3 downto 0);
signal POKEY1_CHANNEL1 : std_logic_vector(3 downto 0);
signal POKEY1_CHANNEL2 : std_logic_vector(3 downto 0);
......
signal POKEY2_CHANNEL2 : std_logic_vector(3 downto 0);
signal POKEY2_CHANNEL3 : std_logic_vector(3 downto 0);
SIGNAL POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CACHE_POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL POKEY_WRITE_ENABLE : STD_LOGIC;
-- COVOX (after market DAC)
signal covox_write_enable : std_logic;
signal covox_channel0 : std_logic_vector(7 downto 0);
......
signal freezer_state : std_logic_vector(2 downto 0);
signal freezer_trigger_nmi_n : std_logic;
-- sid (Verilog)
signal enable_sid : std_logic;
SIGNAL SID1_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SID2_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SID1_WRITE_ENABLE : std_logic;
SIGNAL SID2_WRITE_ENABLE : std_logic;
SIGNAL SID1_AUDIO : std_logic_vector(7 downto 0);
SIGNAL SID2_AUDIO : std_logic_vector(7 downto 0);
component sid8580 IS
PORT
(
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
CE_1M : IN STD_LOGIC;
WE : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(4 downto 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
POT_X : IN STD_LOGIC_VECTOR(7 downto 0);
POT_Y : IN STD_LOGIC_VECTOR(7 downto 0);
EXTFILTER_EN : IN STD_LOGIC;
AUDIO_DATA : OUT STD_LOGIC_VECTOR(17 downto 0)
);
END component;
BEGIN
PBI_WIDTH_8bit_ACCESS <= WIDTH_8bit_access;
......
CHANNEL_L_3 => POKEY1_CHANNEL3,
COVOX_CHANNEL_L_0 => covox_channel0,
COVOX_CHANNEL_L_1 => covox_channel1,
SID_CHANNEL_L_0 => sid1_audio,
CHANNEL_R_0 => POKEY2_CHANNEL0,
CHANNEL_R_1 => POKEY2_CHANNEL1,
CHANNEL_R_2 => POKEY2_CHANNEL2,
CHANNEL_R_3 => POKEY2_CHANNEL3,
COVOX_CHANNEL_R_0 => covox_channel2,
COVOX_CHANNEL_R_1 => covox_channel3,
SID_CHANNEL_R_0 => sid2_audio,
VOLUME_OUT_L => AUDIO_L,
VOLUME_OUT_R => AUDIO_R);
......
POKEY2_CHANNEL3 <= POKEY1_CHANNEL3;
end generate;
--todo: other id type (need to ask permission)
gen_sid1 : if sid=1 generate
sidenable : entity work.enable_divider
GENERIC MAP(
COUNT => cycle_length
)
PORT MAP(
CLK => CLK,
RESET_N => RESET_N,
ENABLE_IN => '1',
ENABLE_OUT => ENABLE_SID
);
sid1 : sid8580
PORT MAP(
RESET => NOT(RESET_N),
CLK => CLK,
CE_1M => ENABLE_SID, --1MHz
WE => SID1_WRITE_ENABLE,
ADDR => PBI_ADDR_INT(4 downto 0),
DATA_IN => WRITE_DATA(7 downto 0),
DATA_OUT => SID1_DO,
POT_X => (others=>'0'),
POT_Y => (others=>'0'),
EXTFILTER_EN => '0',
AUDIO_DATA(17 downto 10) => sid1_audio,
AUDIO_DATA(9 downto 0) => open
);
sid2 : sid8580
PORT MAP(
RESET => NOT(RESET_N),
CLK => CLK,
CE_1M => ENABLE_SID, --1MHz
WE => SID2_WRITE_ENABLE,
ADDR => PBI_ADDR_INT(4 downto 0),
DATA_IN => WRITE_DATA(7 downto 0),
DATA_OUT => SID2_DO,
POT_X => (others=>'0'),
POT_Y => (others=>'0'),
EXTFILTER_EN => '0',
AUDIO_DATA(17 downto 10) => sid2_audio,
AUDIO_DATA(9 downto 0) => open
);
process(pbi_addr_int, pokey1_do, pokey2_do, pokey_write_enable, pbi_addr_int)
begin
POKEY1_WRITE_ENABLE <= '0';
POKEY2_WRITE_ENABLE <= '0';
SID1_WRITE_ENABLE <= '0';
SID2_WRITE_ENABLE <= '0';
POKEY_DO <= (others=>'0');
CACHE_POKEY_DO <= (others=>'0');
case pbi_addr_int(6 downto 4) is
when "000"|"010" =>
POKEY1_WRITE_ENABLE <= POKEY_WRITE_ENABLE;
POKEY_DO <= POKEY1_DO;
CACHE_POKEY_DO <= CACHE_POKEY1_DO;
when "001"|"011" =>
POKEY2_WRITE_ENABLE <= POKEY_WRITE_ENABLE;
POKEY_DO <= POKEY2_DO;
CACHE_POKEY_DO <= CACHE_POKEY2_DO;
when "100"|"101" =>
SID1_WRITE_ENABLE <= POKEY_WRITE_ENABLE;
POKEY_DO <= SID1_DO;
-- TODO freeze
when "110"|"111" =>
SID2_WRITE_ENABLE <= POKEY_WRITE_ENABLE;
POKEY_DO <= SID2_DO;
-- TODO freeze
end case;
end process;
end generate;
gen_sid1only : if sid=0 generate
sid1_audio <= (others=>'0');
sid2_audio <= (others=>'0');
process(pbi_addr_int, pokey1_do, pokey2_do, pokey_write_enable, pbi_addr_int)
begin
POKEY1_WRITE_ENABLE <= '0';
POKEY2_WRITE_ENABLE <= '0';
POKEY_DO <= (others=>'0');
CACHE_POKEY_DO <= (others=>'0');
if (stereo = 1) then
if (pbi_addr_int(4)='0') then
POKEY1_WRITE_ENABLE <= POKEY_WRITE_ENABLE;
POKEY_DO <= POKEY1_DO;
CACHE_POKEY_DO <= CACHE_POKEY1_DO;
else
POKEY2_WRITE_ENABLE <= POKEY_WRITE_ENABLE;
POKEY_DO <= POKEY2_DO;
CACHE_POKEY_DO <= CACHE_POKEY2_DO;
end if;
else
POKEY_DO <= POKEY1_DO;
POKEY1_WRITE_ENABLE <= POKEY_WRITE_ENABLE;
POKEY2_WRITE_ENABLE <= '0';
end if;
end process;
end generate;
pia1 : entity work.pia
PORT MAP(CLK => CLK,
EN => PIA_READ_ENABLE,
......
PORTB_OUT => PORTB_OUT_INT);
mmu1 : entity work.address_decoder
GENERIC MAP(low_memory => low_memory, stereo => stereo, internal_ram => internal_ram)
GENERIC MAP(low_memory => low_memory, internal_ram => internal_ram)
PORT MAP(CLK => CLK,
CPU_FETCH => CPU_FETCH,
CPU_WRITE_N => R_W_N,
......
GTIA_DATA => GTIA_DO,
CACHE_GTIA_DATA => CACHE_GTIA_DO,
PIA_DATA => PIA_DO,
POKEY2_DATA => POKEY2_DO,
CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
POKEY_DATA => POKEY_DO,
CACHE_POKEY_DATA => CACHE_POKEY_DO,
PORTB => PORTB_OPTIONS,
......
MEMORY_READY_CPU => MEMORY_READY_CPU,
GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
PIA_WR_ENABLE => PIA_WRITE_ENABLE,
PIA_RD_ENABLE => PIA_READ_ENABLE,
......
pokey1 : entity work.pokey
PORT MAP(CLK => CLK,
ENABLE_179 => ANTIC_ENABLE_179,
WR_EN => POKEY_WRITE_ENABLE,
WR_EN => POKEY1_WRITE_ENABLE,
RESET_N => RESET_N,
SIO_IN1 => SIO_RXD,
SIO_IN2 => '1',
......
CHANNEL_1_OUT => POKEY1_CHANNEL1,
CHANNEL_2_OUT => POKEY1_CHANNEL2,
CHANNEL_3_OUT => POKEY1_CHANNEL3,
DATA_OUT => POKEY_DO,
DATA_OUT => POKEY1_DO,
keyboard_scan => KEYBOARD_SCAN);
CONSOL_IN <= '1'&CONSOL_OPTION&CONSOL_SELECT&CONSOL_START;
......
CLK => CLK,
ADDR => PBI_ADDR_INT(3 downto 0),
DATA_IN => WRITE_DATA(7 downto 0),
WR_EN => POKEY_WRITE_ENABLE,
DATA_OUT => CACHE_POKEY_DO
WR_EN => POKEY1_WRITE_ENABLE,
DATA_OUT => CACHE_POKEY1_DO
);
pokey2_mirror : entity work.reg_file
common/a8core/pokey_mixer.vhdl
COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
SID_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
VOLUME_OUT_NEXT : OUT STD_LOGIC_vector(15 downto 0)
);
......
END PROCESS;
-- next state
process (channel_0,channel_1,channel_2,channel_3,covox_CHANNEL_0,covox_channel_1,gtia_sound,sio_audio)
process (channel_0,channel_1,channel_2,channel_3,covox_CHANNEL_0,covox_channel_1,sid_channel_0,gtia_sound,sio_audio)
variable channel0_en_long : unsigned(10 downto 0);
variable channel1_en_long : unsigned(10 downto 0);
variable channel2_en_long : unsigned(10 downto 0);
......
variable sio_audio_long : unsigned(10 downto 0);
variable covox_0_long : unsigned(10 downto 0);
variable covox_1_long : unsigned(10 downto 0);
variable sid_0_long : unsigned(10 downto 0);
variable volume_int_sum : unsigned(10 downto 0);
begin
......
sio_audio_long := (others=>'0');
covox_0_long := (others=>'0');
covox_1_long := (others=>'0');
sid_0_long := (others=>'0');
channel0_en_long(7 downto 4) := unsigned(channel_0);
channel1_en_long(7 downto 4) := unsigned(channel_1);
......
sio_audio_long(7 downto 0) := unsigned(sio_audio);
covox_0_long(7 downto 0) := unsigned(covox_channel_0);
covox_1_long(7 downto 0) := unsigned(covox_channel_1);
sid_0_long(7 downto 0) := unsigned(sid_channel_0);
volume_int_sum := ((channel0_en_long + channel1_en_long) + (channel2_en_long + channel3_en_long)) + ((gtia_sound_long + sio_audio_long) + (covox_0_long + covox_1_long));
volume_int_sum := ((channel0_en_long + channel1_en_long) + (channel2_en_long + channel3_en_long)) + ((gtia_sound_long + sio_audio_long) + (covox_0_long + covox_1_long) + (sid_0_long + sid_0_long));
volume_sum_next(9 downto 0) <= std_logic_vector(volume_int_sum(9 downto 0)) or volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10);
common/a8core/pokey_mixer_mux.vhdl
CHANNEL_L_3 : IN STD_LOGIC_VECTOR(3 downto 0);
COVOX_CHANNEL_L_0 : IN STD_LOGIC_VECTOR(7 downto 0);
COVOX_CHANNEL_L_1 : IN STD_LOGIC_VECTOR(7 downto 0);
SID_CHANNEL_L_0 : IN STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
CHANNEL_R_0 : IN STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_R_1 : IN STD_LOGIC_VECTOR(3 downto 0);
......
CHANNEL_R_3 : IN STD_LOGIC_VECTOR(3 downto 0);
COVOX_CHANNEL_R_0 : IN STD_LOGIC_VECTOR(7 downto 0);
COVOX_CHANNEL_R_1 : IN STD_LOGIC_VECTOR(7 downto 0);
SID_CHANNEL_R_0 : IN STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
GTIA_SOUND : IN STD_LOGIC;
SIO_AUDIO : IN STD_LOGIC_VECTOR(7 downto 0);
......
signal CHANNEL_3_SEL : STD_LOGIC_VECTOR(3 downto 0);
signal COVOX_CHANNEL_0_SEL : STD_LOGIC_VECTOR(7 downto 0);
signal COVOX_CHANNEL_1_SEL : STD_LOGIC_VECTOR(7 downto 0);
signal SID_CHANNEL_0_SEL : STD_LOGIC_VECTOR(7 downto 0);
signal VOLUME_OUT_NEXT : STD_LOGIC_VECTOR(15 downto 0);
......
-- mux input
PROCESS(
CHANNEL_L_0,CHANNEL_L_1,CHANNEL_L_2,CHANNEL_L_3,COVOX_CHANNEL_L_0,COVOX_CHANNEL_L_1,
CHANNEL_R_0,CHANNEL_R_1,CHANNEL_R_2,CHANNEL_R_3,COVOX_CHANNEL_R_0,COVOX_CHANNEL_R_1,
CHANNEL_L_0,CHANNEL_L_1,CHANNEL_L_2,CHANNEL_L_3,COVOX_CHANNEL_L_0,COVOX_CHANNEL_L_1,SID_CHANNEL_L_0,
CHANNEL_R_0,CHANNEL_R_1,CHANNEL_R_2,CHANNEL_R_3,COVOX_CHANNEL_R_0,COVOX_CHANNEL_R_1,SID_CHANNEL_R_0,
LEFT_CHANNEL_REG)
BEGIN
CHANNEL_0_SEL <= (OTHERS=>'0');
......
COVOX_CHANNEL_0_SEL <= (OTHERS=>'0');
COVOX_CHANNEL_1_SEL <= (OTHERS=>'0');
SID_CHANNEL_0_SEL <= (OTHERS=>'0');
IF (LEFT_CHANNEL_REG = '1') THEN
CHANNEL_0_SEL <= CHANNEL_L_0;
CHANNEL_1_SEL <= CHANNEL_L_1;
......
COVOX_CHANNEL_0_SEL <= COVOX_CHANNEL_L_0;
COVOX_CHANNEL_1_SEL <= COVOX_CHANNEL_L_1;
SID_CHANNEL_0_SEL <= SID_CHANNEL_L_0;
ELSE
CHANNEL_0_SEL <= CHANNEL_R_0;
CHANNEL_1_SEL <= CHANNEL_R_1;
......
COVOX_CHANNEL_0_SEL <= COVOX_CHANNEL_R_0;
COVOX_CHANNEL_1_SEL <= COVOX_CHANNEL_R_1;
SID_CHANNEL_0_SEL <= SID_CHANNEL_R_0;
END IF;
END PROCESS;
......
COVOX_CHANNEL_0 => COVOX_CHANNEL_0_SEL,
COVOX_CHANNEL_1 => COVOX_CHANNEL_1_SEL,
SID_CHANNEL_0 => SID_CHANNEL_0_SEL,
GTIA_SOUND => GTIA_SOUND,
SIO_AUDIO => SIO_AUDIO,
common/a8core/sid8580/sid.qip
set_global_assignment -name VERILOG_FILE sid8580/sid8580.v
set_global_assignment -name VERILOG_FILE sid8580/sid_voice.v
set_global_assignment -name VERILOG_FILE sid8580/sid_tables.v
set_global_assignment -name VERILOG_FILE sid8580/sid_filters.v
set_global_assignment -name VERILOG_FILE sid8580/sid_envelope.v
common/a8core/sid8580/sid8580.v
module sid8580
(
input reset,
input clk,
input ce_1m,
input we,
input [4:0] addr,
input [7:0] data_in,
output [ 7:0] data_out,
input [7:0] pot_x,
input [7:0] pot_y,
input extfilter_en,
output [17:0] audio_data
);
// Internal Signals
reg [7:0] Voice_1_Freq_lo;
reg [7:0] Voice_1_Freq_hi;
reg [7:0] Voice_1_Pw_lo;
reg [3:0] Voice_1_Pw_hi;
reg [7:0] Voice_1_Control;
reg [7:0] Voice_1_Att_dec;
reg [7:0] Voice_1_Sus_Rel;
reg [7:0] Voice_2_Freq_lo;
reg [7:0] Voice_2_Freq_hi;
reg [7:0] Voice_2_Pw_lo;
reg [3:0] Voice_2_Pw_hi;
reg [7:0] Voice_2_Control;
reg [7:0] Voice_2_Att_dec;
reg [7:0] Voice_2_Sus_Rel;
reg [7:0] Voice_3_Freq_lo;
reg [7:0] Voice_3_Freq_hi;
reg [7:0] Voice_3_Pw_lo;
reg [3:0] Voice_3_Pw_hi;
reg [7:0] Voice_3_Control;
reg [7:0] Voice_3_Att_dec;
reg [7:0] Voice_3_Sus_Rel;
reg [7:0] Filter_Fc_lo;
reg [7:0] Filter_Fc_hi;
reg [7:0] Filter_Res_Filt;
reg [7:0] Filter_Mode_Vol;
wire [7:0] Misc_Osc3_Random;
wire [7:0] Misc_Env3;
reg [7:0] do_buf;
reg [7:0] sidrandom;
wire [11:0] voice_1;
wire [11:0] voice_2;
wire [11:0] voice_3;
wire [17:0] voice_mixed;
reg [17:0] voice_volume;
wire voice_1_PA_MSB;
wire voice_2_PA_MSB;
wire voice_3_PA_MSB;
wire [18:0] filtered_audio;
wire [17:0] unsigned_audio;
wire [18:0] unsigned_filt;
localparam DC_offset = 14'b00111111111111;
reg [7:0] _st_out[3];
reg [7:0] p_t_out[3];
reg [7:0] ps__out[3];
reg [7:0] pst_out[3];
wire [11:0] sawtooth[3];
wire [11:0] triangle[3];
// Voice 1 Instantiation
sid_voice v1
(
.clock(clk),
.ce_1m(ce_1m),
.reset(reset),
.freq_lo(Voice_1_Freq_lo),
.freq_hi(Voice_1_Freq_hi),
.pw_lo(Voice_1_Pw_lo),
.pw_hi(Voice_1_Pw_hi),
.control(Voice_1_Control),
.att_dec(Voice_1_Att_dec),
.sus_rel(Voice_1_Sus_Rel),
.osc_msb_in(voice_3_PA_MSB),
.osc_msb_out(voice_1_PA_MSB),
.signal_out(voice_1),
._st_out(_st_out[0]),
.p_t_out(p_t_out[0]),
.ps__out(ps__out[0]),
.pst_out(pst_out[0]),
.sawtooth(sawtooth[0]),
.triangle(triangle[0])
);
// Voice 2 Instantiation
sid_voice v2
(
.clock(clk),
.ce_1m(ce_1m),
.reset(reset),
.freq_lo(Voice_2_Freq_lo),
.freq_hi(Voice_2_Freq_hi),
.pw_lo(Voice_2_Pw_lo),
.pw_hi(Voice_2_Pw_hi),
.control(Voice_2_Control),
.att_dec(Voice_2_Att_dec),
.sus_rel(Voice_2_Sus_Rel),
.osc_msb_in(voice_1_PA_MSB),
.osc_msb_out(voice_2_PA_MSB),
.signal_out(voice_2),
._st_out(_st_out[1]),
.p_t_out(p_t_out[1]),
.ps__out(ps__out[1]),
.pst_out(pst_out[1]),
.sawtooth(sawtooth[1]),
.triangle(triangle[1])
);
// Voice 3 Instantiation
sid_voice v3
(
.clock(clk),
.ce_1m(ce_1m),
.reset(reset),
.freq_lo(Voice_3_Freq_lo),
.freq_hi(Voice_3_Freq_hi),
.pw_lo(Voice_3_Pw_lo),
.pw_hi(Voice_3_Pw_hi),
.control(Voice_3_Control),
.att_dec(Voice_3_Att_dec),
.sus_rel(Voice_3_Sus_Rel),
.osc_msb_in(voice_2_PA_MSB),
.osc_msb_out(voice_3_PA_MSB),
.signal_out(voice_3),
.osc_out(Misc_Osc3_Random),
.env_out(Misc_Env3),
._st_out(_st_out[2]),
.p_t_out(p_t_out[2]),
.ps__out(ps__out[2]),
.pst_out(pst_out[2]),
.sawtooth(sawtooth[2]),
.triangle(triangle[2])
);
// Filter Instantiation
sid_filters filters
(
.clk(clk),
.rst(reset),
.Fc_lo(Filter_Fc_lo),
.Fc_hi(Filter_Fc_hi),
.Res_Filt(Filter_Res_Filt),
.Mode_Vol(Filter_Mode_Vol),
.voice1(voice_1),
.voice2(voice_2),
.voice3(voice_3),
.input_valid(ce_1m),
.ext_in(12'hfff),
.sound(audio_data),
.extfilter_en(extfilter_en)
);
sid_tables sid_tables
(
.clock(clk),
.sawtooth(f_sawtooth),
.triangle(f_triangle),
._st_out(f__st_out),
.p_t_out(f_p_t_out),
.ps__out(f_ps__out),
.pst_out(f_pst_out)
);
wire [7:0] f__st_out;
wire [7:0] f_p_t_out;
wire [7:0] f_ps__out;
wire [7:0] f_pst_out;
reg [11:0] f_sawtooth;
reg [11:0] f_triangle;
always @(posedge clk) begin
reg [3:0] state;
if(~&state) state <= state + 1'd1;;
if(ce_1m) state <= 0;
case(state)
1,5,9: begin
f_sawtooth <= sawtooth[state[3:2]];
f_triangle <= triangle[state[3:2]];
end
endcase
case(state)
3,7,11: begin
_st_out[state[3:2]] <= f__st_out;
p_t_out[state[3:2]] <= f_p_t_out;
ps__out[state[3:2]] <= f_ps__out;
pst_out[state[3:2]] <= f_pst_out;
end
endcase
end
assign data_out = do_buf;
reg [7:0] last_wr;
always @(*) begin
case (addr)
5'h19: do_buf = pot_x;
5'h1a: do_buf = pot_y;
5'h1b: do_buf = Misc_Osc3_Random;
5'h1c: do_buf = Misc_Env3;
default: do_buf = last_wr;
endcase
end
// Register Decoding
always @(posedge clk) begin
if (reset) begin
Voice_1_Freq_lo <= 0;
Voice_1_Freq_hi <= 0;
Voice_1_Pw_lo <= 0;
Voice_1_Pw_hi <= 0;
Voice_1_Control <= 0;
Voice_1_Att_dec <= 0;
Voice_1_Sus_Rel <= 0;
Voice_2_Freq_lo <= 0;
Voice_2_Freq_hi <= 0;
Voice_2_Pw_lo <= 0;
Voice_2_Pw_hi <= 0;
Voice_2_Control <= 0;
Voice_2_Att_dec <= 0;
Voice_2_Sus_Rel <= 0;
Voice_3_Freq_lo <= 0;
Voice_3_Freq_hi <= 0;
Voice_3_Pw_lo <= 0;
Voice_3_Pw_hi <= 0;
Voice_3_Control <= 0;
Voice_3_Att_dec <= 0;
Voice_3_Sus_Rel <= 0;
Filter_Fc_lo <= 0;
Filter_Fc_hi <= 0;
Filter_Res_Filt <= 0;
Filter_Mode_Vol <= 0;
end
else begin
if (we) begin
last_wr <= data_in;
case (addr)
5'h00: Voice_1_Freq_lo <= data_in;
5'h01: Voice_1_Freq_hi <= data_in;
5'h02: Voice_1_Pw_lo <= data_in;
5'h03: Voice_1_Pw_hi <= data_in[3:0];
5'h04: Voice_1_Control <= data_in;
5'h05: Voice_1_Att_dec <= data_in;
5'h06: Voice_1_Sus_Rel <= data_in;
5'h07: Voice_2_Freq_lo <= data_in;
5'h08: Voice_2_Freq_hi <= data_in;
5'h09: Voice_2_Pw_lo <= data_in;
5'h0a: Voice_2_Pw_hi <= data_in[3:0];
5'h0b: Voice_2_Control <= data_in;
5'h0c: Voice_2_Att_dec <= data_in;
5'h0d: Voice_2_Sus_Rel <= data_in;
5'h0e: Voice_3_Freq_lo <= data_in;
5'h0f: Voice_3_Freq_hi <= data_in;
5'h10: Voice_3_Pw_lo <= data_in;
5'h11: Voice_3_Pw_hi <= data_in[3:0];
5'h12: Voice_3_Control <= data_in;
5'h13: Voice_3_Att_dec <= data_in;
5'h14: Voice_3_Sus_Rel <= data_in;
5'h15: Filter_Fc_lo <= data_in;
5'h16: Filter_Fc_hi <= data_in;
5'h17: Filter_Res_Filt <= data_in;
5'h18: Filter_Mode_Vol <= data_in;
endcase
end
end
end
endmodule
common/a8core/sid8580/sid_envelope.v
module sid_envelope
(
input clock,
input ce_1m,
input reset,
input gate,
input [ 7:0] att_dec,
input [ 7:0] sus_rel,
output reg [7:0] envelope
);
// Internal Signals
reg [ 1:0] state;
reg gate_edge;
reg [14:0] rate_counter;
reg [14:0] rate_period;
wire [14:0] adsrtable [0:15];
reg [ 7:0] exponential_counter;
reg [ 7:0] exponential_counter_period;
reg hold_zero;
reg envelope_pipeline;
`define ST_ATTACK 2'b00
`define ST_DEC_SUS 2'b01
`define ST_RELEASE 2'b10
assign adsrtable[4'h0] = 15'h007f;
assign adsrtable[4'h1] = 15'h3000;
assign adsrtable[4'h2] = 15'h1e00;
assign adsrtable[4'h3] = 15'h0660;
assign adsrtable[4'h4] = 15'h0182;
assign adsrtable[4'h5] = 15'h5573;
assign adsrtable[4'h6] = 15'h000e;
assign adsrtable[4'h7] = 15'h3805;
assign adsrtable[4'h8] = 15'h2424;
assign adsrtable[4'h9] = 15'h2220;
assign adsrtable[4'ha] = 15'h090c;
assign adsrtable[4'hb] = 15'h0ecd;
assign adsrtable[4'hc] = 15'h010e;
assign adsrtable[4'hd] = 15'h23f7;
assign adsrtable[4'he] = 15'h5237;
assign adsrtable[4'hf] = 15'h64a8;
// State Logic
always @(posedge clock) begin
if (reset)
state <= `ST_RELEASE;
else if(ce_1m) begin
if (gate_edge != gate)
if (gate) state <= `ST_ATTACK;
else state <= `ST_RELEASE;
if (((rate_counter == rate_period) &&
(state == `ST_ATTACK ||
(exponential_counter + 1'b1) == exponential_counter_period) &&
(!hold_zero)))
case (state)
`ST_ATTACK: if (envelope + 1'b1 == 8'hff) state <= `ST_DEC_SUS;
endcase
end
end
// Gate Switch Detection
always @(posedge clock) begin
if (reset) gate_edge <= 1'b0;
else if(ce_1m) begin
if (gate_edge != gate) gate_edge <= gate;
end
end
// Envelope
always @(posedge clock) begin
if (reset)
envelope <= 8'h00;
else if(ce_1m) begin
if (envelope_pipeline) envelope <= envelope - 1'b1;
if (((rate_counter == rate_period) &&
(state == `ST_ATTACK ||
(exponential_counter + 1'b1) == exponential_counter_period) &&
(!hold_zero)))
case (state)
`ST_ATTACK: envelope <= envelope + 1'b1;
`ST_DEC_SUS: if (envelope != {2{sus_rel[7:4]}} && exponential_counter_period == 1) envelope <= envelope - 1'b1;
`ST_RELEASE: if (exponential_counter_period == 1) envelope <= envelope - 1'b1;
endcase
end
end
// Envelope Pipeline
always @(posedge clock) begin
if (reset)
envelope_pipeline <= 1'b0;
else if(ce_1m) begin
if (gate_edge != gate)
if (gate) envelope_pipeline <= 1'b0;
if (envelope_pipeline) envelope_pipeline <= 1'b0;
if (((rate_counter == rate_period) &&
(state == `ST_ATTACK ||
(exponential_counter + 1'b1) == exponential_counter_period) &&
(!hold_zero)))
case (state)
`ST_DEC_SUS: if (envelope != {2{sus_rel[7:4]}} && exponential_counter_period != 1) envelope_pipeline <= 1'b1;
`ST_RELEASE: if(exponential_counter_period != 1) envelope_pipeline <= 1'b1;
endcase
end
end
// Exponential Counter
always @(posedge clock) begin
if (reset)
exponential_counter <= 8'h00;
else if(ce_1m) begin
if (rate_counter == rate_period) begin
exponential_counter <= exponential_counter + 1'b1;
if (state == `ST_ATTACK || (exponential_counter + 1'b1) == exponential_counter_period) exponential_counter <= 8'h00;
end
end
end
// Exponential Counter Period
always @(posedge clock) begin
if (reset) begin
hold_zero <= 1'b1;
exponential_counter_period <= 8'h00;
end
else if(ce_1m) begin
if (gate_edge != gate) if (gate) hold_zero <= 1'b0;
if ((envelope_pipeline) || ((rate_counter == rate_period) &&
(state == `ST_ATTACK ||
(exponential_counter + 1'b1) == exponential_counter_period) &&
(!hold_zero)))
begin
case (state == `ST_ATTACK ? envelope + 1'b1 : envelope - 1'b1)
8'hff: exponential_counter_period <= 8'd1;
8'h5d: exponential_counter_period <= 8'd2;
8'h36: exponential_counter_period <= 8'd4;
8'h1a: exponential_counter_period <= 8'd8;
8'h0e: exponential_counter_period <= 8'd16;
8'h06: exponential_counter_period <= 8'd30;
8'h00: begin
exponential_counter_period <= 8'd1;
hold_zero <= 1'b1;
end
endcase
end
end
end
// Rate Counter
always @(posedge clock) begin
if (reset) rate_counter <= 15'h7fff;
else if(ce_1m) begin
if (rate_counter == rate_period) rate_counter <= 15'h7fff;
else rate_counter <= {rate_counter[1] ^ rate_counter[0], rate_counter[14:1]};
end
end
// Rate Period
always @(posedge clock) begin
if (reset)
rate_period <= adsrtable[sus_rel[3:0]];
else if(ce_1m) begin
if (gate_edge != gate) begin
if (gate) rate_period <= adsrtable[att_dec[7:4]];
else rate_period <= adsrtable[sus_rel[3:0]];
end
case (state)
`ST_ATTACK: rate_period <= adsrtable[att_dec[7:4]];
`ST_DEC_SUS: rate_period <= adsrtable[att_dec[3:0]];
default: rate_period <= adsrtable[sus_rel[3:0]];
endcase
end
end
endmodule
common/a8core/sid8580/sid_filters.v
module sid_filters
(
input clk,
input rst,
input [ 7:0] Fc_lo,
input [ 7:0] Fc_hi,
input [ 7:0] Res_Filt,
input [ 7:0] Mode_Vol,
input [11:0] voice1,
input [11:0] voice2,
input [11:0] voice3,
input input_valid,
input [11:0] ext_in,
input extfilter_en,
output reg [17:0] sound
);
reg signed [17:0] Vhp;
reg signed [17:0] Vbp;
reg signed [17:0] w0;
reg signed [17:0] q;
wire [10:0] divmul[16];
assign divmul[0] = 1448;
assign divmul[1] = 1328;
assign divmul[2] = 1218;
assign divmul[3] = 1117;
assign divmul[4] = 1024;
assign divmul[5] = 939;
assign divmul[6] = 861;
assign divmul[7] = 790;
assign divmul[8] = 724;
assign divmul[9] = 664;
assign divmul[10] = 609;
assign divmul[11] = 558;
assign divmul[12] = 512;
assign divmul[13] = 470;
assign divmul[14] = 431;
assign divmul[15] = 395;
wire [35:0] mul1 = w0 * Vhp;
wire [35:0] mul2 = w0 * Vbp;
wire [35:0] mul3 = q * Vbp;
wire [35:0] mul4 = 18'd82355 * ({Fc_hi, Fc_lo[2:0]} + 1'b1);
// Filter
always @(posedge clk) begin
reg [17:0] dVbp;
reg [17:0] Vlp;
reg [17:0] dVlp;
reg [17:0] Vi;
reg [17:0] Vnf;
reg [17:0] Vf;
reg [3:0] state;
reg signed [35:0] mulr;
reg signed [17:0] mula;
reg signed [17:0] mulb;
if (rst) begin
state <= 0;
Vlp <= 0;
Vbp <= 0;
Vhp <= 0;
end
else begin
case (state)
0: if (input_valid) begin
state <= state + 1'd1;
if(!(^mulr[21:20])) sound <= mulr[20:3];
Vi <= 0;
Vnf <= 0;
end
1: begin
state <= state + 1'd1;
w0 <= {mul4[35], mul4[28:12]};
if (Res_Filt[0]) Vi <= Vi + {voice1,2'b00};
else Vnf <= Vnf + {voice1,2'b00};
end
2: begin
state <= state + 1'd1;
if (Res_Filt[1]) Vi <= Vi + {voice2,2'b00};
else Vnf <= Vnf + {voice2,2'b00};
end
3: begin
state <= state + 1'd1;
if (Res_Filt[2]) Vi <= Vi + {voice3,2'b00};
else if (!Mode_Vol[7]) Vnf <= Vnf + {voice3,2'b00};
dVbp <= {mul1[35], mul1[35:19]};
end
4: begin
state <= state + 1'd1;
if (Res_Filt[3]) Vi <= Vi + {ext_in,2'b00};
else Vnf <= Vnf + {ext_in,2'b00};
dVlp <= {mul2[35], mul2[35:19]};
Vbp <= Vbp - dVbp;
q <= divmul[Res_Filt[7:4]];
end
5: begin
state <= state + 1'd1;
Vlp <= Vlp - dVlp;
Vf <= (Mode_Vol[5]) ? Vbp : 18'd0;
end
6: begin
state <= state + 1'd1;
Vhp <= {mul3[35], mul3[26:10]} - Vlp;
if(Mode_Vol[4]) Vf <= Vf + Vlp;
end
7: begin
state <= state + 1'd1;
Vhp <= Vhp - Vi;
end
8: begin
state <= state + 1'd1;
if(Mode_Vol[6]) Vf <= Vf + Vhp;
end
9: begin
state <= state + 1'd1;
mula <= (extfilter_en) ? Vnf - Vf : Vnf + Vi;
mulb <= Mode_Vol[3:0];
end
10:begin
state <= 0;
mulr <= mula * mulb;
end
endcase
end
end
endmodule
common/a8core/sid8580/sid_tables.v
module sid_tables
(
input clock,
input [11:0] sawtooth,
input [11:0] triangle,
output reg [7:0] _st_out,
output reg [7:0] p_t_out,
output reg [7:0] ps__out,
output reg [7:0] pst_out
);
always @(posedge clock) begin
_st_out <= wave__st[sawtooth];
p_t_out <= wave_p_t[triangle[11:1]];
ps__out <= wave_ps_[sawtooth];
pst_out <= wave_pst[sawtooth];
end
//
// convert combinatorial logic to ROM (Sorgelig)
//
wire [7:0] wave__st[4096];
wire [7:0] wave_p_t[2048];
wire [7:0] wave_ps_[4096];
wire [7:0] wave_pst[4096];
generate
genvar i;
for(i = 0; i<4096; i=i+1) begin : b1 assign wave__st[i] =
(i < 'h07e) ? 8'h00 : (i < 'h080) ? 8'h03 : (i < 'h0fc) ? 8'h00 : (i < 'h100) ? 8'h07 :
(i < 'h17e) ? 8'h00 : (i < 'h180) ? 8'h03 : (i < 'h1f8) ? 8'h00 : (i < 'h1fc) ? 8'h0e :
(i < 'h200) ? 8'h0f : (i < 'h27e) ? 8'h00 : (i < 'h280) ? 8'h03 : (i < 'h2fc) ? 8'h00 :
(i < 'h300) ? 8'h07 : (i < 'h37e) ? 8'h00 : (i < 'h380) ? 8'h03 : (i < 'h3bf) ? 8'h00 :
(i < 'h3c0) ? 8'h01 : (i < 'h3f0) ? 8'h00 : (i < 'h3f8) ? 8'h1c : (i < 'h3fa) ? 8'h1e :
(i < 'h400) ? 8'h1f : (i < 'h47e) ? 8'h00 : (i < 'h480) ? 8'h03 : (i < 'h4fc) ? 8'h00 :
(i < 'h500) ? 8'h07 : (i < 'h57e) ? 8'h00 : (i < 'h580) ? 8'h03 : (i < 'h5f8) ? 8'h00 :
(i < 'h5fc) ? 8'h0e : (i < 'h5ff) ? 8'h0f : (i < 'h600) ? 8'h1f : (i < 'h67e) ? 8'h00 :
(i < 'h680) ? 8'h03 : (i < 'h6fc) ? 8'h00 : (i < 'h700) ? 8'h07 : (i < 'h77e) ? 8'h00 :
(i < 'h780) ? 8'h03 : (i < 'h7bf) ? 8'h00 : (i < 'h7c0) ? 8'h01 : (i < 'h7e0) ? 8'h00 :
(i < 'h7f0) ? 8'h38 : (i < 'h7f7) ? 8'h3c : (i < 'h7f8) ? 8'h3e : (i < 'h800) ? 8'h7f :
(i < 'h87e) ? 8'h00 : (i < 'h880) ? 8'h03 : (i < 'h8fc) ? 8'h00 : (i < 'h900) ? 8'h07 :
(i < 'h97e) ? 8'h00 : (i < 'h980) ? 8'h03 : (i < 'h9f8) ? 8'h00 : (i < 'h9fc) ? 8'h0e :
(i < 'ha00) ? 8'h0f : (i < 'ha7e) ? 8'h00 : (i < 'ha80) ? 8'h03 : (i < 'hafc) ? 8'h00 :
(i < 'hb00) ? 8'h07 : (i < 'hb7e) ? 8'h00 : (i < 'hb80) ? 8'h03 : (i < 'hbbf) ? 8'h00 :
(i < 'hbc0) ? 8'h01 : (i < 'hbf0) ? 8'h00 : (i < 'hbf8) ? 8'h1c : (i < 'hbfa) ? 8'h1e :
(i < 'hbfe) ? 8'h1f : (i < 'hc00) ? 8'h3f : (i < 'hc7e) ? 8'h00 : (i < 'hc80) ? 8'h03 :
(i < 'hcfc) ? 8'h00 : (i < 'hd00) ? 8'h07 : (i < 'hd7e) ? 8'h00 : (i < 'hd80) ? 8'h03 :
(i < 'hdbf) ? 8'h00 : (i < 'hdc0) ? 8'h01 : (i < 'hdf8) ? 8'h00 : (i < 'hdfc) ? 8'h0e :
(i < 'hdfe) ? 8'h0f : (i < 'he00) ? 8'h1f : (i < 'he7c) ? 8'h00 : (i < 'he7d) ? 8'h80 :
(i < 'he7e) ? 8'h00 : (i < 'he80) ? 8'h83 : (i < 'hefc) ? 8'h80 : (i < 'heff) ? 8'h87 :
(i < 'hf00) ? 8'h8f : (i < 'hf01) ? 8'hc0 : (i < 'hf03) ? 8'he0 : (i < 'hf05) ? 8'hc0 :
(i < 'hf09) ? 8'he0 : (i < 'hf11) ? 8'hc0 : (i < 'hf13) ? 8'he0 : (i < 'hf18) ? 8'hc0 :
(i < 'hf19) ? 8'he0 : (i < 'hf21) ? 8'hc0 : (i < 'hf23) ? 8'he0 : (i < 'hf25) ? 8'hc0 :
(i < 'hf2b) ? 8'he0 : (i < 'hf2c) ? 8'hc0 : (i < 'hf2d) ? 8'he0 : (i < 'hf2e) ? 8'hc0 :
(i < 'hf7e) ? 8'he0 : (i < 'hf80) ? 8'he3 : (i < 'hfbf) ? 8'hf0 : (i < 'hfc0) ? 8'hf1 :
(i < 'hfe0) ? 8'hf8 : (i < 'hff0) ? 8'hfc : (i < 'hff8) ? 8'hfe : 8'hff;
end
for(i = 0; i<2048; i=i+1) begin : b2 assign wave_p_t[i] =
(i < 'h0ff) ? 8'h00 : (i < 'h100) ? 8'h07 : (i < 'h1fb) ? 8'h00 : (i < 'h1fc) ? 8'h1c :
(i < 'h1fd) ? 8'h00 : (i < 'h1fe) ? 8'h3c : (i < 'h200) ? 8'h3f : (i < 'h2fd) ? 8'h00 :
(i < 'h2fe) ? 8'h0c : (i < 'h2ff) ? 8'h5e : (i < 'h300) ? 8'h5f : (i < 'h377) ? 8'h00 :
(i < 'h378) ? 8'h40 : (i < 'h37b) ? 8'h00 : (i < 'h37d) ? 8'h40 : (i < 'h37f) ? 8'h60 :
(i < 'h380) ? 8'h6f : (i < 'h39f) ? 8'h00 : (i < 'h3a0) ? 8'h40 : (i < 'h3ae) ? 8'h00 :
(i < 'h3b0) ? 8'h40 : (i < 'h3b3) ? 8'h00 : (i < 'h3b7) ? 8'h40 : (i < 'h3b8) ? 8'h60 :
(i < 'h3ba) ? 8'h40 : (i < 'h3be) ? 8'h60 : (i < 'h3bf) ? 8'h70 : (i < 'h3c0) ? 8'h77 :
(i < 'h3c5) ? 8'h00 : (i < 'h3cd) ? 8'h40 : (i < 'h3d0) ? 8'h60 : (i < 'h3d3) ? 8'h40 :
(i < 'h3d7) ? 8'h60 : (i < 'h3d8) ? 8'h70 : (i < 'h3db) ? 8'h60 : (i < 'h3de) ? 8'h70 :
(i < 'h3df) ? 8'h78 : (i < 'h3e0) ? 8'h7b : (i < 'h3e3) ? 8'h60 : (i < 'h3e4) ? 8'h70 :
(i < 'h3e5) ? 8'h60 : (i < 'h3eb) ? 8'h70 : (i < 'h3ef) ? 8'h78 : (i < 'h3f0) ? 8'h7c :
(i < 'h3f3) ? 8'h78 : (i < 'h3f4) ? 8'h7c : (i < 'h3f5) ? 8'h78 : (i < 'h3f7) ? 8'h7c :
(i < 'h3f8) ? 8'h7e : (i < 'h3f9) ? 8'h7c : (i < 'h3fb) ? 8'h7e : (i < 'h400) ? 8'h7f :
(i < 'h47f) ? 8'h00 : (i < 'h480) ? 8'h80 : (i < 'h4bd) ? 8'h00 : (i < 'h4c0) ? 8'h80 :
(i < 'h4cf) ? 8'h00 : (i < 'h4d0) ? 8'h80 : (i < 'h4d7) ? 8'h00 : (i < 'h4d8) ? 8'h80 :
(i < 'h4da) ? 8'h00 : (i < 'h4e0) ? 8'h80 : (i < 'h4e3) ? 8'h00 : (i < 'h4fe) ? 8'h80 :
(i < 'h4ff) ? 8'h8e : (i < 'h500) ? 8'h9f : (i < 'h51f) ? 8'h00 : (i < 'h520) ? 8'h80 :
(i < 'h52b) ? 8'h00 : (i < 'h52c) ? 8'h80 : (i < 'h52d) ? 8'h00 : (i < 'h530) ? 8'h80 :
(i < 'h532) ? 8'h00 : (i < 'h540) ? 8'h80 : (i < 'h543) ? 8'h00 : (i < 'h544) ? 8'h80 :
(i < 'h545) ? 8'h00 : (i < 'h57f) ? 8'h80 : (i < 'h580) ? 8'haf : (i < 'h5bb) ? 8'h80 :
(i < 'h5bf) ? 8'ha0 : (i < 'h5c0) ? 8'hb7 : (i < 'h5cf) ? 8'h80 : (i < 'h5d0) ? 8'ha0 :
(i < 'h5d6) ? 8'h80 : (i < 'h5db) ? 8'ha0 : (i < 'h5dc) ? 8'hb0 : (i < 'h5dd) ? 8'ha0 :
(i < 'h5df) ? 8'hb0 : (i < 'h5e0) ? 8'hbb : (i < 'h5e6) ? 8'ha0 : (i < 'h5e8) ? 8'hb0 :
(i < 'h5e9) ? 8'ha0 : (i < 'h5eb) ? 8'hb0 : (i < 'h5ec) ? 8'hb8 : (i < 'h5ed) ? 8'hb0 :
(i < 'h5ef) ? 8'hb8 : (i < 'h5f0) ? 8'hbc : (i < 'h5f1) ? 8'hb0 : (i < 'h5f5) ? 8'hb8 :
(i < 'h5f7) ? 8'hbc : (i < 'h5f8) ? 8'hbe : (i < 'h5fa) ? 8'hbc : (i < 'h5fb) ? 8'hbe :
(i < 'h5fc) ? 8'hbf : (i < 'h5fd) ? 8'hbe : (i < 'h600) ? 8'hbf : (i < 'h63e) ? 8'h80 :
(i < 'h640) ? 8'hc0 : (i < 'h657) ? 8'h80 : (i < 'h658) ? 8'hc0 : (i < 'h65a) ? 8'h80 :
(i < 'h660) ? 8'hc0 : (i < 'h663) ? 8'h80 : (i < 'h664) ? 8'hc0 : (i < 'h665) ? 8'h80 :
(i < 'h67f) ? 8'hc0 : (i < 'h680) ? 8'hcf : (i < 'h686) ? 8'h80 : (i < 'h689) ? 8'hc0 :
(i < 'h68a) ? 8'h80 : (i < 'h6bf) ? 8'hc0 : (i < 'h6c0) ? 8'hd7 : (i < 'h6dd) ? 8'hc0 :
(i < 'h6df) ? 8'hd0 : (i < 'h6e0) ? 8'hd9 : (i < 'h6e7) ? 8'hc0 : (i < 'h6e8) ? 8'hd0 :
(i < 'h6e9) ? 8'hc0 : (i < 'h6ed) ? 8'hd0 : (i < 'h6ef) ? 8'hd8 : (i < 'h6f0) ? 8'hdc :
(i < 'h6f2) ? 8'hd0 : (i < 'h6f5) ? 8'hd8 : (i < 'h6f7) ? 8'hdc : (i < 'h6f8) ? 8'hde :
(i < 'h6fa) ? 8'hdc : (i < 'h6fb) ? 8'hde : (i < 'h6fc) ? 8'hdf : (i < 'h6fd) ? 8'hde :
(i < 'h700) ? 8'hdf : (i < 'h71b) ? 8'hc0 : (i < 'h71c) ? 8'he0 : (i < 'h71d) ? 8'hc0 :
(i < 'h720) ? 8'he0 : (i < 'h727) ? 8'hc0 : (i < 'h728) ? 8'he0 : (i < 'h72a) ? 8'hc0 :
(i < 'h73f) ? 8'he0 : (i < 'h740) ? 8'he7 : (i < 'h75f) ? 8'he0 : (i < 'h760) ? 8'he8 :
(i < 'h76e) ? 8'he0 : (i < 'h76f) ? 8'he8 : (i < 'h770) ? 8'hec : (i < 'h773) ? 8'he0 :
(i < 'h776) ? 8'he8 : (i < 'h777) ? 8'hec : (i < 'h778) ? 8'hee : (i < 'h77b) ? 8'hec :
(i < 'h77d) ? 8'hee : (i < 'h780) ? 8'hef : (i < 'h78d) ? 8'he0 : (i < 'h790) ? 8'hf0 :
(i < 'h792) ? 8'he0 : (i < 'h7af) ? 8'hf0 : (i < 'h7b0) ? 8'hf4 : (i < 'h7b7) ? 8'hf0 :
(i < 'h7b8) ? 8'hf4 : (i < 'h7b9) ? 8'hf0 : (i < 'h7bb) ? 8'hf4 : (i < 'h7bd) ? 8'hf6 :
(i < 'h7c0) ? 8'hf7 : (i < 'h7c3) ? 8'hf0 : (i < 'h7c4) ? 8'hf8 : (i < 'h7c5) ? 8'hf0 :
(i < 'h7db) ? 8'hf8 : (i < 'h7dd) ? 8'hfa : (i < 'h7e0) ? 8'hfb : (i < 'h7e1) ? 8'hf8 :
(i < 'h7ed) ? 8'hfc : (i < 'h7f0) ? 8'hfd : (i < 'h7f8) ? 8'hfe : 8'hff;
end
for(i = 0; i<4096; i=i+1) begin : b3 assign wave_ps_[i] =
(i < 'h07f) ? 8'h00 : (i < 'h080) ? 8'h03 : (i < 'h0bf) ? 8'h00 : (i < 'h0c0) ? 8'h01 :
(i < 'h0ff) ? 8'h00 : (i < 'h100) ? 8'h0f : (i < 'h17f) ? 8'h00 : (i < 'h180) ? 8'h07 :
(i < 'h1bf) ? 8'h00 : (i < 'h1c0) ? 8'h03 : (i < 'h1df) ? 8'h00 : (i < 'h1e0) ? 8'h01 :
(i < 'h1fd) ? 8'h00 : (i < 'h1ff) ? 8'h07 : (i < 'h200) ? 8'h1f : (i < 'h27f) ? 8'h00 :
(i < 'h280) ? 8'h03 : (i < 'h2bf) ? 8'h00 : (i < 'h2c0) ? 8'h03 : (i < 'h2df) ? 8'h00 :
(i < 'h2e0) ? 8'h01 : (i < 'h2fe) ? 8'h00 : (i < 'h2ff) ? 8'h01 : (i < 'h300) ? 8'h0f :
(i < 'h33f) ? 8'h00 : (i < 'h340) ? 8'h01 : (i < 'h37f) ? 8'h00 : (i < 'h380) ? 8'h17 :
(i < 'h3bf) ? 8'h00 : (i < 'h3c0) ? 8'h3b : (i < 'h3df) ? 8'h00 : (i < 'h3e0) ? 8'h3d :
(i < 'h3ef) ? 8'h00 : (i < 'h3f0) ? 8'h3e : (i < 'h3f7) ? 8'h00 : (i < 'h3f8) ? 8'h3f :
(i < 'h3f9) ? 8'h00 : (i < 'h3fa) ? 8'h0c : (i < 'h3fb) ? 8'h1c : (i < 'h3fc) ? 8'h3f :
(i < 'h3fd) ? 8'h1e : (i < 'h400) ? 8'h3f : (i < 'h47f) ? 8'h00 : (i < 'h480) ? 8'h03 :
(i < 'h4bf) ? 8'h00 : (i < 'h4c0) ? 8'h01 : (i < 'h4ff) ? 8'h00 : (i < 'h500) ? 8'h0f :
(i < 'h53f) ? 8'h00 : (i < 'h540) ? 8'h01 : (i < 'h57f) ? 8'h00 : (i < 'h580) ? 8'h07 :
(i < 'h5bf) ? 8'h00 : (i < 'h5c0) ? 8'h0b : (i < 'h5df) ? 8'h00 : (i < 'h5e0) ? 8'h0a :
(i < 'h5ef) ? 8'h00 : (i < 'h5f0) ? 8'h5e : (i < 'h5f7) ? 8'h00 : (i < 'h5f8) ? 8'h5f :
(i < 'h5fb) ? 8'h00 : (i < 'h5fc) ? 8'h5f : (i < 'h5fd) ? 8'h0c : (i < 'h600) ? 8'h5f :
(i < 'h63f) ? 8'h00 : (i < 'h640) ? 8'h01 : (i < 'h67f) ? 8'h00 : (i < 'h680) ? 8'h47 :
(i < 'h6bf) ? 8'h00 : (i < 'h6c0) ? 8'h43 : (i < 'h6df) ? 8'h00 : (i < 'h6e0) ? 8'h65 :
(i < 'h6ef) ? 8'h00 : (i < 'h6f0) ? 8'h6e : (i < 'h6f7) ? 8'h00 : (i < 'h6f8) ? 8'h6f :
(i < 'h6f9) ? 8'h00 : (i < 'h6fb) ? 8'h40 : (i < 'h6fc) ? 8'h6f : (i < 'h6fd) ? 8'h40 :
(i < 'h700) ? 8'h6f : (i < 'h73f) ? 8'h00 : (i < 'h740) ? 8'h63 : (i < 'h75e) ? 8'h00 :
(i < 'h75f) ? 8'h40 : (i < 'h760) ? 8'h61 : (i < 'h767) ? 8'h00 : (i < 'h768) ? 8'h40 :
(i < 'h76b) ? 8'h00 : (i < 'h76c) ? 8'h40 : (i < 'h76d) ? 8'h00 : (i < 'h76f) ? 8'h40 :
(i < 'h770) ? 8'h70 : (i < 'h772) ? 8'h00 : (i < 'h777) ? 8'h40 : (i < 'h778) ? 8'h70 :
(i < 'h779) ? 8'h40 : (i < 'h77b) ? 8'h60 : (i < 'h77c) ? 8'h77 : (i < 'h77d) ? 8'h60 :
(i < 'h780) ? 8'h77 : (i < 'h78f) ? 8'h00 : (i < 'h790) ? 8'h40 : (i < 'h796) ? 8'h00 :
(i < 'h797) ? 8'h40 : (i < 'h798) ? 8'h60 : (i < 'h799) ? 8'h00 : (i < 'h79b) ? 8'h40 :
(i < 'h79c) ? 8'h60 : (i < 'h79d) ? 8'h40 : (i < 'h79f) ? 8'h60 : (i < 'h7a0) ? 8'h79 :
(i < 'h7a1) ? 8'h00 : (i < 'h7a7) ? 8'h40 : (i < 'h7a8) ? 8'h60 : (i < 'h7ab) ? 8'h40 :
(i < 'h7af) ? 8'h60 : (i < 'h7b0) ? 8'h78 : (i < 'h7b1) ? 8'h40 : (i < 'h7b7) ? 8'h60 :
(i < 'h7b8) ? 8'h78 : (i < 'h7b9) ? 8'h60 : (i < 'h7bb) ? 8'h70 : (i < 'h7bc) ? 8'h78 :
(i < 'h7bd) ? 8'h70 : (i < 'h7be) ? 8'h79 : (i < 'h7c0) ? 8'h7b : (i < 'h7c7) ? 8'h60 :
(i < 'h7c8) ? 8'h70 : (i < 'h7cb) ? 8'h60 : (i < 'h7cc) ? 8'h70 : (i < 'h7cd) ? 8'h60 :
(i < 'h7cf) ? 8'h70 : (i < 'h7d0) ? 8'h7c : (i < 'h7d1) ? 8'h60 : (i < 'h7d7) ? 8'h70 :
(i < 'h7d8) ? 8'h7c : (i < 'h7d9) ? 8'h70 : (i < 'h7db) ? 8'h78 : (i < 'h7dc) ? 8'h7c :
(i < 'h7dd) ? 8'h78 : (i < 'h7df) ? 8'h7c : (i < 'h7e0) ? 8'h7d : (i < 'h7e1) ? 8'h70 :
(i < 'h7e7) ? 8'h78 : (i < 'h7e8) ? 8'h7c : (i < 'h7e9) ? 8'h78 : (i < 'h7eb) ? 8'h7c :
(i < 'h7ec) ? 8'h7e : (i < 'h7ed) ? 8'h7c : (i < 'h7f0) ? 8'h7e : (i < 'h7f3) ? 8'h7c :
(i < 'h7f5) ? 8'h7e : (i < 'h7f8) ? 8'h7f : (i < 'h7f9) ? 8'h7e : (i < 'h7ff) ? 8'h7f :
(i < 'h800) ? 8'hff : (i < 'h87f) ? 8'h00 : (i < 'h880) ? 8'h03 : (i < 'h8bf) ? 8'h00 :
(i < 'h8c0) ? 8'h01 : (i < 'h8ff) ? 8'h00 : (i < 'h900) ? 8'h8f : (i < 'h93f) ? 8'h00 :
(i < 'h940) ? 8'h01 : (i < 'h97f) ? 8'h00 : (i < 'h980) ? 8'h87 : (i < 'h9bf) ? 8'h00 :
(i < 'h9c0) ? 8'h83 : (i < 'h9de) ? 8'h00 : (i < 'h9df) ? 8'h80 : (i < 'h9e0) ? 8'h8d :
(i < 'h9e7) ? 8'h00 : (i < 'h9e8) ? 8'h80 : (i < 'h9eb) ? 8'h00 : (i < 'h9ec) ? 8'h80 :
(i < 'h9ed) ? 8'h00 : (i < 'h9ef) ? 8'h80 : (i < 'h9f0) ? 8'h8e : (i < 'h9f3) ? 8'h00 :
(i < 'h9f7) ? 8'h80 : (i < 'h9f8) ? 8'h8f : (i < 'h9fb) ? 8'h80 : (i < 'h9fc) ? 8'h9f :
(i < 'h9fd) ? 8'h80 : (i < 'ha00) ? 8'h9f : (i < 'ha3f) ? 8'h00 : (i < 'ha40) ? 8'h01 :
(i < 'ha6f) ? 8'h00 : (i < 'ha70) ? 8'h80 : (i < 'ha77) ? 8'h00 : (i < 'ha78) ? 8'h80 :
(i < 'ha7b) ? 8'h00 : (i < 'ha7c) ? 8'h80 : (i < 'ha7d) ? 8'h00 : (i < 'ha7f) ? 8'h80 :
(i < 'ha80) ? 8'h87 : (i < 'ha9f) ? 8'h00 : (i < 'haa0) ? 8'h80 : (i < 'haaf) ? 8'h00 :
(i < 'hab0) ? 8'h80 : (i < 'hab7) ? 8'h00 : (i < 'hab8) ? 8'h80 : (i < 'habb) ? 8'h00 :
(i < 'habf) ? 8'h80 : (i < 'hac0) ? 8'h83 : (i < 'hacf) ? 8'h00 : (i < 'had0) ? 8'h80 :
(i < 'had5) ? 8'h00 : (i < 'had8) ? 8'h80 : (i < 'had9) ? 8'h00 : (i < 'hadf) ? 8'h80 :
(i < 'hae0) ? 8'h81 : (i < 'haef) ? 8'h80 : (i < 'haf0) ? 8'h84 : (i < 'haf7) ? 8'h80 :
(i < 'haf8) ? 8'h87 : (i < 'hafb) ? 8'h80 : (i < 'hafc) ? 8'h87 : (i < 'hafd) ? 8'h80 :
(i < 'hafe) ? 8'h8f : (i < 'hb00) ? 8'haf : (i < 'hb0f) ? 8'h00 : (i < 'hb10) ? 8'h80 :
(i < 'hb17) ? 8'h00 : (i < 'hb18) ? 8'h80 : (i < 'hb1b) ? 8'h00 : (i < 'hb20) ? 8'h80 :
(i < 'hb23) ? 8'h00 : (i < 'hb24) ? 8'h80 : (i < 'hb26) ? 8'h00 : (i < 'hb28) ? 8'h80 :
(i < 'hb29) ? 8'h00 : (i < 'hb3f) ? 8'h80 : (i < 'hb40) ? 8'h83 : (i < 'hb5f) ? 8'h80 :
(i < 'hb60) ? 8'h81 : (i < 'hb6f) ? 8'h80 : (i < 'hb70) ? 8'ha0 : (i < 'hb77) ? 8'h80 :
(i < 'hb78) ? 8'ha0 : (i < 'hb7b) ? 8'h80 : (i < 'hb7c) ? 8'ha0 : (i < 'hb7d) ? 8'h80 :
(i < 'hb7e) ? 8'ha3 : (i < 'hb80) ? 8'hb7 : (i < 'hb9f) ? 8'h80 : (i < 'hba0) ? 8'hb1 :
(i < 'hbaf) ? 8'h80 : (i < 'hbb0) ? 8'hb0 : (i < 'hbb7) ? 8'h80 : (i < 'hbb8) ? 8'hb0 :
(i < 'hbb9) ? 8'h80 : (i < 'hbbb) ? 8'ha0 : (i < 'hbbc) ? 8'hb0 : (i < 'hbbd) ? 8'ha0 :
(i < 'hbbe) ? 8'hb8 : (i < 'hbbf) ? 8'hb9 : (i < 'hbc0) ? 8'hbb : (i < 'hbc7) ? 8'h80 :
(i < 'hbc8) ? 8'ha0 : (i < 'hbcb) ? 8'h80 : (i < 'hbcc) ? 8'ha0 : (i < 'hbcd) ? 8'h80 :
(i < 'hbcf) ? 8'ha0 : (i < 'hbd0) ? 8'hb8 : (i < 'hbd1) ? 8'h80 : (i < 'hbd7) ? 8'ha0 :
(i < 'hbd8) ? 8'hb8 : (i < 'hbd9) ? 8'ha0 : (i < 'hbdb) ? 8'hb0 : (i < 'hbdc) ? 8'hb8 :
(i < 'hbdd) ? 8'hb0 : (i < 'hbdf) ? 8'hbc : (i < 'hbe0) ? 8'hbd : (i < 'hbe1) ? 8'ha0 :
(i < 'hbe5) ? 8'hb0 : (i < 'hbe7) ? 8'hb8 : (i < 'hbe8) ? 8'hbc : (i < 'hbe9) ? 8'hb0 :
(i < 'hbeb) ? 8'hb8 : (i < 'hbec) ? 8'hbc : (i < 'hbed) ? 8'hb8 : (i < 'hbee) ? 8'hbc :
(i < 'hbf0) ? 8'hbe : (i < 'hbf1) ? 8'hb8 : (i < 'hbf3) ? 8'hbc : (i < 'hbf4) ? 8'hbe :
(i < 'hbf5) ? 8'hbc : (i < 'hbf7) ? 8'hbe : (i < 'hbf8) ? 8'hbf : (i < 'hbf9) ? 8'hbe :
(i < 'hc00) ? 8'hbf : (i < 'hc03) ? 8'h00 : (i < 'hc04) ? 8'h80 : (i < 'hc07) ? 8'h00 :
(i < 'hc08) ? 8'h80 : (i < 'hc0b) ? 8'h00 : (i < 'hc0c) ? 8'h80 : (i < 'hc0f) ? 8'h00 :
(i < 'hc10) ? 8'h80 : (i < 'hc11) ? 8'h00 : (i < 'hc18) ? 8'h80 : (i < 'hc19) ? 8'h00 :
(i < 'hc3f) ? 8'h80 : (i < 'hc40) ? 8'h81 : (i < 'hc7f) ? 8'h80 : (i < 'hc80) ? 8'hc7 :
(i < 'hcbe) ? 8'h80 : (i < 'hcbf) ? 8'hc0 : (i < 'hcc0) ? 8'hc3 : (i < 'hccf) ? 8'h80 :
(i < 'hcd0) ? 8'hc0 : (i < 'hcd7) ? 8'h80 : (i < 'hcd8) ? 8'hc0 : (i < 'hcdb) ? 8'h80 :
(i < 'hcdc) ? 8'hc0 : (i < 'hcdd) ? 8'h80 : (i < 'hcdf) ? 8'hc0 : (i < 'hce0) ? 8'hc1 :
(i < 'hce7) ? 8'h80 : (i < 'hce8) ? 8'hc0 : (i < 'hceb) ? 8'h80 : (i < 'hcf7) ? 8'hc0 :
(i < 'hcf8) ? 8'hc7 : (i < 'hcfb) ? 8'hc0 : (i < 'hcfc) ? 8'hc7 : (i < 'hcfd) ? 8'hc0 :
(i < 'hd00) ? 8'hcf : (i < 'hd1f) ? 8'h80 : (i < 'hd20) ? 8'hc0 : (i < 'hd2f) ? 8'h80 :
(i < 'hd30) ? 8'hc0 : (i < 'hd36) ? 8'h80 : (i < 'hd38) ? 8'hc0 : (i < 'hd39) ? 8'h80 :
(i < 'hd3f) ? 8'hc0 : (i < 'hd40) ? 8'hc3 : (i < 'hd47) ? 8'h80 : (i < 'hd48) ? 8'hc0 :
(i < 'hd4b) ? 8'h80 : (i < 'hd4c) ? 8'hc0 : (i < 'hd4d) ? 8'h80 : (i < 'hd50) ? 8'hc0 :
(i < 'hd51) ? 8'h80 : (i < 'hd5f) ? 8'hc0 : (i < 'hd60) ? 8'hc1 : (i < 'hd7d) ? 8'hc0 :
(i < 'hd7e) ? 8'hc1 : (i < 'hd7f) ? 8'hc7 : (i < 'hd80) ? 8'hd7 : (i < 'hdaf) ? 8'hc0 :
(i < 'hdb0) ? 8'hd0 : (i < 'hdb7) ? 8'hc0 : (i < 'hdb8) ? 8'hd0 : (i < 'hdbb) ? 8'hc0 :
(i < 'hdbc) ? 8'hd0 : (i < 'hdbd) ? 8'hc0 : (i < 'hdbe) ? 8'hd0 : (i < 'hdbf) ? 8'hd8 :
(i < 'hdc0) ? 8'hdb : (i < 'hdcf) ? 8'hc0 : (i < 'hdd0) ? 8'hd8 : (i < 'hdd7) ? 8'hc0 :
(i < 'hdd8) ? 8'hd8 : (i < 'hddb) ? 8'hc0 : (i < 'hddc) ? 8'hd8 : (i < 'hddd) ? 8'hd0 :
(i < 'hddf) ? 8'hd8 : (i < 'hde0) ? 8'hdd : (i < 'hde3) ? 8'hc0 : (i < 'hde4) ? 8'hd0 :
(i < 'hde5) ? 8'hc0 : (i < 'hde7) ? 8'hd0 : (i < 'hde8) ? 8'hdc : (i < 'hde9) ? 8'hd0 :
(i < 'hdeb) ? 8'hd8 : (i < 'hdec) ? 8'hdc : (i < 'hded) ? 8'hd8 : (i < 'hdef) ? 8'hdc :
(i < 'hdf0) ? 8'hde : (i < 'hdf1) ? 8'hd8 : (i < 'hdf3) ? 8'hdc : (i < 'hdf4) ? 8'hde :
(i < 'hdf5) ? 8'hdc : (i < 'hdf7) ? 8'hde : (i < 'hdf8) ? 8'hdf : (i < 'hdf9) ? 8'hde :
(i < 'he00) ? 8'hdf : (i < 'he3f) ? 8'hc0 : (i < 'he40) ? 8'he3 : (i < 'he57) ? 8'hc0 :
(i < 'he58) ? 8'he0 : (i < 'he5b) ? 8'hc0 : (i < 'he5c) ? 8'he0 : (i < 'he5d) ? 8'hc0 :
(i < 'he5f) ? 8'he0 : (i < 'he60) ? 8'he1 : (i < 'he67) ? 8'hc0 : (i < 'he68) ? 8'he0 :
(i < 'he6b) ? 8'hc0 : (i < 'he70) ? 8'he0 : (i < 'he71) ? 8'hc0 : (i < 'he7d) ? 8'he0 :
(i < 'he7e) ? 8'he1 : (i < 'he7f) ? 8'he3 : (i < 'he80) ? 8'he7 : (i < 'he87) ? 8'hc0 :
(i < 'he88) ? 8'he0 : (i < 'he8b) ? 8'hc0 : (i < 'he8c) ? 8'he0 : (i < 'he8d) ? 8'hc0 :
(i < 'he90) ? 8'he0 : (i < 'he93) ? 8'hc0 : (i < 'he94) ? 8'he0 : (i < 'he95) ? 8'hc0 :
(i < 'hebf) ? 8'he0 : (i < 'hec0) ? 8'heb : (i < 'hedb) ? 8'he0 : (i < 'hedc) ? 8'he8 :
(i < 'hedd) ? 8'he0 : (i < 'hedf) ? 8'he8 : (i < 'hee0) ? 8'hed : (i < 'hee7) ? 8'he0 :
(i < 'hee8) ? 8'hec : (i < 'heeb) ? 8'he0 : (i < 'heec) ? 8'hec : (i < 'heed) ? 8'he8 :
(i < 'heef) ? 8'hec : (i < 'hef0) ? 8'hee : (i < 'hef3) ? 8'he8 : (i < 'hef5) ? 8'hec :
(i < 'hef7) ? 8'hee : (i < 'hef8) ? 8'hef : (i < 'hef9) ? 8'hec : (i < 'hf00) ? 8'hef :
(i < 'hf1f) ? 8'he0 : (i < 'hf20) ? 8'hf0 : (i < 'hf27) ? 8'he0 : (i < 'hf28) ? 8'hf0 :
(i < 'hf2b) ? 8'he0 : (i < 'hf2c) ? 8'hf0 : (i < 'hf2d) ? 8'he0 : (i < 'hf30) ? 8'hf0 :
(i < 'hf33) ? 8'he0 : (i < 'hf3f) ? 8'hf0 : (i < 'hf40) ? 8'hf3 : (i < 'hf43) ? 8'he0 :
(i < 'hf5f) ? 8'hf0 : (i < 'hf60) ? 8'hf5 : (i < 'hf6d) ? 8'hf0 : (i < 'hf6f) ? 8'hf4 :
(i < 'hf70) ? 8'hf6 : (i < 'hf73) ? 8'hf0 : (i < 'hf74) ? 8'hf4 : (i < 'hf75) ? 8'hf0 :
(i < 'hf76) ? 8'hf4 : (i < 'hf77) ? 8'hf6 : (i < 'hf78) ? 8'hf7 : (i < 'hf79) ? 8'hf4 :
(i < 'hf7b) ? 8'hf6 : (i < 'hf80) ? 8'hf7 : (i < 'hf87) ? 8'hf0 : (i < 'hf88) ? 8'hf8 :
(i < 'hf8d) ? 8'hf0 : (i < 'hf90) ? 8'hf8 : (i < 'hf93) ? 8'hf0 : (i < 'hf94) ? 8'hf8 :
(i < 'hf95) ? 8'hf0 : (i < 'hf9f) ? 8'hf8 : (i < 'hfa0) ? 8'hf9 : (i < 'hfaf) ? 8'hf8 :
(i < 'hfb0) ? 8'hfa : (i < 'hfb7) ? 8'hf8 : (i < 'hfb8) ? 8'hfb : (i < 'hfb9) ? 8'hf8 :
(i < 'hfbb) ? 8'hfa : (i < 'hfc0) ? 8'hfb : (i < 'hfc3) ? 8'hf8 : (i < 'hfc4) ? 8'hfc :
(i < 'hfc5) ? 8'hf8 : (i < 'hfd7) ? 8'hfc : (i < 'hfd8) ? 8'hfd : (i < 'hfdb) ? 8'hfc :
(i < 'hfe0) ? 8'hfd : (i < 'hfe2) ? 8'hfc : (i < 'hff0) ? 8'hfe : 8'hff;
end
for(i = 0; i<4096; i=i+1) begin : b4 assign wave_pst[i] =
(i < 'h3ff) ? 8'h00 : (i < 'h400) ? 8'h1f : (i < 'h7ee) ? 8'h00 : (i < 'h7ef) ? 8'h20 :
(i < 'h7f0) ? 8'h70 : (i < 'h7f1) ? 8'h60 : (i < 'h7f2) ? 8'h20 : (i < 'h7f7) ? 8'h70 :
(i < 'h7fa) ? 8'h78 : (i < 'h7fc) ? 8'h7c : (i < 'h7fe) ? 8'h7e : (i < 'h800) ? 8'h7f :
(i < 'hbfd) ? 8'h00 : (i < 'hbfe) ? 8'h08 : (i < 'hbff) ? 8'h1e : (i < 'hc00) ? 8'h3f :
(i < 'hdf7) ? 8'h00 : (i < 'hdfe) ? 8'h80 : (i < 'hdff) ? 8'h8c : (i < 'he00) ? 8'h9f :
(i < 'he3e) ? 8'h00 : (i < 'he40) ? 8'h80 : (i < 'he5e) ? 8'h00 : (i < 'he60) ? 8'h80 :
(i < 'he66) ? 8'h00 : (i < 'he67) ? 8'h80 : (i < 'he6a) ? 8'h00 : (i < 'he80) ? 8'h80 :
(i < 'he82) ? 8'h00 : (i < 'he83) ? 8'h80 : (i < 'he85) ? 8'h00 : (i < 'he89) ? 8'h80 :
(i < 'he8a) ? 8'h00 : (i < 'heee) ? 8'h80 : (i < 'heff) ? 8'hc0 : (i < 'hf00) ? 8'hcf :
(i < 'hf6f) ? 8'hc0 : (i < 'hf70) ? 8'he0 : (i < 'hf74) ? 8'hc0 : (i < 'hf7f) ? 8'he0 :
(i < 'hf80) ? 8'he3 : (i < 'hfb6) ? 8'he0 : (i < 'hfda) ? 8'hf0 : (i < 'hfeb) ? 8'hf8 :
(i < 'hff5) ? 8'hfc : (i < 'hff9) ? 8'hfe : 8'hff;
end
endgenerate
endmodule
common/a8core/sid8580/sid_voice.v
// altera message_off 10030
module sid_voice
(
input clock,
input ce_1m,
input reset,
input [7:0] freq_lo,
input [7:0] freq_hi,
input [7:0] pw_lo,
input [3:0] pw_hi,
input [7:0] control,
input [7:0] att_dec,
input [7:0] sus_rel,
input osc_msb_in,
input [7:0] _st_out,
input [7:0] p_t_out,
input [7:0] ps__out,
input [7:0] pst_out,
output reg [11:0] sawtooth,
output reg [11:0] triangle,
output osc_msb_out,
output [11:0] signal_out,
output [ 7:0] osc_out,
output [ 7:0] env_out
);
// Internal Signals
reg [23:0] oscillator;
reg osc_edge;
reg osc_msb_in_prv;
reg [11:0] pulse;
reg [11:0] noise;
reg [22:0] lfsr_noise;
wire [ 7:0] envelope;
reg [11:0] wave_out;
reg [19:0] dca_out;
`define noise_ctrl control[7]
`define pulse_ctrl control[6]
`define saw_ctrl control[5]
`define tri_ctrl control[4]
`define test_ctrl control[3]
`define ringmod_ctrl control[2]
`define sync_ctrl control[1]
// Signal Assignments
assign osc_msb_out = oscillator[23];
assign signal_out = dca_out[19:8];
assign osc_out = wave_out[11:4];
assign env_out = envelope;
// Digital Controlled Amplifier
always @(posedge clock) if(ce_1m) dca_out <= wave_out * envelope;
// Envelope Instantiation
sid_envelope adsr
(
.clock(clock),
.ce_1m(ce_1m),
.reset(reset),
.gate(control[0]),
.att_dec(att_dec),
.sus_rel(sus_rel),
.envelope(envelope)
);
// Phase Accumulating Oscillator
always @(posedge clock) begin
if(ce_1m) begin
osc_msb_in_prv <= osc_msb_in;
if (reset || `test_ctrl || ((`sync_ctrl) && (!osc_msb_in) && (osc_msb_in != osc_msb_in_prv)))
oscillator <= 0;
else
oscillator <= oscillator + {freq_hi, freq_lo};
end
end
// Waveform Generator
always @(posedge clock) begin
if (reset) begin
triangle <= 0;
sawtooth <= 0;
pulse <= 0;
noise <= 0;
osc_edge <= 0;
lfsr_noise <= 23'h7fffff;
end
else if(ce_1m) begin
triangle <= (`ringmod_ctrl) ?
{({11{osc_msb_in}} ^ {{11{oscillator[23]}}}) ^ oscillator[22:12], 1'b0} :
{{11{oscillator[23]}} ^ oscillator[22:12], 1'b0};
sawtooth <= oscillator[23:12];
pulse <= (`test_ctrl) ? 12'hfff :
(oscillator[23:12] >= {pw_hi, pw_lo}) ? {12{1'b1}} :
{12{1'b0}};
noise <= {lfsr_noise[21], lfsr_noise[19], lfsr_noise[15],
lfsr_noise[12], lfsr_noise[10], lfsr_noise[6],
lfsr_noise[3], lfsr_noise[1], 4'b0000};
osc_edge <= (oscillator[19] && !osc_edge) ? 1'b1 :
(!oscillator[19] && osc_edge) ? 1'b0 :
osc_edge;
lfsr_noise <= (oscillator[19] && !osc_edge) ?
{lfsr_noise[21:0], (lfsr_noise[22] | `test_ctrl) ^ lfsr_noise[17]} :
lfsr_noise;
end
end
// Waveform Output Selector
always @(*) begin
case (control[7:4])
4'b0001: wave_out = triangle;
4'b0010: wave_out = sawtooth;
4'b0011: wave_out = {_st_out, 4'b0000};
4'b0100: wave_out = pulse;
4'b0101: wave_out = {p_t_out, 4'b0000} & pulse;
4'b0110: wave_out = {ps__out, 4'b0000} & pulse;
4'b0111: wave_out = {pst_out, 4'b0000} & pulse;
4'b1000: wave_out = noise;
default: wave_out = 0;
endcase
end
endmodule

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