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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY zpu_config_regs IS
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PORT
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(
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CLK : IN STD_LOGIC;
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ENABLE_179 : in std_logic;
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ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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WR_EN : IN STD_LOGIC;
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-- SWITCHES
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SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
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KEY : in std_logic_vector(3 downto 0); -- already synchronized
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-- LEDS
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LEDG : out std_logic_vector(7 downto 0);
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LEDR : out std_logic_vector(9 downto 0);
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-- SDCARD
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SDCARD_CLK : out std_logic;
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SDCARD_CMD : out std_logic;
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SDCARD_DAT : in std_logic;
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SDCARD_DAT3 : out std_logic;
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-- ATARI interface (in future we can also turbo load by directly hitting memory...)
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SIO_DATA_IN : out std_logic;
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SIO_COMMAND_OUT : in std_logic;
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SIO_DATA_OUT : in std_logic;
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-- CPU interface
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DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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PAUSE_ZPU : out std_logic;
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-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
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PAL : OUT STD_LOGIC;
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USE_SDRAM : OUT STD_LOGIC;
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RAM_SELECT : OUT STD_LOGIC_VECTOR(3 downto 0);
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VGA : OUT STD_LOGIC;
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COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
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GPIO_ENABLE : OUT STD_LOGIC;
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ROM_SELECT : out stD_logic_vector(3 downto 0);
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-- sector buffer
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sector : out std_logic_vector(31 downto 0);
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sector_request : out std_logic;
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sector_ready : in std_logic;
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-- system reset/halt
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PLL_LOCKED : IN STD_LOGIC; -- pll locked
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REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
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RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
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RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
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RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
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PAUSE_6502 : out std_logic;
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THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
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ZPU_HEX : out std_logic_vector(15 downto 0)
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-- -- synchronize async inputs
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-- locked_synchronizer : synchronizer
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-- port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
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);
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END zpu_config_regs;
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ARCHITECTURE vhdl OF zpu_config_regs IS
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COMPONENT complete_address_decoder IS
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generic (width : natural := 4);
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PORT
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(
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addr_in : in std_logic_vector(width-1 downto 0);
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addr_decoded : out std_logic_vector((2**width)-1 downto 0)
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);
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END component;
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COMPONENT spi_master IS
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GENERIC(
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slaves : INTEGER := 4; --number of spi slaves
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d_width : INTEGER := 2); --data bus width
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PORT(
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clock : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --asynchronous reset
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enable : IN STD_LOGIC; --initiate transaction
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cpol : IN STD_LOGIC; --spi clock polarity
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cpha : IN STD_LOGIC; --spi clock phase
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cont : IN STD_LOGIC; --continuous mode command
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clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
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addr : IN INTEGER; --address of slave
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tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
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miso : IN STD_LOGIC; --master in, slave out
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sclk : BUFFER STD_LOGIC; --spi clock
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ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
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mosi : OUT STD_LOGIC; --master out, slave in
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busy : OUT STD_LOGIC; --busy / data ready signal
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rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
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END component;
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component pokey IS
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PORT
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(
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CLK : IN STD_LOGIC;
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--ENABLE_179 :in std_logic;
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CPU_MEMORY_READY :in std_logic;
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ANTIC_MEMORY_READY :in std_logic;
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ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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WR_EN : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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-- keyboard interface
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keyboard_scan : out std_logic_vector(5 downto 0);
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keyboard_response : in std_logic_vector(1 downto 0);
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-- pots - go high as capacitor charges
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POT_IN : in std_logic_vector(7 downto 0);
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-- sio interface
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SIO_IN1 : IN std_logic;
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SIO_IN2 : IN std_logic;
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SIO_IN3 : IN std_logic;
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DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
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CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
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CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
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CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
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IRQ_N_OUT : OUT std_logic;
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SIO_OUT1 : OUT std_logic;
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SIO_OUT2 : OUT std_logic;
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SIO_OUT3 : OUT std_logic;
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SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
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POT_RESET : out std_logic
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);
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END component;
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function vectorize(s: std_logic) return std_logic_vector is
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variable v: std_logic_vector(0 downto 0);
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begin
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v(0) := s;
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return v;
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end;
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signal addr_decoded : std_logic_vector(15 downto 0);
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signal config_6502_next : std_logic_vector(7 downto 0);
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signal config_6502_reg : std_logic_vector(7 downto 0);
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signal ram_select_next : std_logic_vector(3 downto 0);
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signal ram_select_reg : std_logic_vector(3 downto 0);
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signal rom_select_next : std_logic_vector(3 downto 0);
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signal rom_select_reg : std_logic_vector(3 downto 0);
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signal gpio_enable_next : std_logic;
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signal gpio_enable_reg : std_logic;
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signal pause_next : std_logic_vector(31 downto 0);
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signal pause_reg : std_logic_vector(31 downto 0);
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signal paused_next : std_logic;
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signal paused_reg : std_logic;
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signal ledg_next : std_logic_vector(7 downto 0);
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signal ledg_reg : std_logic_vector(7 downto 0);
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signal ledr_next : std_logic_vector(9 downto 0);
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signal ledr_reg : std_logic_vector(9 downto 0);
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signal reset_n_next : std_logic;
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signal reset_n_reg : std_logic;
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signal reset_6502_cpu_next : std_logic;
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signal reset_6502_cpu_reg : std_logic;
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signal reset_zpu_next : std_logic;
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signal reset_zpu_reg : std_logic;
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signal spi_miso : std_logic;
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signal spi_mosi : std_logic;
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signal spi_busy : std_logic;
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signal spi_enable : std_logic;
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signal spi_chip_select : std_logic_vector(0 downto 0);
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signal spi_clk_out : std_logic;
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signal spi_tx_data : std_logic_vector(7 downto 0);
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signal spi_rx_data : std_logic_vector(7 downto 0);
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signal spi_addr_next : std_logic;
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signal spi_addr_reg : std_logic;
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signal spi_speed_next : std_logic_vector(7 downto 0);
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signal spi_speed_reg : std_logic_vector(7 downto 0);
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signal zpu_hex_next : std_logic_vector(15 downto 0);
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signal zpu_hex_reg : std_logic_vector(15 downto 0);
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signal pokey_data_out : std_logic_vector(7 downto 0);
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signal sector_next : std_logic_vector(31 downto 0);
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signal sector_reg : std_logic_vector(31 downto 0);
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signal sector_request_next : std_logic;
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signal sector_request_reg : std_logic; -- cleared when ready asserted
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begin
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-- register
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process(clk,pll_locked)
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begin
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if (clk'event and clk='1') then
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if (pll_locked = '0') then
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config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
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rom_select_reg <= "0010";
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ram_select_reg <= "0010";
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gpio_enable_reg <= '0';
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pause_reg <= (others=>'0');
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paused_reg <= '0';
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ledg_reg <= (others=>'0');
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ledr_reg <= (others=>'0');
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spi_addr_reg <= '1';
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spi_speed_reg <= X"80";
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zpu_hex_reg <= X"b007";
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reset_n_reg <= '0';
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reset_zpu_reg <= '1';
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reset_6502_cpu_reg <= '1';
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sector_reg <= (others=>'0');
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sector_request_reg <= '0';
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else
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config_6502_reg <= config_6502_next;
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rom_select_reg <= rom_select_next;
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ram_select_reg <= ram_select_next;
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gpio_enable_reg <= gpio_enable_next;
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pause_reg <= pause_next;
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paused_reg <= paused_next;
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ledg_reg <= ledg_next;
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ledr_reg <= ledr_next;
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spi_addr_reg <= spi_addr_next;
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spi_speed_reg <= spi_speed_next;
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zpu_hex_reg <= zpu_hex_next;
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reset_n_reg <= reset_n_next;
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reset_zpu_reg <= reset_zpu_next;
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reset_6502_cpu_reg <= reset_6502_cpu_next;
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sector_reg <= sector_next;
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sector_request_reg <= sector_request_next;
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end if;
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end if;
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end process;
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-- decode address
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decode_addr1 : complete_address_decoder
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generic map(width=>4)
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port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
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-- spi - for sd card access without bit banging...
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-- 200KHz to start with - probably fine for 8-bit, can up it later after init
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spi_master1 : spi_master
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generic map(slaves=>1,d_width=>8)
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port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
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tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
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rx_data=>spi_rx_data,busy=>spi_busy);
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-- spi-programming model:
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-- reg for write/read
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-- data (send/receive)
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-- busy
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-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
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-- chip select
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-- uart - another Pokey! Running at atari frequency.
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uart1 : pokey
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port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en,
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reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
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sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
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data_out=>pokey_data_out,
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sio_out1=>sio_data_in);
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-- hardware regs for ZPU
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--
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-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
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-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
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-- these need storing somewhere...
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-- TODO - volume output from here
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-- TODO - hex digits register
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-- TODO - if we take over antic we need to point antic to alternative RAM!
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-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
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-- TODO - reset pokey and pia interrupts too?
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--
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-- virtual joystick button -> keyboard (windows key?)
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-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
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--
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-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
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--
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-- STEP 1 -> joystick -> keyboard (DONE)
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-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled (DONE)
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-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
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-- STEP 4 -> zpu starts 6502 on key1 (DONE)
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-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
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--
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-- CONFIG_ATARI:
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-- R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset
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-- R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
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-- R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
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-- R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
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-- PAUSE (DONE) -- W: 0-31:wait for n cycles
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-- SWITCH (DONE)
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-- R: 0-9 - switches
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-- KEY (DONE)
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-- R: 0-3 - keys
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-- LEDG (DONE)
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-- R/W: 0-9
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-- LEDR (DONE)
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-- R/W: 0-9
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-- SPI_DATA (DONE)
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-- W - write data (starts transmission)
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-- R - read data (wait for complete first)
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-- SPI_STATE/SPI_CTRL (DONE)
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-- R: 0=busy
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-- W: 0=select_n, speed
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-- SIO
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-- R: 0=CMD
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-- FPGA board (DONE)
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-- R(32 bits) 0=DE1
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-- HEX digits
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-- W(16 bits)
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-- SECTOR
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-- W(32 bits) - write here initiates a request_reset_zpu
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-- R: 0=request_active
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-- TODO, ROM select, RAM select etc etc
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-- TODO firmware with OSD!
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-- Writes to registers
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process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg, sector_request_reg, sector_ready, sector_reg)
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begin
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config_6502_next <= config_6502_reg;
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rom_select_next <= rom_select_reg;
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ram_select_next <= ram_select_reg;
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gpio_enable_next <= gpio_enable_reg;
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pause_next <= pause_reg;
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ledg_next <= ledg_reg;
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ledr_next <= ledr_reg;
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spi_speed_next <= spi_speed_reg;
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spi_addr_next <= spi_addr_reg;
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spi_tx_data <= (others=>'0');
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spi_enable <= '0';
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zpu_hex_next <= zpu_hex_reg;
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sector_next <= sector_reg;
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sector_request_next <= sector_request_reg and not(sector_ready);
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paused_next <= '0';
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if (not(pause_reg = X"00000000")) then
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pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
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paused_next <= '1';
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end if;
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if (wr_en = '1' and addr(4) = '0') then
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if(addr_decoded(0) = '1') then
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config_6502_next <= cpu_data_in(7 downto 0);
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ram_select_next <= cpu_DATA_IN(11 downto 8);
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rom_select_next <= cpu_DATA_IN(15 downto 12);
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gpio_enable_next <= cpu_DATA_IN(16);
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end if;
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if(addr_decoded(1) = '1') then
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pause_next <= cpu_data_in;
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paused_next <= '1';
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end if;
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if(addr_decoded(4) = '1') then
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ledg_next <= cpu_data_in(7 downto 0);
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end if;
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if(addr_decoded(5) = '1') then
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ledr_next <= cpu_data_in(9 downto 0);
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end if;
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if(addr_decoded(6) = '1') then
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-- TODO, check overrun?
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spi_tx_data <= cpu_data_in(7 downto 0);
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spi_enable <= '1';
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end if;
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if(addr_decoded(7) = '1') then
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spi_addr_next <= cpu_data_in(0);
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if (cpu_data_in(1) = '1') then
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spi_speed_next <= X"80"; -- slow, for init
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else
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spi_speed_next <= X"04"; -- turbo!
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end if;
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end if;
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if(addr_decoded(10) = '1') then
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zpu_hex_next <= cpu_data_in(15 downto 0);
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end if;
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if(addr_decoded(11) = '1') then
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sector_next <= cpu_data_in;
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sector_request_next <= '1';
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end if;
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end if;
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end process;
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-- Read from registers
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process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg, sector_request_reg)
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begin
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data_out <= (others=>'0');
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if (addr(4) = '0') then
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if (addr_decoded(0) = '1') then
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data_out(7 downto 0) <= config_6502_reg;
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data_out(11 downto 8) <= ram_select_reg;
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data_out(15 downto 12) <= rom_select_reg;
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data_out(16) <= gpio_enable_reg;
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end if;
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if (addr_decoded(2) = '1') then
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data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.
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end if;
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if (addr_decoded(3) = '1') then
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data_out(3 downto 0) <= key;
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end if;
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|
if (addr_decoded(4) = '1') then
|
|
data_out(7 downto 0) <= ledg_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(5) = '1') then
|
|
data_out(9 downto 0) <= ledr_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(6) = '1') then
|
|
data_out(7 downto 0) <= spi_rx_data;
|
|
end if;
|
|
|
|
if (addr_decoded(7) = '1') then
|
|
data_out(0) <= spi_busy;
|
|
end if;
|
|
|
|
if(addr_decoded(8) = '1') then
|
|
data_out(0) <= sio_command_OUT;
|
|
end if;
|
|
|
|
if (addr_decoded(9) = '1') then
|
|
--data_out <= X"00000000"; -- DE1!
|
|
--data_out <= X"00000001"; -- DE2!
|
|
--data_out <= X"00000002"; -- SOCKIT!
|
|
--data_out <= X"00000003"; -- REPLAY!
|
|
data_out <= X"00000004"; -- MMC!
|
|
end if;
|
|
|
|
if (addr_decoded(10) = '1') then
|
|
data_out(15 downto 0) <= zpu_hex_reg;
|
|
end if;
|
|
|
|
if (addr_decoded(11) = '1') then
|
|
data_out(0) <= sector_request_reg;
|
|
end if;
|
|
|
|
else
|
|
data_out(7 downto 0) <= pokey_data_out;
|
|
end if;
|
|
end process;
|
|
|
|
process(request_reset_zpu, config_6502_next, config_6502_reg)
|
|
begin
|
|
reset_n_next <= '1';
|
|
reset_zpu_next <= '0';
|
|
reset_6502_cpu_next <= config_6502_reg(7);
|
|
|
|
if (request_reset_zpu = '1') then
|
|
reset_n_next <= '0';
|
|
reset_zpu_next <= '1';
|
|
reset_6502_cpu_next <= '1';
|
|
end if;
|
|
end process;
|
|
|
|
-- outputs
|
|
PAUSE_ZPU <= paused_reg;
|
|
LEDG <= ledg_reg;
|
|
LEDR <= ledr_reg;
|
|
|
|
SDCARD_CLK <= spi_clk_out;
|
|
SDCARD_CMD <= spi_mosi;
|
|
spi_miso <= SDCARD_DAT; -- INPUT!! XXX
|
|
SDCARD_DAT3 <= spi_chip_select(0);
|
|
|
|
PAL <= '1'; -- TODO
|
|
--USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
|
|
USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
|
|
RAM_SELECT <= ram_select_reg;
|
|
VGA <= '1';
|
|
COMPOSITE_ON_HSYNC <= '0';
|
|
GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!
|
|
ROM_SELECT <= rom_select_reg;
|
|
|
|
reset_n <= reset_n_reg; -- system reset or pll not locked
|
|
reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
|
|
reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
|
|
|
|
pause_6502 <= config_6502_reg(6); -- zpu software controlled
|
|
|
|
throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled
|
|
|
|
zpu_hex <= zpu_hex_reg;
|
|
|
|
sector <= sector_reg;
|
|
sector_request <= sector_request_reg;
|
|
end vhdl;
|
|
|
|
|