repo2/common/components/generic_ram_infer.vhdl @ 9
| 1 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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ENTITY generic_ram_infer IS
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generic
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(
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ADDRESS_WIDTH : natural := 9;
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SPACE : natural := 512;
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DATA_WIDTH : natural := 8
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);
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PORT
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(
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clock: IN std_logic;
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data: IN std_logic_vector (data_width-1 DOWNTO 0);
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address: IN std_logic_vector(address_width-1 downto 0);
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we: IN std_logic;
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q: OUT std_logic_vector (data_width-1 DOWNTO 0)
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);
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END generic_ram_infer;
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ARCHITECTURE rtl OF generic_ram_infer IS
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| 3 | markw | TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0);
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| 1 | markw | SIGNAL ram_block : mem;
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BEGIN
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PROCESS (clock)
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BEGIN
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IF (clock'event AND clock = '1') THEN
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| 3 | markw | q<= (others=>'1');
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| 4 | markw | IF (to_integer(to_01(unsigned(address))) < space) THEN
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| 3 | markw | IF (we = '1') THEN
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| 4 | markw | ram_block(to_integer(to_01(unsigned(address)))) <= data;
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| 3 | markw | END IF;
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| 4 | markw | q <= ram_block(to_integer(to_01(unsigned(address))));
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| 1 | markw | END IF;
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END IF;
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END PROCESS;
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| 3 | markw | END rtl;
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