Project

General

Profile

« Previous | Next » 

Revision 80

Added by markw about 11 years ago

Allow more than 4 bits of precision

View differences:

common/components/scandoubler.vhdl
use ieee.numeric_std.all;
ENTITY scandoubler IS
--TODO video bits
GENERIC
(
video_bits : integer := 4
);
PORT
(
CLK : IN STD_LOGIC;
......
hsync_in : in std_logic;
-- TO TV...
R : OUT STD_LOGIC_vector(3 downto 0);
G : OUT STD_LOGIC_vector(3 downto 0);
B : OUT STD_LOGIC_vector(3 downto 0);
R : OUT STD_LOGIC_vector(video_bits-1 downto 0);
G : OUT STD_LOGIC_vector(video_bits-1 downto 0);
B : OUT STD_LOGIC_vector(video_bits-1 downto 0);
VSYNC : out std_logic;
HSYNC : out std_logic
......
-- output
-- TODO - for DE2, output full 8 bits
R <= R_reg(7 downto 4);
G <= G_reg(7 downto 4);
B <= B_reg(7 downto 4);
R <= R_reg(7 downto 8-video_bits);
G <= G_reg(7 downto 8-video_bits);
B <= B_reg(7 downto 8-video_bits);
vsync<=vsync_reg;
hsync<=hsync_reg;

Also available in: Unified diff