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Revision 8

Added by markw over 11 years ago

Renamed poly_* to pokey_poly_* since it is part of pokey

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common/a8core/poly_5.vhdl
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY poly_5 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END poly_5;
ARCHITECTURE vhdl OF poly_5 IS
signal shift_reg: std_logic_vector(4 downto 0);
signal shift_next: std_logic_vector(4 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1);
end if;
end process;
-- output
bit_out <= not(shift_reg(0));
END vhdl;
common/a8core/poly_17_9.vhdl
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC;
RAND_OUT : OUT std_logic_vector(7 downto 0)
);
END poly_17_9;
ARCHITECTURE vhdl OF poly_17_9 IS
signal shift_reg: std_logic_vector(16 downto 0);
signal shift_next: std_logic_vector(16 downto 0);
signal feedback : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010101010101010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state (as pokey decap)
feedback <= shift_reg(13) xnor shift_reg(8);
process(enable,shift_reg,feedback,select_9_17,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next(15 downto 8) <= shift_reg(16 downto 9);
shift_next(7) <= feedback;
shift_next(6 downto 0) <= shift_reg(7 downto 1);
shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
end if;
end process;
-- output
bit_out <= shift_reg(9);
RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
END vhdl;
common/a8core/poly_4.vhdl
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY poly_4 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END poly_4;
ARCHITECTURE vhdl OF poly_4 IS
signal shift_reg: std_logic_vector(3 downto 0);
signal shift_next: std_logic_vector(3 downto 0);
BEGIN
-- register
process(clk, reset_n)
begin
if (reset_n = '0') then
shift_reg <= "1010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1);
end if;
end process;
-- output
bit_out <= not(shift_reg(0));
END vhdl;
common/a8core/pokey.vhdl
);
END component;
component poly_17_9 IS
component pokey_poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
......
);
END component;
component poly_5 IS
component pokey_poly_5 IS
PORT
(
CLK : IN STD_LOGIC;
......
);
END component;
component poly_4 IS
component pokey_poly_4 IS
PORT
(
CLK : IN STD_LOGIC;
......
-- Instantiate pokey noise circuits (lfsr)
initmode <= skctl_next(1) nor skctl_next(0);
poly_17_19_lfsr : poly_17_9
poly_17_19_lfsr : pokey_poly_17_9
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,select_9_17=>audctl_reg(7),bit_out=>noise_large,rand_out=>rand_out);
poly_5_lfsr : poly_5
poly_5_lfsr : pokey_poly_5
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_5);
poly_4_lfsr : poly_4
poly_4_lfsr : pokey_poly_4
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4);
--AUDIO_LEFT <= "000"&count_reg(15 downto 3);
common/a8core/pokey_poly_17_9.vhdl
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC;
RAND_OUT : OUT std_logic_vector(7 downto 0)
);
END pokey_poly_17_9;
ARCHITECTURE vhdl OF pokey_poly_17_9 IS
signal shift_reg: std_logic_vector(16 downto 0);
signal shift_next: std_logic_vector(16 downto 0);
signal feedback : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010101010101010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state (as pokey decap)
feedback <= shift_reg(13) xnor shift_reg(8);
process(enable,shift_reg,feedback,select_9_17,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next(15 downto 8) <= shift_reg(16 downto 9);
shift_next(7) <= feedback;
shift_next(6 downto 0) <= shift_reg(7 downto 1);
shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
end if;
end process;
-- output
bit_out <= shift_reg(9);
RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
END vhdl;
common/a8core/pokey_poly_4.vhdl
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_4 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END pokey_poly_4;
ARCHITECTURE vhdl OF pokey_poly_4 IS
signal shift_reg: std_logic_vector(3 downto 0);
signal shift_next: std_logic_vector(3 downto 0);
BEGIN
-- register
process(clk, reset_n)
begin
if (reset_n = '0') then
shift_reg <= "1010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1);
end if;
end process;
-- output
bit_out <= not(shift_reg(0));
END vhdl;
common/a8core/pokey_poly_5.vhdl
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_5 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END pokey_poly_5;
ARCHITECTURE vhdl OF pokey_poly_5 IS
signal shift_reg: std_logic_vector(4 downto 0);
signal shift_next: std_logic_vector(4 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1);
end if;
end process;
-- output
bit_out <= not(shift_reg(0));
END vhdl;
common/zpu/simulate_zpu.sh
cp "../../a8core/pokey_keyboard_scanner.vhdl" .
cp "../../a8core/pokey_countdown_timer.vhdl" .
cp "../../a8core/pokey_noise_filter.vhdl" .
cp "../../a8core/poly_4.vhdl" .
cp "../../a8core/poly_5.vhdl" .
cp "../../a8core/poly_17_9.vhdl" .
cp "../../a8core/pokey_poly_4.vhdl" .
cp "../../a8core/pokey_poly_5.vhdl" .
cp "../../a8core/pokey_poly_17_9.vhdl" .
# set up project definition file
ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat > $name.prj

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