Revision 79
Added by markw over 11 years ago
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-- wsync write takes 1 cycle to assert rdy
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-- TODO - revisit antic delays in terms of cpu cycles
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wsync_delay : delay_line
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--generic map (COUNT=>cycle_length+cycle_length/2)
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generic map (COUNT=>cycle_length+cycle_length-2) -- TODO
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generic map (COUNT=>cycle_length+cycle_length/2)
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--generic map (COUNT=>cycle_length+cycle_length-2) -- TODO
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port map (clk=>clk,sync_reset=>'0',data_in=>wsync_write,enable=>'1',reset_n=>reset_n,data_out=>wsync_delayed_write);
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-- dmactl takes 1 cycle to be applied - NO IT DOES NOT - TODO FIXME
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Not 100% sure why but this change from a while ago breaks the mist and de1 sdram versions. Need to investigate futher but reverting for now.