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Revision 70

Added by markw over 11 years ago

Added ZPU. Added read/write SD support. Fixed joystick. Switched to new mist keyboard mode (ps2 emulation).

View differences:

mist/atari800core.qsf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VHDL_FILE data_io.vhdl
set_global_assignment -name VHDL_FILE zpu_rom.vhdl
set_global_assignment -name SDC_FILE atari800core.sdc
set_global_assignment -name QIP_FILE mist_sector_buffer.qip
set_global_assignment -name VHDL_FILE atari800core_mist.vhd
mist/atari800core_mist.vhd
---------------------------------------------------------------------------
-- (c) 2013 mark watson
--------------------------------------------------------------------------- -- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
......
CORE_TYPE : in std_logic_vector(7 downto 0);
JOY0 : out std_logic_vector(5 downto 0);
JOY1 : out std_logic_vector(5 downto 0);
KEYBOARD : out std_logic_vector(127 downto 0);
BUTTONS : out std_logic_vector(1 downto 0);
SWITCHES : out std_logic_vector(1 downto 0)
SWITCHES : out std_logic_vector(1 downto 0);
CLK : in std_logic;
PS2_CLK : out std_logic;
PS2_DATA : out std_logic
);
end component;
signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
......
signal CLK : std_logic;
signal CLK_SDRAM : std_logic;
signal keyboard : std_logic_vector(127 downto 0);
signal atari_keyboard : std_logic_vector(63 downto 0);
SIGNAL SHIFT_PRESSED : STD_LOGIC;
SIGNAL BREAK_PRESSED : STD_LOGIC;
SIGNAL CONTROL_PRESSED : STD_LOGIC;
SIGNAL PS2_CLK : std_logic;
SIGNAL PS2_DAT : std_logic;
SIGNAL CONSOL_OPTION : STD_LOGIC;
SIGNAL CONSOL_SELECT : STD_LOGIC;
SIGNAL CONSOL_START : STD_LOGIC;
SIGNAL FKEYS : std_logic_vector(11 downto 0);
signal capslock_pressed : std_logic;
signal capsheld_next : std_logic;
......
signal mist_sector_ready_sync : std_logic;
signal mist_sector_request : std_logic;
signal mist_sector_request_sync : std_logic;
signal mist_sector : std_logic_vector(31 downto 0);
signal mist_sector_sync : std_logic_vector(31 downto 0);
signal mist_sector_write : std_logic;
signal mist_sector_write_sync : std_logic;
signal mist_sector : std_logic_vector(23 downto 0);
signal mist_sector_sync : std_logic_vector(23 downto 0);
signal mist_addr : std_logic_vector(8 downto 0);
......
SIGNAL KEYBOARD_RESPONSE : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL KEYBOARD_SCAN : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL THROTTLE_COUNT_6502 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL PAL : std_logic;
signal SDRAM_REQUEST : std_logic;
......
signal SDRAM_REFRESH : std_logic;
signal SYSTEM_RESET_REQUEST: std_logic;
signal SDRAM_RESET_N : std_logic;
-- dma/virtual drive
signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
signal DMA_FETCH : std_logic;
signal DMA_32BIT_WRITE_ENABLE : std_logic;
signal DMA_16BIT_WRITE_ENABLE : std_logic;
signal DMA_8BIT_WRITE_ENABLE : std_logic;
signal DMA_READ_ENABLE : std_logic;
signal DMA_MEMORY_READY : std_logic;
signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
signal ZPU_OUT1 : std_logic_vector(31 downto 0);
signal ZPU_OUT2 : std_logic_vector(31 downto 0);
signal ZPU_OUT3 : std_logic_vector(31 downto 0);
signal ZPU_OUT4 : std_logic_vector(31 downto 0);
signal zpu_pokey_enable : std_logic;
signal zpu_sio_txd : std_logic;
signal zpu_sio_rxd : std_logic;
signal zpu_sio_command : std_logic;
-- system control from zpu
signal ram_select : std_logic_vector(2 downto 0);
signal rom_select : std_logic_vector(5 downto 0);
signal reset_atari : std_logic;
signal pause_atari : std_logic;
SIGNAL speed_6502 : std_logic_vector(5 downto 0);
-- mist sector
signal ZPU_ROM_DATA_MUX : std_logic_vector(31 downto 0);
signal ZPU_SECTOR_DATA : std_logic_vector(31 downto 0);
signal ZPU_ROM_DO : std_logic_vector(31 downto 0);
signal ZPU_ROM_WREN : std_logic;
-- ps2
signal SLOW_PS2_CLK : std_logic; -- around 16KHz
BEGIN
pal <= '1'; -- TODO, two builds, with appropriate pll settings
......
SPI_MOSI => spi_di,
-- Sector access request
request => mist_sector_request_sync,
read_request => mist_sector_request_sync,
write_request => mist_sector_write_sync,
--request => mist_sector_request_sync,
sector => mist_sector_sync(23 downto 0),
ready => mist_sector_ready,
......
select_sync2 : entity work.synchronizer
PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
select_sync3 : entity work.synchronizer
PORT MAP ( CLK => spi_sck, raw => mist_sector_write, sync=>mist_sector_write_sync);
sector_sync0 : entity work.synchronizer
PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
......
PORT map
(
address_a => mist_addr,
address_b => "0000000", -- TODO - need to expose a 2nd dma channel of some kind, so we don't have to halt 6502 to access sector buffer! ZPU_ADDR_ROM_RAM(8 DOWNTO 2),
address_b => zpu_addr_rom(8 downto 2),
clock_a => spi_sck,
clock_b => clk,
data_a => mist_do,
data_b => X"00000000", -- TODO zpu_do,
data_b => dma_write_data(7 downto 0)&dma_write_data(15 downto 8)&dma_write_data(23 downto 16)&dma_write_data(31 downto 24),
wren_a => mist_wren,
wren_b => '0',
wren_b => zpu_rom_wren,
q_a => mist_di,
q_b => open -- TODO zpu_sector_data
q_b => zpu_sector_data
);
my_user_io : user_io
......
CORE_TYPE => x"A4",
JOY0 => joy1,
JOY1 => joy2,
KEYBOARD => keyboard,
BUTTONS => mist_buttons,
SWITCHES => mist_switches
SWITCHES => mist_switches,
CLK => SLOW_PS2_CLK,
PS2_CLK => ps2_clk,
PS2_DATA => ps2_dat
);
joy1_n <= not(joy1(4 downto 0));
joy2_n <= not(joy2(4 downto 0));
process(clk,reset_n)
begin
if (reset_n='0') then
capsheld_reg <= '0';
elsif (clk'event and clk='1') then
capsheld_reg <= capsheld_next;
end if;
end process;
-- TODO, this doesn't work yet
process(keyboard,capsheld_reg)
begin
capsheld_next <= capsheld_reg;
capslock_pressed <= '0';
-- PS2 to pokey
keyboard_map1 : entity work.ps2_to_atari800
PORT MAP
(
CLK => clk,
RESET_N => reset_n,
PS2_CLK => ps2_clk,
PS2_DAT => ps2_dat,
if ((keyboard(58) xor capsheld_reg)='1') then
capsheld_next <= keyboard(58);
-- assert something for 10 frames
capslock_pressed <= '1';
end if;
end process;
-- TODO, this is mapping from ST keycode, make mist firmware send PS2 keycodes or USB keycodes if possible
atari_keyboard(63) <= keyboard(30);
atari_keyboard(62) <= keyboard(31);
atari_keyboard(61) <= keyboard(34);
atari_keyboard(60) <= '0';
atari_keyboard(58) <= keyboard(32);
atari_keyboard(57) <= keyboard(35);
atari_keyboard(56) <= keyboard(33);
atari_keyboard(55) <= keyboard(13);
atari_keyboard(54) <= keyboard(12);
atari_keyboard(53) <= keyboard(9);
atari_keyboard(52) <= keyboard(14);
atari_keyboard(51) <= keyboard(8);
atari_keyboard(50) <= keyboard(11);
atari_keyboard(48) <= keyboard(10);
atari_keyboard(47) <= keyboard(16);
atari_keyboard(46) <= keyboard(17);
atari_keyboard(45) <= keyboard(20);
atari_keyboard(44) <= keyboard(15);
atari_keyboard(43) <= keyboard(21);
atari_keyboard(42) <= keyboard(18);
atari_keyboard(40) <= keyboard(19);
atari_keyboard(39) <= keyboard(56);
atari_keyboard(38) <= keyboard(53);
atari_keyboard(37) <= keyboard(50);
atari_keyboard(35) <= keyboard(49);
atari_keyboard(34) <= keyboard(52);
atari_keyboard(33) <= keyboard(57);
atari_keyboard(32) <= keyboard(51);
atari_keyboard(31) <= keyboard(2);
atari_keyboard(30) <= keyboard(3);
atari_keyboard(29) <= keyboard(6);
atari_keyboard(28) <= keyboard(1);
atari_keyboard(27) <= keyboard(7);
atari_keyboard(26) <= keyboard(4);
atari_keyboard(24) <= keyboard(5);
atari_keyboard(23) <= keyboard(44);
atari_keyboard(22) <= keyboard(45);
atari_keyboard(21) <= keyboard(48);
atari_keyboard(18) <= keyboard(46);
atari_keyboard(17) <= keyboard(59);
atari_keyboard(16) <= keyboard(47);
atari_keyboard(15) <= keyboard(27);
atari_keyboard(14) <= keyboard(26);
atari_keyboard(13) <= keyboard(23);
atari_keyboard(12) <= keyboard(28);
atari_keyboard(11) <= keyboard(22);
atari_keyboard(10) <= keyboard(25);
atari_keyboard(8) <= keyboard(24);
atari_keyboard(7) <= keyboard(41);
atari_keyboard(6) <= keyboard(40);
atari_keyboard(5) <= keyboard(37);
atari_keyboard(2) <= keyboard(39);
atari_keyboard(1) <= keyboard(36);
atari_keyboard(0) <= keyboard(38);
KEYBOARD_SCAN => KEYBOARD_SCAN,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
shift_pressed <= keyboard(54) or keyboard(42);
control_pressed <= keyboard(29);
break_pressed <= keyboard(96); -- TODO - not on st keyboard
consol_start <= keyboard(60); --F2
consol_select <= keyboard(61); --F3
consol_option <= keyboard(62); -- F4
CONSOL_START => CONSOL_START,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_OPTION => CONSOL_OPTION,
--f5 <= keyboard(63);
--f6 <= keyboard(64);
--f7 <= keyboard(65);
--f8 <= keyboard(66);
--f9 <= keyboard(67);
--f10 <= keyboard(68);
--HOT KEYS! Connect to ZPU when present...
--virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
SYSTEM_RESET_REQUEST <= keyboard(63);
-- TODO this should be common, same for PS2 after mapping...
process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
begin
keyboard_response <= (others=>'1');
if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
keyboard_response(0) <= '0';
end if;
if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
keyboard_response(1) <= '0';
end if;
if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
keyboard_response(1) <= '0';
end if;
if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
keyboard_response(1) <= '0';
end if;
end process;
FKEYS => FKEYS
);
dac_left : hq_dac
port map
(
......
dac_out => audio_r
);
-- TODO - mist joystick mapping!
--GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
--fire is bit 4...
mist_pll : entity work.pll
PORT MAP(inclk0 => CLOCK_27(0),
c0 => CLK_SDRAM,
c1 => CLK,
c2 => SDRAM_CLK,
c3 => SLOW_PS2_CLK,
locked => PLL_LOCKED);
reset_n <= PLL_LOCKED;
-- THROTTLE
THROTTLE_COUNT_6502 <= std_logic_vector(to_unsigned(1,6));
atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
GENERIC MAP
(
cycle_length => 32,
internal_rom => 1,
internal_rom => 0,
internal_ram => 0,
video_bits => 6
)
PORT MAP
(
CLK => CLK,
RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
VIDEO_VS => VGA_VS_RAW,
VIDEO_HS => VGA_HS_RAW,
......
AUDIO_L => AUDIO_L_PCM,
AUDIO_R => AUDIO_R_PCM,
JOY1_n => JOY1_n,
JOY2_n => JOY2_n,
JOY1_n => JOY1_n(4)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3),
JOY2_n => JOY2_n(4)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3),
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
SIO_COMMAND => open,
SIO_RXD => '1',
SIO_TXD => open,
SIO_COMMAND => zpu_sio_command,
SIO_RXD => zpu_sio_txd,
SIO_TXD => zpu_sio_rxd,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
......
SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
SDRAM_REFRESH => SDRAM_REFRESH,
DMA_FETCH => '0',
DMA_READ_ENABLE => '0',
DMA_32BIT_WRITE_ENABLE => '0',
DMA_16BIT_WRITE_ENABLE => '0',
DMA_8BIT_WRITE_ENABLE => '0',
DMA_ADDR => (others=>'1'),
DMA_WRITE_DATA => (others=>'1'),
MEMORY_READY_DMA => open,
DMA_FETCH => dma_fetch,
DMA_READ_ENABLE => dma_read_enable,
DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
DMA_ADDR => dma_addr_fetch,
DMA_WRITE_DATA => dma_write_data,
MEMORY_READY_DMA => dma_memory_ready,
DMA_MEMORY_DATA => dma_memory_data,
RAM_SELECT => (others=>'0'),
ROM_SELECT => "000001",
RAM_SELECT => ram_select,
ROM_SELECT => rom_select,
PAL => PAL,
HALT => '0',
THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502
HALT => pause_atari,
THROTTLE_COUNT_6502 => speed_6502
);
sdram_adaptor : entity work.sdram_statemachine
......
)
PORT MAP(CLK_SYSTEM => CLK,
CLK_SDRAM => CLK_SDRAM,
RESET_N => RESET_N and not(SYSTEM_RESET_REQUEST),
RESET_N => RESET_N,
READ_EN => SDRAM_READ_ENABLE,
WRITE_EN => SDRAM_WRITE_ENABLE,
REQUEST => SDRAM_REQUEST,
......
);
SDRAM_A(12) <= '0';
SDRAM_REFRESH <= '0'; -- TODO
--SDRAM_REFRESH <= '0'; -- TODO
-- Until SDRAM enabled... TODO
--SDRAM_nCS <= '1';
......
VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
VGA_VS <= not(VGA_VS_RAW);
zpu: entity work.zpucore
GENERIC MAP
(
platform => 1,
spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
)
PORT MAP
(
-- standard...
CLK => CLK,
RESET_N => RESET_N and sdram_reset_n,
-- dma bus master (with many waitstates...)
ZPU_ADDR_FETCH => dma_addr_fetch,
ZPU_DATA_OUT => dma_write_data,
ZPU_FETCH => dma_fetch,
ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
ZPU_READ_ENABLE => dma_read_enable,
ZPU_MEMORY_READY => dma_memory_ready,
ZPU_MEMORY_DATA => dma_memory_data,
-- rom bus master
-- data on next cycle after addr
ZPU_ADDR_ROM => zpu_addr_rom,
ZPU_ROM_DATA => zpu_rom_data_mux,
ZPU_ROM_WREN => zpu_rom_wren, -- special for mist...
-- spi master
-- not used for mist...
ZPU_SD_DAT0 => '0',
ZPU_SD_CLK => open,
ZPU_SD_CMD => open,
ZPU_SD_DAT3 => open,
-- SIO
-- Ditto for speaking to Atari, we have a built in Pokey
ZPU_POKEY_ENABLE => zpu_pokey_enable,
ZPU_SIO_TXD => zpu_sio_txd,
ZPU_SIO_RXD => zpu_sio_rxd,
ZPU_SIO_COMMAND => zpu_sio_command,
-- external control
-- switches etc. sector DMA blah blah.
ZPU_IN1 => X"00000"&FKEYS,
ZPU_IN2 => X"00000000",
ZPU_IN3 => X"00000000",
ZPU_IN4 => X"000000"&"0000000"&mist_sector_ready_sync,
-- ouputs - e.g. Atari system control, halt, throttle, rom select
ZPU_OUT1 => zpu_out1,
ZPU_OUT2 => zpu_out2,
ZPU_OUT3 => zpu_out3,
ZPU_OUT4 => zpu_out4
);
mist_sector <= zpu_out4(23 downto 0);
mist_sector_request <= zpu_out4(24);
mist_sector_write <= zpu_out4(25);
pause_atari <= zpu_out1(0);
reset_atari <= zpu_out1(1);
speed_6502 <= zpu_out1(7 downto 2);
ram_select <= zpu_out1(10 downto 8);
rom_select <= zpu_out1(16 downto 11);
zpu_rom1: entity work.zpu_rom
port map(
clock => clk,
address => zpu_addr_rom(13 downto 2),
q => zpu_rom_data
);
process(zpu_addr_rom, zpu_rom_data, zpu_sector_data)
begin
zpu_rom_data_mux <= zpu_rom_data;
if (zpu_addr_rom(15 downto 14) = "01") then
zpu_rom_data_mux <= zpu_sector_data(7 downto 0)&zpu_sector_data(15 downto 8)&zpu_sector_data(23 downto 16)&zpu_sector_data(31 downto 24);
end if;
end process;
enable_179_clock_div_zpu_pokey : entity work.enable_divider
generic map (COUNT=>32) -- cycle_length
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
END vhdl;
mist/build.sh
cp data_io.vhdl build
cp user_io.v build
cp mist_sector_buffer.* build
cp zpu_rom.vhdl build
mkdir build/common
mkdir build/common/a8core
mkdir build/common/components
mkdir build/common/zpu
cp ../common/a8core/* ./build/common/a8core
cp ../common/components/* ./build/common/components
cp ../common/zpu/* ./build/common/zpu
cd build
../makeqsf ../atari800core.qsf ./common/a8core ./common/components
../makeqsf ../atari800core.qsf ./common/a8core ./common/components ./common/zpu
quartus_sh --flow compile atari800core
mist/data_io.cmd
#onerror {resume}
# GAME
#=====================
#run 18871970 ns
#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns
#run 200 ms
mist/data_io.vhdl
SPI_MISO: out std_logic;
SPI_MOSI : in std_logic;
-- Sector access request
request : in std_logic;
-- Sector access read_request
read_request : in std_logic;
write_request : in std_logic;
sector : in std_logic_vector(23 downto 0);
ready : out std_logic;
......
signal cnt_next : std_logic_vector(15 downto 0);
signal cnt_reg : std_logic_vector(15 downto 0);
signal data_in_next : std_logic_vector(7 downto 0);
signal data_in_reg : std_logic_vector(7 downto 0);
signal data_out_next : std_logic_vector(7 downto 0);
signal data_out_reg : std_logic_vector(7 downto 0);
......
signal sector_next : std_logic_vector(23 downto 0);
signal sector_reg : std_logic_vector(23 downto 0);
signal request_next : std_logic;
signal request_reg : std_logic;
signal read_request_next : std_logic;
signal read_request_reg : std_logic;
signal write_request_next : std_logic;
signal write_request_reg : std_logic;
signal clk2 : std_logic;
begin
process(clk,reset_n)
clk2 <= clk or spi_ss_io;
process(clk2,reset_n,spi_ss_io)
begin
if (reset_n = '0') then
if (spi_ss_io = '1') then
cnt_reg <= (others=>'0');
cmd_reg <= (others=>'0');
wren_reg <= '0';
elsif (reset_n = '0') then
cnt_reg <= (others=>'0');
cmd_reg <= (others=>'0');
sbuf_reg <= (others=>'0');
addr_reg <= (others => '0');
data_in_reg <= (others => '0');
data_out_reg <= (others => '0');
wren_reg <= '0';
......
transmit_reg <= (others=>'0');
request_reg <= '0';
read_request_reg <= '0';
write_request_reg <= '0';
sector_reg <=(others=>'0');
elsif (clk'event and clk='1') then
elsif (clk2'event and clk2='1') then
cnt_reg <= cnt_next;
cmd_reg <= cmd_next;
sbuf_reg <= sbuf_next;
addr_reg <= addr_next;
data_in_reg <= data_in_next;
data_out_reg <= data_out_next;
wren_reg <= wren_next;
......
transmit_reg <= transmit_next;
request_reg <= request_next;
read_request_reg <= read_request_next;
write_request_reg <= write_request_next;
sector_reg <= sector_next;
end if;
end process;
......
-- select_sync : synchronizer
-- PORT MAP ( CLK => clk, raw => spi_ss_io, sync=>spi_ss_next);
data_in_next <= data_in;
process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, request_reg, ready_reg,request,sector)
process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, write_request_reg, read_request_reg, ready_reg,read_request,write_request,sector,data_in_reg)
begin
cnt_next <= cnt_reg;
sbuf_next <= sbuf_reg;
cmd_next <= cmd_reg;
ready_next <= ready_reg and request; -- stay ready until request cleared (received by other end)
ready_next <= ready_reg and (read_request or write_request); -- stay ready until read_request cleared (received by other end)
transmit_next <= transmit_reg;
......
addr_next <= addr_reg;
sector_next <= sector_reg;
request_next <= request_reg;
read_request_next <= read_request_reg;
write_request_next <= write_request_reg;
--- It polls get_status 10 times a second
--- it uses SPI_SS2 for this
......
sbuf_next(6 downto 1) <= sbuf_reg(5 downto 0);
sbuf_next(0) <= SPI_MOSI;
if (cnt_reg = X"0000") then
addr_next <= (others=>'0');
end if;
if (cnt_reg = X"0007") then
cmd_next(7 downto 1) <= sbuf_reg;
cmd_next(0) <= SPI_MOSI;
addr_next <= (others=>'1');
sector_next <= sector;
request_next <= request;
read_request_next <= read_request;
write_request_next <= write_request;
end if;
--end if;
if (spi_ss_io = '1') then
cnt_next <= (others=>'0');
cmd_next <= (others=>'0');
end if;
case cmd_reg is
when X"50" => --get status
case cnt_reg is
......
when X"0018" =>
transmit_next <= sector_reg(7 downto 0);
when X"0020" =>
transmit_next <= "1010010"&request_reg; --read request
transmit_next <= "101001"&write_request_reg&read_request_reg; --read read_request
when others =>
-- nothing
end case;
when X"51" => --sector read from sd, write it...
if (cnt_reg = X"0008") then
addr_next <= (others=>'1');
end if;
if (cnt_reg(2 downto 0) = "111") then
addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
data_out_next(7 downto 1) <= sbuf_reg;
data_out_next(0) <= SPI_MOSI;
wren_next <= request;
wren_next <= read_request;
if (cnt_reg(12) = '1')then
ready_next <= '1';
end if;
end if;
when X"52" => -- read from write, write to sd
if (cnt_reg(2 downto 0) = "000") then
addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
transmit_next <= data_in_reg;
if (cnt_reg(12) = '1')then
ready_next <= '1';
end if;
end if;
when others =>
-- nop
end case;
end process;
-- outputs
addr <= addr_reg;
data_out <= data_out_reg;
wr_en <= wren_reg;
addr <= addr_next;
data_out <= data_out_next;
wr_en <= wren_next;
ready <= ready_reg;
mist/data_io.wcfg
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="data_io.wdb" id="1" type="auto">
<top_modules>
<top_module name="data_io_tb" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="19" />
<wvobject fp_name="/data_io_tb/reset_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset_n</obj_property>
<obj_property name="ObjectShortName">reset_n</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/request" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">request</obj_property>
<obj_property name="ObjectShortName">request</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">write</obj_property>
<obj_property name="ObjectShortName">write</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ready</obj_property>
<obj_property name="ObjectShortName">ready</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/spi_miso" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_miso</obj_property>
<obj_property name="ObjectShortName">spi_miso</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/spi_mosi" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_mosi</obj_property>
<obj_property name="ObjectShortName">spi_mosi</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/spi_clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_clk</obj_property>
<obj_property name="ObjectShortName">spi_clk</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/spi_tx_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">spi_tx_data[7:0]</obj_property>
<obj_property name="ObjectShortName">spi_tx_data[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/spi_rx_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">spi_rx_data[7:0]</obj_property>
<obj_property name="ObjectShortName">spi_rx_data[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/spi_busy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_busy</obj_property>
<obj_property name="ObjectShortName">spi_busy</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/spi_enable" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_enable</obj_property>
<obj_property name="ObjectShortName">spi_enable</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/data_io/cmd_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cmd_reg[7:0]</obj_property>
<obj_property name="ObjectShortName">cmd_reg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/data_io/cnt_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cnt_reg[15:0]</obj_property>
<obj_property name="ObjectShortName">cnt_reg[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/data_io/sbuf_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sbuf_reg[6:0]</obj_property>
<obj_property name="ObjectShortName">sbuf_reg[6:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr[8:0]</obj_property>
<obj_property name="ObjectShortName">addr[8:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/data_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_out[7:0]</obj_property>
<obj_property name="ObjectShortName">data_out[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[7:0]</obj_property>
<obj_property name="ObjectShortName">data_in[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/wr_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wr_en</obj_property>
<obj_property name="ObjectShortName">wr_en</obj_property>
</wvobject>
<wvobject fp_name="/data_io_tb/spi_ss_io" type="array" db_ref_id="1">
<obj_property name="ElementShortName">spi_ss_io[1:0]</obj_property>
<obj_property name="ObjectShortName">spi_ss_io[1:0]</obj_property>
</wvobject>
</wave_config>
mist/pll.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 256 184)
(text "pll" (rect 122 0 137 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 25 180)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
)
(port
(pt 256 64)
(output)
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 240 50 250 63)(font "Arial" (font_size 8)))
)
(port
(pt 256 80)
(output)
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c1" (rect 240 66 248 79)(font "Arial" (font_size 8)))
)
(port
(pt 256 96)
(output)
(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c2" (rect 240 82 250 95)(font "Arial" (font_size 8)))
)
(port
(pt 256 112)
(output)
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 221 98 250 111)(font "Arial" (font_size 8)))
)
(drawing
(text "Cyclone III" (rect 194 168 433 347)(font "Arial" ))
(text "inclk0 frequency: 27.000 MHz" (rect 50 59 223 129)(font "Arial" ))
(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
(text "Clk " (rect 51 93 116 197)(font "Arial" ))
(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
(text "Ph (dg)" (rect 99 93 227 197)(font "Arial" ))
(text "DC (%)" (rect 134 93 298 197)(font "Arial" ))
(text "c0" (rect 54 107 116 225)(font "Arial" ))
(text "69/16" (rect 72 107 165 225)(font "Arial" ))
(text "0.00" (rect 105 107 226 225)(font "Arial" ))
(text "50.00" (rect 138 107 297 225)(font "Arial" ))
(text "c1" (rect 54 121 115 253)(font "Arial" ))
(text "69/32" (rect 72 121 165 253)(font "Arial" ))
(text "0.00" (rect 105 121 226 253)(font "Arial" ))
(text "50.00" (rect 138 121 297 253)(font "Arial" ))
(text "c2" (rect 54 135 116 281)(font "Arial" ))
(text "69/16" (rect 72 135 165 281)(font "Arial" ))
(text "-100.60" (rect 99 135 227 281)(font "Arial" ))
(text "50.00" (rect 138 135 297 281)(font "Arial" ))
(line (pt 0 0)(pt 257 0))
(line (pt 257 0)(pt 257 185))
(line (pt 0 185)(pt 257 185))
(line (pt 0 0)(pt 0 185))
(line (pt 48 91)(pt 166 91))
(line (pt 48 104)(pt 166 104))
(line (pt 48 118)(pt 166 118))
(line (pt 48 132)(pt 166 132))
(line (pt 48 146)(pt 166 146))
(line (pt 48 91)(pt 48 146))
(line (pt 69 91)(pt 69 146)(line_width 3))
(line (pt 96 91)(pt 96 146)(line_width 3))
(line (pt 131 91)(pt 131 146)(line_width 3))
(line (pt 165 91)(pt 165 146))
(line (pt 40 48)(pt 207 48))
(line (pt 207 48)(pt 207 167))
(line (pt 40 167)(pt 207 167))
(line (pt 40 48)(pt 40 167))
(line (pt 255 64)(pt 207 64))
(line (pt 255 80)(pt 207 80))
(line (pt 255 96)(pt 207 96))
(line (pt 255 112)(pt 207 112))
)
)
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 224 168)
(text "pll" (rect 106 0 120 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 157 22 164)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 22 9)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 55 21 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
)
(port
(pt 224 64)
(output)
(text "c0" (rect 0 0 9 9)(font "Arial" (font_size 8)))
(text "c0" (rect 212 55 218 63)(font "Arial" (font_size 8)))
)
(port
(pt 224 80)
(output)
(text "c1" (rect 0 0 9 9)(font "Arial" (font_size 8)))
(text "c1" (rect 212 71 218 79)(font "Arial" (font_size 8)))
)
(port
(pt 224 96)
(output)
(text "c2" (rect 0 0 9 9)(font "Arial" (font_size 8)))
(text "c2" (rect 212 87 219 95)(font "Arial" (font_size 8)))
)
(port
(pt 224 112)
(output)
(text "c3" (rect 0 0 9 9)(font "Arial" (font_size 8)))
(text "c3" (rect 212 103 218 111)(font "Arial" (font_size 8)))
)
(port
(pt 224 128)
(output)
(text "locked" (rect 0 0 24 9)(font "Arial" (font_size 8)))
(text "locked" (rect 199 119 219 127)(font "Arial" (font_size 8)))
)
(drawing
(text "Cyclone III" (rect 181 161 394 328)(font "Arial" ))
(text "inclk0 frequency: 27.000 MHz" (rect 50 71 191 148)(font "Arial" ))
(text "Operation Mode: Normal" (rect 50 79 175 164)(font "Arial" ))
(text "Clk " (rect 51 92 112 190)(font "Arial" ))
(text "Ratio" (rect 74 92 163 190)(font "Arial" ))
(text "Ph (dg)" (rect 102 92 226 190)(font "Arial" ))
(text "DC (%)" (rect 129 92 279 190)(font "Arial" ))
(text "c0" (rect 53 101 112 208)(font "Arial" ))
(text "69/16" (rect 73 101 162 208)(font "Arial" ))
(text "0.00" (rect 106 101 224 208)(font "Arial" ))
(text "50.00" (rect 131 101 278 208)(font "Arial" ))
(text "c1" (rect 53 110 112 226)(font "Arial" ))
(text "69/32" (rect 73 110 163 226)(font "Arial" ))
(text "0.00" (rect 106 110 224 226)(font "Arial" ))
(text "50.00" (rect 131 110 278 226)(font "Arial" ))
(text "c2" (rect 53 119 113 244)(font "Arial" ))
(text "69/16" (rect 73 119 162 244)(font "Arial" ))
(text "-100.60" (rect 101 119 224 244)(font "Arial" ))
(text "50.00" (rect 131 119 278 244)(font "Arial" ))
(text "c3" (rect 53 128 112 262)(font "Arial" ))
(text "23/32768" (rect 67 128 162 262)(font "Arial" ))
(text "0.00" (rect 106 128 224 262)(font "Arial" ))
(text "50.00" (rect 131 128 278 262)(font "Arial" ))
(line (pt 0 0)(pt 225 0))
(line (pt 225 0)(pt 225 170))
(line (pt 0 170)(pt 225 170))
(line (pt 0 0)(pt 0 170))
(line (pt 48 90)(pt 152 90))
(line (pt 48 98)(pt 152 98))
(line (pt 48 107)(pt 152 107))
(line (pt 48 116)(pt 152 116))
(line (pt 48 125)(pt 152 125))
(line (pt 48 134)(pt 152 134))
(line (pt 48 90)(pt 48 134))
(line (pt 64 90)(pt 64 134)(line_width 3))
(line (pt 98 90)(pt 98 134)(line_width 3))
(line (pt 126 90)(pt 126 134)(line_width 3))
(line (pt 151 90)(pt 151 134))
(line (pt 40 48)(pt 183 48))
(line (pt 183 48)(pt 183 152))
(line (pt 40 152)(pt 183 152))
(line (pt 40 48)(pt 40 152))
(line (pt 223 64)(pt 183 64))
(line (pt 223 80)(pt 183 80))
(line (pt 223 96)(pt 183 96))
(line (pt 223 112)(pt 183 112))
(line (pt 223 128)(pt 183 128))
)
)
mist/pll.cmp
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
mist/pll.ppf
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="c3" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>
mist/pll.qip
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "12.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
mist/pll.vhd
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 16,
clk0_duty_cycle => 50,
clk0_multiply_by => 69,
clk0_phase_shift => "0",
clk1_divide_by => 32,
clk1_duty_cycle => 50,
clk1_multiply_by => 69,
clk1_phase_shift => "0",
clk2_divide_by => 16,
clk2_duty_cycle => 50,
clk2_multiply_by => 69,
clk2_phase_shift => "-2400",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "16"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "32"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "16"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "116.437500"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "58.218750"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "116.437500"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "69"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "69"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "69"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2.40000000"
... This diff was truncated because it exceeds the maximum size that can be displayed.

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