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------------------------------------------------------------------------------
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---- ----
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---- ZPU Package ----
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---- ----
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---- http://www.opencores.org/ ----
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---- ----
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---- Description: ----
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---- ZPU is a 32 bits small stack cpu. This is the package. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author: ----
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---- - Øyvind Harboe, oyvind.harboe zylin.com ----
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---- - Salvador E. Tropea, salvador inti.gob.ar ----
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---- ----
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------------------------------------------------------------------------------
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---- ----
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---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
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---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
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---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
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---- ----
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---- Distributed under the BSD license ----
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---- ----
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------------------------------------------------------------------------------
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---- ----
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---- Design unit: zpupkg, UART (Package) ----
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---- File name: zpu_medium.vhdl ----
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---- Note: None ----
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---- Limitations: None known ----
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---- Errors: None known ----
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---- Library: zpu ----
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---- Dependencies: IEEE.std_logic_1164 ----
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---- IEEE.numeric_std ----
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---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
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---- Language: VHDL ----
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---- Wishbone: No ----
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---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
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---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
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---- Text editor: SETEdit 0.5.x ----
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---- ----
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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package zpupkg is
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constant OPCODE_W : integer:=8;
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-- Debug structure, currently only for the trace module
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type zpu_dbgo_t is record
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b_inst : std_logic;
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opcode : unsigned(OPCODE_W-1 downto 0);
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pc : unsigned(31 downto 0);
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sp : unsigned(31 downto 0);
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stk_a : unsigned(31 downto 0);
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stk_b : unsigned(31 downto 0);
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end record;
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component Trace is
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generic(
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LOG_FILE : string:="trace.txt"; -- Name of the trace file
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ADDR_W : integer:=16; -- Address width
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WORD_SIZE : integer:=32); -- 16/32
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port(
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clk_i : in std_logic;
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dbg_i : in zpu_dbgo_t;
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stop_i : in std_logic;
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busy_i : in std_logic
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);
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end component Trace;
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component ZPUSmallCore is
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generic(
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WORD_SIZE : integer:=32; -- Data width 16/32
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ADDR_W : integer:=16; -- Total address space width (incl. I/O)
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MEM_W : integer:=15; -- Memory (prog+data+stack) width
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D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
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port(
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clk_i : in std_logic; -- System Clock
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reset_i : in std_logic; -- Synchronous Reset
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interrupt_i : in std_logic; -- Interrupt
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break_o : out std_logic; -- Breakpoint opcode executed
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dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
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-- BRAM (text, data, bss and stack)
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a_we_o : out std_logic; -- BRAM A port Write Enable
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a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
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a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
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a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
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b_we_o : out std_logic; -- BRAM B port Write Enable
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b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
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b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
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b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
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-- Memory mapped I/O
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mem_busy_i : in std_logic;
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data_i : in unsigned(WORD_SIZE-1 downto 0);
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data_o : out unsigned(WORD_SIZE-1 downto 0);
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addr_o : out unsigned(ADDR_W-1 downto 0);
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write_en_o : out std_logic;
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read_en_o : out std_logic);
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end component ZPUSmallCore;
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component ZPUMediumCore is
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generic(
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WORD_SIZE : integer:=32; -- Data width 16/32
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ADDR_W : integer:=16; -- Total address space width (incl. I/O)
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MEM_W : integer:=15; -- Memory (prog+data+stack) width
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D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
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MULT_PIPE : boolean:=false; -- Pipeline multiplication
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BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
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ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
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ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
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ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
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ENA_LSHR : boolean:=true; -- lshiftright
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ENA_IDLE : boolean:=false; -- Enable the enable_i input
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FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
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port(
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clk_i : in std_logic; -- CPU Clock
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reset_i : in std_logic; -- Sync Reset
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enable_i : in std_logic; -- Hold the CPU (after reset)
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break_o : out std_logic; -- Break instruction executed
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dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
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-- Memory interface
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mem_busy_i : in std_logic; -- Memory is busy
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data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
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data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
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addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
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write_en_o : out std_logic; -- Memory write enable
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read_en_o : out std_logic); -- Memory read enable
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end component ZPUMediumCore;
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component Timer is
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port(
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clk_i : in std_logic;
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reset_i : in std_logic;
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we_i : in std_logic;
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data_i : in unsigned(31 downto 0);
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addr_i : in unsigned(0 downto 0);
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data_o : out unsigned(31 downto 0));
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end component Timer;
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component gpio is
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port(
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clk_i : in std_logic;
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reset_i : in std_logic;
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--
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we_i : in std_logic;
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data_i : in unsigned(31 downto 0);
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addr_i : in unsigned( 0 downto 0);
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data_o : out unsigned(31 downto 0);
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--
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port_in : in std_logic_vector(31 downto 0);
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port_out : out std_logic_vector(31 downto 0);
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port_dir : out std_logic_vector(31 downto 0)
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);
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end component gpio;
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component ZPUPhiIO is
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generic(
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BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4
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ENA_LOG : boolean:=true; -- Enable log
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LOG_FILE : string:="log.txt"); -- Name for the log file
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port(
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clk_i : in std_logic; -- System Clock
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reset_i : in std_logic; -- Synchronous Reset
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busy_o : out std_logic; -- I/O is busy
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we_i : in std_logic; -- Write Enable
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re_i : in std_logic; -- Read Enable
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data_i : in unsigned(31 downto 0);
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data_o : out unsigned(31 downto 0);
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addr_i : in unsigned(2 downto 0); -- Address bits 4-2
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--
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rs232_rx_i : in std_logic; -- UART Rx input
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rs232_tx_o : out std_logic; -- UART Tx output
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br_clk_i : in std_logic; -- UART base clock (enable)
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--
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gpio_in : in std_logic_vector(31 downto 0);
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gpio_out : out std_logic_vector(31 downto 0);
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gpio_dir : out std_logic_vector(31 downto 0)
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);
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end component ZPUPhiIO;
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-- Opcode decode constants
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-- Note: these are the basic opcodes, always implemented using hardware.
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constant OPCODE_IM : unsigned(7 downto 7):="1";
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constant OPCODE_STORESP : unsigned(7 downto 5):="010";
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constant OPCODE_LOADSP : unsigned(7 downto 5):="011";
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constant OPCODE_EMULATE : unsigned(7 downto 5):="001";
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constant OPCODE_ADDSP : unsigned(7 downto 4):="0001";
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constant OPCODE_SHORT : unsigned(7 downto 4):="0000";
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constant OPCODE_BREAK : unsigned(3 downto 0):="0000";
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constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
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constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010";
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constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011";
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constant OPCODE_POPPC : unsigned(3 downto 0):="0100";
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constant OPCODE_ADD : unsigned(3 downto 0):="0101";
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constant OPCODE_AND : unsigned(3 downto 0):="0110";
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constant OPCODE_OR : unsigned(3 downto 0):="0111";
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constant OPCODE_LOAD : unsigned(3 downto 0):="1000";
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constant OPCODE_NOT : unsigned(3 downto 0):="1001";
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constant OPCODE_FLIP : unsigned(3 downto 0):="1010";
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constant OPCODE_NOP : unsigned(3 downto 0):="1011";
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constant OPCODE_STORE : unsigned(3 downto 0):="1100";
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constant OPCODE_POPSP : unsigned(3 downto 0):="1101";
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constant OPCODE_COMPARE : unsigned(3 downto 0):="1110";
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constant OPCODE_POPINT : unsigned(3 downto 0):="1111";
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-- The following instructions are emulated in the small version and
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-- implemented as hardware in the full version.
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-- The constants correpond to the "emulated" instruction number.
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-- Enabled by the ENA_LEVEL0 generic:
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constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6);
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constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6);
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constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6);
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constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6);
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-- Enabled by the ENA_LEVEL1 generic:
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constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6);
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constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6);
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constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6);
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constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6);
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constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6);
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constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6);
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-- Enabled by the ENA_LEVEL2 generic:
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constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6);
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constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
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constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6);
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constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6);
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-- Enabled by the ENA_LSHR generic:
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constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6);
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-- The following opcodes are always emulated.
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constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6);
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constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6);
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constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6);
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constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6);
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constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6);
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constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6);
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constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6);
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constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6);
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constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6);
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constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6);
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constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6);
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constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6);
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end package zpupkg;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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package UART is
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----------------------
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-- Very simple UART --
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----------------------
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component RxUnit is
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port(
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clk_i : in std_logic; -- System clock signal
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reset_i : in std_logic; -- Reset input (sync)
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enable_i : in std_logic; -- Enable input (rate*4)
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read_i : in std_logic; -- Received Byte Read
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rxd_i : in std_logic; -- RS-232 data input
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rxav_o : out std_logic; -- Byte available
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datao_o : out std_logic_vector(7 downto 0)); -- Byte received
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end component RxUnit;
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component TxUnit is
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port (
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clk_i : in std_logic; -- Clock signal
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reset_i : in std_logic; -- Reset input
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enable_i : in std_logic; -- Enable input
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load_i : in std_logic; -- Load input
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txd_o : out std_logic; -- RS-232 data output
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busy_o : out std_logic; -- Tx Busy
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datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
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end component TxUnit;
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component BRGen is
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generic(
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COUNT : integer range 0 to 65535);-- Count revolution
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port (
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clk_i : in std_logic; -- Clock
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reset_i : in std_logic; -- Reset input
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ce_i : in std_logic; -- Chip Enable
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o_o : out std_logic); -- Output
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end component BRGen;
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end package UART;
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