Revision 7
Added by markw over 11 years ago
| common/a8core/synchronizer.vhdl | ||
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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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||
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-- please contact me for explicit permission at scrameta (gmail).
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||
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY synchronizer IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RAW : IN STD_LOGIC;
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SYNC : OUT STD_LOGIC
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);
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END synchronizer;
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ARCHITECTURE vhdl OF synchronizer IS
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signal ff_next : std_logic_vector(2 downto 0);
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signal ff_reg : std_logic_vector(2 downto 0);
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begin
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-- register
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process(clk)
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begin
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if (clk'event and clk='1') then
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ff_reg <= ff_next;
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end if;
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end process;
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ff_next <= RAW&ff_reg(2 downto 1);
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SYNC <= ff_reg(0);
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end vhdl;
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| common/a8core/generic_ram_infer.vhdl | ||
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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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||
|
-- I am happy for anyone to use this for non-commercial use.
|
||
|
-- If my vhdl files are used commercially or otherwise sold,
|
||
|
-- please contact me for explicit permission at scrameta (gmail).
|
||
|
-- This applies for source and binary form and derived works.
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||
|
---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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ENTITY generic_ram_infer IS
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generic
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(
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ADDRESS_WIDTH : natural := 9;
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SPACE : natural := 512;
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DATA_WIDTH : natural := 8
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);
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PORT
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(
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clock: IN std_logic;
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data: IN std_logic_vector (data_width-1 DOWNTO 0);
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address: IN std_logic_vector(address_width-1 downto 0);
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we: IN std_logic;
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q: OUT std_logic_vector (data_width-1 DOWNTO 0)
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);
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END generic_ram_infer;
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ARCHITECTURE rtl OF generic_ram_infer IS
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TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0);
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SIGNAL ram_block : mem;
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BEGIN
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PROCESS (clock)
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BEGIN
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IF (clock'event AND clock = '1') THEN
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q<= (others=>'1');
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IF (to_integer(to_01(unsigned(address))) < space) THEN
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IF (we = '1') THEN
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ram_block(to_integer(to_01(unsigned(address)))) <= data;
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END IF;
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q <= ram_block(to_integer(to_01(unsigned(address))));
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END IF;
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END IF;
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END PROCESS;
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END rtl;
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| common/a8core/complete_address_decoder.vhdl | ||
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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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|
-- I am happy for anyone to use this for non-commercial use.
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||
|
-- If my vhdl files are used commercially or otherwise sold,
|
||
|
-- please contact me for explicit permission at scrameta (gmail).
|
||
|
-- This applies for source and binary form and derived works.
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||
|
---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY complete_address_decoder IS
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generic (width : natural := 1);
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PORT
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(
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addr_in : in std_logic_vector(width-1 downto 0);
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addr_decoded : out std_logic_vector((2**width)-1 downto 0)
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);
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END complete_address_decoder;
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--ARCHITECTURE vhdl OF complete_address_decoder IS
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--BEGIN
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-- comp_gen:
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-- for i in 0 to ((2**width)-1) generate
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-- addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
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-- end generate;
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--end vhdl;
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architecture tree of complete_address_decoder is
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constant STAGE : natural:=width;
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type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
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signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
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signal a: std_logic_vector(width-1 downto 0) ;
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begin
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a<=addr_in;
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process(a,p)
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begin
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p(stage,0) <= '1';
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for s in stage downto 1 loop
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for r in 0 to (2**(stage-s)-1) loop
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p(s-1,2*r) <= (not a(s-1)) and p(s,r);
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p(s-1,2*r+1) <= a(s-1) and p(s,r);
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end loop;
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end loop;
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for i in 0 to (2**stage-1) loop
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addr_decoded(i) <= p(0,i);
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end loop;
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end process;
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end tree;
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| common/a8core/delay_line.vhdl | ||
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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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||
|
-- If my vhdl files are used commercially or otherwise sold,
|
||
|
-- please contact me for explicit permission at scrameta (gmail).
|
||
|
-- This applies for source and binary form and derived works.
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|
---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY delay_line IS
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generic(COUNT : natural := 1);
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PORT
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(
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CLK : IN STD_LOGIC;
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SYNC_RESET : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
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RESET_N : IN STD_LOGIC;
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DATA_OUT : OUT STD_LOGIC
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);
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END delay_line;
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ARCHITECTURE vhdl OF delay_line IS
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signal shift_reg : std_logic_vector(COUNT-1 downto 0);
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signal shift_next : std_logic_vector(COUNT-1 downto 0);
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BEGIN
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-- register
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process(clk,reset_n)
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begin
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if (reset_N = '0') then
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shift_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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shift_reg <= shift_next;
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end if;
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end process;
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-- shift on enable
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process(shift_reg,enable,data_in,sync_reset)
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begin
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shift_next <= shift_reg;
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if (enable = '1') then
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shift_next <= data_in&shift_reg(COUNT-1 downto 1);
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end if;
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if (sync_reset = '1') then
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shift_next <= (others=>'0');
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end if;
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end process;
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-- output
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data_out <= shift_reg(0) and enable;
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END vhdl;
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| common/a8core/syncreset_enable_divider.vhd | ||
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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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|
-- I am happy for anyone to use this for non-commercial use.
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||
|
-- If my vhdl files are used commercially or otherwise sold,
|
||
|
-- please contact me for explicit permission at scrameta (gmail).
|
||
|
-- This applies for source and binary form and derived works.
|
||
|
---------------------------------------------------------------------------
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|
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY syncreset_enable_divider IS
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generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
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PORT
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(
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CLK : IN STD_LOGIC;
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SYNCRESET : in std_logic;
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RESET_N : IN STD_LOGIC;
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ENABLE_IN : IN STD_LOGIC;
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ENABLE_OUT : OUT STD_LOGIC
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);
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END syncreset_enable_divider;
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ARCHITECTURE vhdl OF syncreset_enable_divider IS
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function log2c(n : integer) return integer is
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variable m,p : integer;
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begin
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m := 0;
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p := 1;
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while p<n loop
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m:=m+1;
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p:=p*2;
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end loop;
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return m;
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end log2c;
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constant WIDTH : natural := log2c(COUNT);
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signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
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signal count_next : std_logic_vector(WIDTH-1 downto 0);
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signal enabled_out_next : std_logic;
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signal enabled_out_reg : std_logic;
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BEGIN
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-- register
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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count_reg <= (others=>'0');
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enabled_out_reg <= '0';
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elsif (clk'event and clk='1') then
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count_reg <= count_next;
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enabled_out_reg <= enabled_out_next;
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end if;
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end process;
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-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
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process(count_reg,enable_in,enabled_out_reg,syncreset)
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begin
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count_next <= count_reg;
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enabled_out_next <= enabled_out_reg;
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if (enable_in = '1') then
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count_next <= std_logic_vector(unsigned(count_reg) + 1);
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enabled_out_next <= '0';
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if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
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count_next <= std_logic_vector(to_unsigned(0,WIDTH));
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enabled_out_next <= '1';
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end if;
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end if;
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if (syncreset='1') then
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count_next <= std_logic_vector(to_unsigned(resetcount,width));
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end if;
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end process;
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-- output
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enable_out <= enabled_out_reg and enable_in;
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END vhdl;
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| common/a8core/countdown_timer.vhdl | ||
|---|---|---|
|
---------------------------------------------------------------------------
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|
-- (c) 2013 mark watson
|
||
|
-- I am happy for anyone to use this for non-commercial use.
|
||
|
-- If my vhdl files are used commercially or otherwise sold,
|
||
|
-- please contact me for explicit permission at scrameta (gmail).
|
||
|
-- This applies for source and binary form and derived works.
|
||
|
---------------------------------------------------------------------------
|
||
|
LIBRARY ieee;
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||
|
USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
|
||
|
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ENTITY pokey_countdown_timer IS
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generic(UNDERFLOW_DELAY : natural := 3);
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PORT
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||
|
(
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CLK : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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ENABLE_UNDERFLOW : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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|
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WR_EN : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
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||
|
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DATA_OUT : OUT STD_LOGIC
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);
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END pokey_countdown_timer;
|
||
|
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ARCHITECTURE vhdl OF pokey_countdown_timer IS
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||
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component delay_line IS
|
||
|
generic(COUNT : natural := 1);
|
||
|
PORT
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||
|
(
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||
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CLK : IN STD_LOGIC;
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SYNC_RESET : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC;
|
||
|
|
||
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ENABLE : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
|
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|
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DATA_OUT : OUT STD_LOGIC
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);
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END component;
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||
|
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function To_Std_Logic(L: BOOLEAN) return std_ulogic is
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begin
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if L then
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return('1');
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else
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return('0');
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|
end if;
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end function To_Std_Logic;
|
||
|
|
||
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signal count_reg : std_logic_vector(7 downto 0);
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signal count_next: std_logic_vector(7 downto 0);
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||
|
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signal underflow : std_logic;
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||
|
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signal count_command : std_logic_vector(1 downto 0);
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||
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signal underflow_command: std_logic_vector(1 downto 0);
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||
|
BEGIN
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||
|
-- Instantiate delay (provides output)
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||
|
underflow0_delay : delay_line
|
||
|
generic map (COUNT=>UNDERFLOW_DELAY)
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||
|
port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
|
||
|
|
||
|
-- register
|
||
|
process(clk,reset_n)
|
||
|
begin
|
||
|
if (reset_N = '0') then
|
||
|
count_reg <= (others=>'0');
|
||
|
elsif (clk'event and clk='1') then
|
||
|
count_reg <= count_next;
|
||
|
end if;
|
||
|
end process;
|
||
|
|
||
|
-- count down on enable
|
||
|
process(count_reg,enable,wr_en,count_command,data_in)
|
||
|
begin
|
||
|
count_command <= enable&wr_en;
|
||
|
case count_command is
|
||
|
when "10" =>
|
||
|
count_next <= std_logic_vector(unsigned(count_reg) -1);
|
||
|
when "01"|"11" =>
|
||
|
count_next <= data_in;
|
||
|
when others =>
|
||
|
count_next <= count_reg;
|
||
|
end case;
|
||
|
end process;
|
||
|
|
||
|
-- underflow
|
||
|
process(count_reg,enable,underflow_command)
|
||
|
begin
|
||
|
underflow_command <= enable & To_Std_Logic(count_reg = X"00");
|
||
|
case underflow_command is
|
||
|
when "11" =>
|
||
|
underflow <= '1';
|
||
|
when others =>
|
||
|
underflow <= '0';
|
||
|
end case;
|
||
|
end process;
|
||
|
|
||
|
END vhdl;
|
||
| common/zpu/zpu_rom.vhdl | ||
|---|---|---|
|
|
||
|
--
|
||
|
--ROMsUsingBlockRAMResources.
|
||
|
--VHDLcodeforaROMwithregisteredoutput(template2)
|
||
|
--
|
||
|
library ieee;
|
||
|
use ieee.std_logic_1164.all;
|
||
|
use ieee.std_logic_unsigned.all;
|
||
|
|
||
|
entity zpu_rom is
|
||
|
port(
|
||
|
clock:in std_logic;
|
||
|
address:in std_logic_vector(11 downto 0);
|
||
|
q:out std_logic_vector(31 downto 0)
|
||
|
);
|
||
|
end zpu_rom;
|
||
|
|
||
|
architecture syn of zpu_rom is
|
||
|
type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
|
||
|
signal ROM:rom_type:=
|
||
|
(
|
||
|
X"0b0b0b89",
|
||
|
X"ab040b0b",
|
||
|
X"0b0b0b0b",
|
||
|
X"0b0b0b0b",
|
||
|
X"0b0b0b0b",
|
||
|
X"0b0b0b0b",
|
||
|
X"0b0b0b0b",
|
||
|
X"0b0b0b0b",
|
||
|
X"0b0b0b0b",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"71fd0608",
|
||
|
X"72830609",
|
||
|
X"81058205",
|
||
|
X"832b2a83",
|
||
|
X"ffff0652",
|
||
|
X"04000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"71fd0608",
|
||
|
X"83ffff73",
|
||
|
X"83060981",
|
||
|
X"05820583",
|
||
|
X"2b2b0906",
|
||
|
X"7383ffff",
|
||
|
X"0b0b0b0b",
|
||
|
X"83a70400",
|
||
|
X"72098105",
|
||
|
X"72057373",
|
||
|
X"09060906",
|
||
|
X"73097306",
|
||
|
X"070a8106",
|
||
|
X"53510400",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"72722473",
|
||
|
X"732e0753",
|
||
|
X"51040000",
|
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Also available in: Unified diff
Cleaned up ZPU into slightly more generic form, though still clearly atari core targetted. Added inital tb, though needs rom to verify more. MIST sector side removed, but should be possible with external changes. Now ZPU instead has lots of GPIO.