Latest 65816 changes from Robs github
Board has CE2, not CE_N connected to this pin. So need to use 1 to enable sram.
Back off by 2 cycles, make it more reliable (was missing some eclairexl writes)
Plugged in the sram model to check timings
Need to review further, but these changes seem to bring the 65816 core to life somewhat
Added testbenches. Do not respond to bus cycles that do not target the cart
sram model for tb
Moved memory timing bridge inside slave_timing, its an internal detail really
Adjusted delays and verified in sim
Trivial but important fixes, thanks to quartus warnings
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