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Revision 67

Added by markw over 11 years ago

Added simple dma for faster sd card reading

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common/zpu/zpu_config_regs.vhdl
SDCARD_CMD : out std_logic;
SDCARD_DAT : in std_logic;
SDCARD_DAT3 : out std_logic;
-- SD DMA
sd_addr : out std_logic_vector(15 downto 0);
sd_data : out std_logic_vector(7 downto 0);
sd_write : out std_logic;
-- ATARI interface (in future we can also turbo load by directly hitting memory...)
SIO_DATA_IN : out std_logic;
......
signal pause_reg : std_logic_vector(31 downto 0);
signal paused_next : std_logic;
signal paused_reg : std_logic;
signal spi_dma_addr_next : std_logic_vector(15 downto 0);
signal spi_dma_addrend_next : std_logic_vector(15 downto 0);
signal spi_dma_wr : std_logic;
signal spi_dma_next : std_logic;
signal spi_dma_addr_reg : std_logic_vector(15 downto 0);
signal spi_dma_addrend_reg : std_logic_vector(15 downto 0);
signal spi_dma_reg : std_logic;
begin
-- register
process(clk,reset_n)
......
pause_reg <= (others=>'0');
paused_reg <= '0';
spi_dma_addr_reg <= (others=>'0');
spi_dma_addrend_reg <= (others=>'0');
spi_dma_reg <= '0';
elsif (clk'event and clk='1') then
out1_reg <= out1_next;
out2_reg <= out2_next;
......
pause_reg <= pause_next;
paused_reg <= paused_next;
spi_dma_addr_reg <= spi_dma_addr_next;
spi_dma_addrend_reg <= spi_dma_addrend_next;
spi_dma_reg <= spi_dma_next;
end if;
end process;
......
-- 12: TYPE
-- FPGA board (DONE)
-- R(32 bits) 0=DE1
-- 13 : SPI_DMA
-- W(15 downto 0 = addr),(31 downto 16 = endAddr)
-- 16-31: POKEY! Low bytes only... i.e. pokey reg every 4 bytes...
-- Writes to registers
process(cpu_data_in,wr_en,addr,addr_decoded, spi_speed_reg, spi_addr_reg, out1_reg, out2_reg, out3_reg, out4_reg, pause_reg, pokey_enable)
process(cpu_data_in,wr_en,addr,addr_decoded, spi_speed_reg, spi_addr_reg, out1_reg, out2_reg, out3_reg, out4_reg, pause_reg, pokey_enable, spi_dma_addr_reg, spi_dma_addrend_reg, spi_dma_reg, spi_busy, spi_dma_addr_next)
begin
spi_speed_next <= spi_speed_reg;
spi_addr_next <= spi_addr_reg;
......
out2_next <= out2_reg;
out3_next <= out3_reg;
out4_next <= out4_reg;
paused_next <= '0';
pause_next <= pause_reg;
if (not(pause_reg = X"00000000")) then
......
end if;
paused_next <= '1';
end if;
spi_dma_addr_next <= spi_dma_addr_reg;
spi_dma_addrend_next <= spi_dma_addrend_reg;
spi_dma_wr <= '0';
spi_dma_next <= spi_dma_reg;
if (spi_dma_reg = '1') then
paused_next <= '1';
if (spi_busy = '0') then
spi_dma_wr <= '1';
spi_dma_addr_next <= std_logic_vector(unsigned(spi_dma_addr_reg)+1);
spi_dma_next <= '0';
if (not(spi_dma_addr_next = spi_dma_addrend_reg)) then
spi_tx_data <= X"ff";
spi_enable <= '1';
spi_dma_next <= '1';
end if;
end if;
end if;
if (wr_en = '1' and addr(4) = '0') then
if(addr_decoded(4) = '1') then
......
spi_speed_next <= std_logic_vector(to_unsigned(spi_clock_div,8)); -- turbo - up to 25MHz for SD, 20MHz for MMC I believe... If 1 then clock is half input, if 2 then clock is 1/4 input etc.
end if;
end if;
if(addr_decoded(13) = '1') then
paused_next <= '1';
spi_dma_addr_next <= cpu_data_in(15 downto 0);
spi_dma_addrend_next <= cpu_data_in(31 downto 16);
spi_dma_next <= '1';
spi_tx_data <= X"ff";
spi_enable <= '1';
end if;
end if;
end process;
......
SDCARD_CMD <= spi_mosi;
spi_miso <= SDCARD_DAT; -- INPUT!! XXX
SDCARD_DAT3 <= spi_chip_select(0);
sd_addr <= spi_dma_addr_reg;
sd_data <= spi_rx_data;
sd_write <= spi_dma_wr;
end vhdl;
common/zpu/zpu_glue.vhdl
ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, memORY_ACCESS,
process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, special_mem, memORY_ACCESS,
zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp,
zpu_do_unsigned, zpu_do_reg
common/zpu/zpucore.vhd
signal ZPU_CONFIG_DO : std_logic_vector(31 downto 0);
signal ZPU_CONFIG_WRITE_ENABLE : std_logic;
signal ZPU_SD_DMA_ADDR : std_logic_vector(15 downto 0);
signal ZPU_SD_DMA_DATA : std_logic_vector(7 downto 0);
signal ZPU_SD_DMA_WRITE : std_logic;
signal ZPU_SD_DMA_WRITE_BITS : std_logic_vector(3 downto 0);
signal ZPU_ADDR_ROM_RAM_DMA : std_logic_vector(15 downto 0);
signal ZPU_DO_DMA : std_logic_vector(31 downto 0);
signal ZPU_STACK_WRITE_DMA : std_logic_vector(3 downto 0);
BEGIN
ZPU_RESET <= not(reset_n);
......
SIO_DATA_IN => ZPU_SIO_TXD,
SIO_DATA_OUT => ZPU_SIO_RXD,
SIO_COMMAND => ZPU_SIO_COMMAND,
sd_addr => ZPU_SD_DMA_ADDR,
sd_data => ZPU_SD_DMA_DATA,
sd_write => ZPU_SD_DMA_WRITE,
DATA_OUT => ZPU_CONFIG_DO,
PAUSE_ZPU => ZPU_PAUSE
);
decode_addr1 : entity work.complete_address_decoder
generic map(width=>2)
port map (addr_in=>ZPU_SD_DMA_ADDR(1 downto 0), addr_decoded=>ZPU_SD_DMA_WRITE_BITS);
process(ZPU_DO, ZPU_ADDR_ROM_RAM, ZPU_STACK_WRITE, ZPU_SD_DMA_ADDR, ZPU_SD_DMA_DATA, ZPU_SD_DMA_WRITE, ZPU_SD_DMA_WRITE_BITS)
begin
ZPU_DO_DMA <= ZPU_DO;
ZPU_ADDR_ROM_RAM_DMA <= ZPU_ADDR_ROM_RAM;
ZPU_STACK_WRITE_DMA <= ZPU_STACK_WRITE;
if (ZPU_SD_DMA_WRITE = '1') then
ZPU_DO_DMA <= ZPU_SD_DMA_DATA&ZPU_SD_DMA_DATA&ZPU_SD_DMA_DATA&ZPU_SD_DMA_DATA;
ZPU_ADDR_ROM_RAM_DMA <= ZPU_SD_DMA_ADDR(15 downto 2)&"00";
ZPU_STACK_WRITE_DMA <= ZPU_SD_DMA_WRITE_BITS(0)&ZPU_SD_DMA_WRITE_BITS(1)&ZPU_SD_DMA_WRITE_BITS(2)&ZPU_SD_DMA_WRITE_BITS(3);
end if;
end process;
ram_31_24 : entity work.generic_ram_infer
GENERIC MAP
(
......
)
PORT MAP
(
we => ZPU_STACK_WRITE(3),
we => ZPU_STACK_WRITE_DMA(3),
clock => CLK,
address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
data => ZPU_DO(31 DOWNTO 24),
address => ZPU_ADDR_ROM_RAM_DMA(11 DOWNTO 2),
data => ZPU_DO_DMA(31 DOWNTO 24),
q => ZPU_RAM_DATA(31 DOWNTO 24)
);
......
)
PORT MAP
(
we => ZPU_STACK_WRITE(2),
we => ZPU_STACK_WRITE_DMA(2),
clock => CLK,
address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
data => ZPU_DO(23 DOWNTO 16),
address => ZPU_ADDR_ROM_RAM_DMA(11 DOWNTO 2),
data => ZPU_DO_DMA(23 DOWNTO 16),
q => ZPU_RAM_DATA(23 DOWNTO 16)
);
......
)
PORT MAP
(
we => ZPU_STACK_WRITE(1),
we => ZPU_STACK_WRITE_DMA(1),
clock => CLK,
address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
data => ZPU_DO(15 DOWNTO 8),
address => ZPU_ADDR_ROM_RAM_DMA(11 DOWNTO 2),
data => ZPU_DO_DMA(15 DOWNTO 8),
q => ZPU_RAM_DATA(15 DOWNTO 8)
);
......
)
PORT MAP
(
we => ZPU_STACK_WRITE(0),
we => ZPU_STACK_WRITE_DMA(0),
clock => CLK,
address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
data => ZPU_DO(7 DOWNTO 0),
address => ZPU_ADDR_ROM_RAM_DMA(11 DOWNTO 2),
data => ZPU_DO_DMA(7 DOWNTO 0),
q => ZPU_RAM_DATA(7 DOWNTO 0)
);

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