repo2/de1/defunct/flashrom.vhdl @ 57
| 1 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY flashrom IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
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REQUEST : IN STD_LOGIC;
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-- takes 90+ns, wait states handled here
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-- Flash interface
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FLASH_D : IN STD_LOGIC_VECTOR(7 downto 0);
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FLASH_CE_N : OUT STD_LOGIC;
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FLASH_OE_N : OUT STD_LOGIC;
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FLASH_WE_N : OUT STD_LOGIC;
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FLASH_RESET_N : OUT STD_LOGIC;
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FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 downto 0);
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-- Provide data to system
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DOUT : OUT STD_LOGIC_VECTOR(7 downto 0);
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COMPLETE : OUT STD_LOGIC
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);
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END flashrom;
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ARCHITECTURE vhdl OF flashrom IS
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signal complete_next : std_logic_vector(4 downto 0); --56MHZ, 17ns per cycle.
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signal complete_reg : std_logic_vector(4 downto 0);
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BEGIN
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-- registers
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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complete_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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complete_reg <= complete_next;
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end if;
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end process;
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complete_next <= request&complete_reg(complete_reg'left downto 1);
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FLASH_CE_N <= '0';
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FLASH_OE_N <= '0';
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FLASH_WE_N <= '1';
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FLASH_RESET_N <= RESET_N;
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FLASH_ADDRESS <= ADDRESS;
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DOUT <= FLASH_D;
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COMPLETE <= complete_reg(0);
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END vhdl;
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