Revision 56
Added by markw over 11 years ago
common/a8core/antic.vhdl | ||
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begin
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increment_refresh_count <= '0';
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refresh_pending_next <= refresh_pending_reg;
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refresh_fetch_next <= '0';
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refresh_fetch_next <= refresh_fetch_reg;
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if (colour_clock_1x = '1') then
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if (colour_clock_1x = '1' and hcount_reg(0) = '0') then
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refresh_fetch_next <= '0';
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-- do pending refresh once we have a spare cycle
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if (refresh_pending_reg='1' and (dma_fetch_next='0' or allow_real_dma_next='0') and hcount_reg(0) = '0') then
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if (refresh_pending_reg='1' and (dma_fetch_next='0' or allow_real_dma_next='0')) then
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refresh_fetch_next <= '1';
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refresh_pending_next <= '0';
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end if;
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-- do scheduled refresh - if block, enable pending one
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if (hcount_reg(2 downto 0) = "010" and unsigned(refresh_count_reg)<9) then
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if (hcount_reg(2 downto 1) = "01" and unsigned(refresh_count_reg)<9) then
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increment_refresh_count <= '1';
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refresh_fetch_next <= not(dma_fetch_next);
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refresh_pending_next <= dma_fetch_next;
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... | ... | |
end if;
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end process;
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process(refresh_fetch_next)
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begin
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end process;
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-- nmi handling
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-- edge senstive, single cycle is enough (unless cpu disabled or clashes)
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-- antic asserts for 2 old cycles - if we stick to that then in turbo mode it fixes most nmi bugs, in normal mode they still exist... which is the goal.
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common/a8core/atari800core.vhd | ||
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-- ANTIC lightpen
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ANTIC_LIGHTPEN : IN std_logic;
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ANTIC_REFRESH : out STD_LOGIC; -- 1 cycle high when antic doing refresh cycle..., propose locking out for the next 'cycle_length'
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ANTIC_REFRESH : out STD_LOGIC; -- 1 'original' cycle high when antic doing refresh cycle...
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-----------------------
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-- After here all FPGA implementation specific
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common/a8core/atari800core_simple_sdram.vhd | ||
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-- ANTIC
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signal ANTIC_LIGHTPEN : std_logic;
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signal ANTIC_REFRESH : std_logic;
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signal ANTIC_REFRESH_END : std_logic;
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signal SDRAM_REFRESH_NEXT : std_logic;
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signal SDRAM_REFRESH_REG : std_logic;
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-- CARTRIDGE ACCESS
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SIGNAL CART_RD4 : STD_LOGIC;
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... | ... | |
-- ANTIC lightpen
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ANTIC_LIGHTPEN <= JOY2_n(4) and JOY1_n(4);
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-- ANTIC REFRESH - provide hint to SDRAM of a good time to refresh
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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SDRAM_REFRESH_REG <= '0';
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elsif (clk'event and clk='1') then
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SDRAM_REFRESH_REG <= SDRAM_REFRESH_NEXT;
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end if;
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end process;
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process(ANTIC_REFRESH, ANTIC_REFRESH_END, SDRAM_REFRESH_REG)
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begin
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SDRAM_REFRESH_NEXT <= SDRAM_REFRESH_REG;
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if (ANTIC_REFRESH = '1') then
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SDRAM_REFRESH_NEXT <= '1';
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end if;
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if (ANTIC_REFRESH_END = '1') then
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SDRAM_REFRESH_NEXT <= '0';
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end if;
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end process;
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refresh_delay : entity work.delay_line
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generic map (COUNT=>cycle_length)
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port map(clk=>clk,sync_reset=>'0',data_in=>ANTIC_REFRESH,enable=>'1',reset_n=>reset_n,data_out=>ANTIC_REFRESH_END);
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SDRAM_REFRESH <= SDRAM_REFRESH_NEXT;
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-- GTIA triggers
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GTIA_TRIG <= CART_RD5&"1"&JOY2_n(4)&JOY1_n(4);
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... | ... | |
GTIA_TRIG => GTIA_TRIG,
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ANTIC_LIGHTPEN => ANTIC_LIGHTPEN,
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ANTIC_REFRESH => ANTIC_REFRESH,
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ANTIC_REFRESH => SDRAM_REFRESH,
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SDRAM_REQUEST => SDRAM_REQUEST,
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SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
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Also available in: Unified diff
Antic refresh always takes one original cycle - this fixes turbo mode up to 4x on mcc