EclaireXL

Plugged in the sram model to check timings

Need to review further, but these changes seem to bring the 65816 core to life somewhat

Added testbenches. Do not respond to bus cycles that do not target the cart

sram model for tb

Moved memory timing bridge inside slave_timing, its an internal detail really

Adjusted delays and verified in sim

Trivial but important fixes, thanks to quartus warnings

70ns accuracy is not enough for reliable Atari bus sampling, use faster clock we are already using for sram

Register bus_data before we write it

Fixed c0 decode and made more explicit