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--IP Functional Simulation Model
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--VERSION_BEGIN 14.0 cbx_mgl 2014:06:05:10:17:12:SJ cbx_simgen 2014:06:05:09:45:41:SJ VERSION_END
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-- Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, the Altera Quartus II License Agreement,
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-- the Altera MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Altera and sold by Altera or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-- You may only use these simulation model output files for simulation
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-- purposes and expressly not for synthesis or any other purposes (in which
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-- event Altera disclaims all warranties of any kind).
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--synopsys translate_off
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LIBRARY altera_lnsim;
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USE altera_lnsim.altera_lnsim_components.all;
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--synthesis_resources = altera_pll 1
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY pll IS
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PORT
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(
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locked : OUT STD_LOGIC;
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outclk_0 : OUT STD_LOGIC;
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outclk_1 : OUT STD_LOGIC;
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outclk_2 : OUT STD_LOGIC;
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refclk : IN STD_LOGIC;
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rst : IN STD_LOGIC
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);
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END pll;
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ARCHITECTURE RTL OF pll IS
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ATTRIBUTE synthesis_clearbox : natural;
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ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
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SIGNAL wire_gnd : STD_LOGIC;
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SIGNAL wire_pll_altera_pll_altera_pll_i_1557_locked : STD_LOGIC;
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SIGNAL wire_pll_altera_pll_altera_pll_i_1557_outclk : STD_LOGIC_VECTOR (2 DOWNTO 0);
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BEGIN
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wire_gnd <= '0';
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locked <= wire_pll_altera_pll_altera_pll_i_1557_locked;
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outclk_0 <= wire_pll_altera_pll_altera_pll_i_1557_outclk(0);
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outclk_1 <= wire_pll_altera_pll_altera_pll_i_1557_outclk(1);
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outclk_2 <= wire_pll_altera_pll_altera_pll_i_1557_outclk(2);
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pll_altera_pll_altera_pll_i_1557 : altera_pll
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GENERIC MAP (
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c_cnt_bypass_en0 => "false",
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c_cnt_bypass_en1 => "false",
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c_cnt_bypass_en10 => "false",
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c_cnt_bypass_en11 => "false",
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c_cnt_bypass_en12 => "false",
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c_cnt_bypass_en13 => "false",
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c_cnt_bypass_en14 => "false",
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c_cnt_bypass_en15 => "false",
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c_cnt_bypass_en16 => "false",
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c_cnt_bypass_en17 => "false",
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c_cnt_bypass_en2 => "false",
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c_cnt_bypass_en3 => "false",
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c_cnt_bypass_en4 => "false",
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c_cnt_bypass_en5 => "false",
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c_cnt_bypass_en6 => "false",
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c_cnt_bypass_en7 => "false",
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c_cnt_bypass_en8 => "false",
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c_cnt_bypass_en9 => "false",
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c_cnt_hi_div0 => 1,
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c_cnt_hi_div1 => 1,
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c_cnt_hi_div10 => 1,
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c_cnt_hi_div11 => 1,
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c_cnt_hi_div12 => 1,
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c_cnt_hi_div13 => 1,
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c_cnt_hi_div14 => 1,
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c_cnt_hi_div15 => 1,
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c_cnt_hi_div16 => 1,
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c_cnt_hi_div17 => 1,
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c_cnt_hi_div2 => 1,
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c_cnt_hi_div3 => 1,
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c_cnt_hi_div4 => 1,
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c_cnt_hi_div5 => 1,
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c_cnt_hi_div6 => 1,
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c_cnt_hi_div7 => 1,
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c_cnt_hi_div8 => 1,
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c_cnt_hi_div9 => 1,
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c_cnt_in_src0 => "ph_mux_clk",
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c_cnt_in_src1 => "ph_mux_clk",
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c_cnt_in_src10 => "ph_mux_clk",
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c_cnt_in_src11 => "ph_mux_clk",
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c_cnt_in_src12 => "ph_mux_clk",
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c_cnt_in_src13 => "ph_mux_clk",
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c_cnt_in_src14 => "ph_mux_clk",
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c_cnt_in_src15 => "ph_mux_clk",
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c_cnt_in_src16 => "ph_mux_clk",
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c_cnt_in_src17 => "ph_mux_clk",
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c_cnt_in_src2 => "ph_mux_clk",
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c_cnt_in_src3 => "ph_mux_clk",
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c_cnt_in_src4 => "ph_mux_clk",
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c_cnt_in_src5 => "ph_mux_clk",
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c_cnt_in_src6 => "ph_mux_clk",
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c_cnt_in_src7 => "ph_mux_clk",
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c_cnt_in_src8 => "ph_mux_clk",
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c_cnt_in_src9 => "ph_mux_clk",
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c_cnt_lo_div0 => 1,
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c_cnt_lo_div1 => 1,
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c_cnt_lo_div10 => 1,
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c_cnt_lo_div11 => 1,
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c_cnt_lo_div12 => 1,
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c_cnt_lo_div13 => 1,
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c_cnt_lo_div14 => 1,
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c_cnt_lo_div15 => 1,
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c_cnt_lo_div16 => 1,
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c_cnt_lo_div17 => 1,
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c_cnt_lo_div2 => 1,
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c_cnt_lo_div3 => 1,
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c_cnt_lo_div4 => 1,
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c_cnt_lo_div5 => 1,
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c_cnt_lo_div6 => 1,
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c_cnt_lo_div7 => 1,
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c_cnt_lo_div8 => 1,
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c_cnt_lo_div9 => 1,
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c_cnt_odd_div_duty_en0 => "false",
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c_cnt_odd_div_duty_en1 => "false",
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c_cnt_odd_div_duty_en10 => "false",
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c_cnt_odd_div_duty_en11 => "false",
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c_cnt_odd_div_duty_en12 => "false",
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c_cnt_odd_div_duty_en13 => "false",
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c_cnt_odd_div_duty_en14 => "false",
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c_cnt_odd_div_duty_en15 => "false",
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c_cnt_odd_div_duty_en16 => "false",
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c_cnt_odd_div_duty_en17 => "false",
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c_cnt_odd_div_duty_en2 => "false",
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c_cnt_odd_div_duty_en3 => "false",
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c_cnt_odd_div_duty_en4 => "false",
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c_cnt_odd_div_duty_en5 => "false",
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c_cnt_odd_div_duty_en6 => "false",
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c_cnt_odd_div_duty_en7 => "false",
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c_cnt_odd_div_duty_en8 => "false",
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c_cnt_odd_div_duty_en9 => "false",
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c_cnt_ph_mux_prst0 => 0,
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c_cnt_ph_mux_prst1 => 0,
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c_cnt_ph_mux_prst10 => 0,
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c_cnt_ph_mux_prst11 => 0,
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c_cnt_ph_mux_prst12 => 0,
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c_cnt_ph_mux_prst13 => 0,
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c_cnt_ph_mux_prst14 => 0,
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c_cnt_ph_mux_prst15 => 0,
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c_cnt_ph_mux_prst16 => 0,
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c_cnt_ph_mux_prst17 => 0,
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c_cnt_ph_mux_prst2 => 0,
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c_cnt_ph_mux_prst3 => 0,
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c_cnt_ph_mux_prst4 => 0,
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c_cnt_ph_mux_prst5 => 0,
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c_cnt_ph_mux_prst6 => 0,
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c_cnt_ph_mux_prst7 => 0,
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c_cnt_ph_mux_prst8 => 0,
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c_cnt_ph_mux_prst9 => 0,
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c_cnt_prst0 => 1,
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c_cnt_prst1 => 1,
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c_cnt_prst10 => 1,
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c_cnt_prst11 => 1,
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c_cnt_prst12 => 1,
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c_cnt_prst13 => 1,
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c_cnt_prst14 => 1,
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c_cnt_prst15 => 1,
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c_cnt_prst16 => 1,
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c_cnt_prst17 => 1,
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c_cnt_prst2 => 1,
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c_cnt_prst3 => 1,
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c_cnt_prst4 => 1,
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c_cnt_prst5 => 1,
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c_cnt_prst6 => 1,
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c_cnt_prst7 => 1,
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c_cnt_prst8 => 1,
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c_cnt_prst9 => 1,
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clock_name_0 => "UNUSED",
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clock_name_1 => "UNUSED",
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clock_name_2 => "UNUSED",
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clock_name_3 => "UNUSED",
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clock_name_4 => "UNUSED",
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clock_name_5 => "UNUSED",
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clock_name_6 => "UNUSED",
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clock_name_7 => "UNUSED",
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clock_name_8 => "UNUSED",
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clock_name_global_0 => "false",
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clock_name_global_1 => "false",
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clock_name_global_2 => "false",
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clock_name_global_3 => "false",
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clock_name_global_4 => "false",
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clock_name_global_5 => "false",
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clock_name_global_6 => "false",
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clock_name_global_7 => "false",
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clock_name_global_8 => "false",
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data_rate => 0,
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deserialization_factor => 4,
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duty_cycle0 => 50,
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duty_cycle1 => 50,
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duty_cycle10 => 50,
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duty_cycle11 => 50,
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duty_cycle12 => 50,
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duty_cycle13 => 50,
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duty_cycle14 => 50,
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duty_cycle15 => 50,
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duty_cycle16 => 50,
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duty_cycle17 => 50,
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duty_cycle2 => 50,
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duty_cycle3 => 50,
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duty_cycle4 => 50,
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duty_cycle5 => 50,
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duty_cycle6 => 50,
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duty_cycle7 => 50,
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duty_cycle8 => 50,
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duty_cycle9 => 50,
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fractional_vco_multiplier => "false",
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m_cnt_bypass_en => "false",
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m_cnt_hi_div => 1,
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m_cnt_lo_div => 1,
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m_cnt_odd_div_duty_en => "false",
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mimic_fbclk_type => "gclk",
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n_cnt_bypass_en => "false",
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n_cnt_hi_div => 1,
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n_cnt_lo_div => 1,
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n_cnt_odd_div_duty_en => "false",
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number_of_clocks => 3,
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operation_mode => "normal",
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output_clock_frequency0 => "113.500000 MHz",
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output_clock_frequency1 => "56.750000 MHz",
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output_clock_frequency10 => "0 MHz",
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output_clock_frequency11 => "0 MHz",
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output_clock_frequency12 => "0 MHz",
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output_clock_frequency13 => "0 MHz",
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output_clock_frequency14 => "0 MHz",
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output_clock_frequency15 => "0 MHz",
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output_clock_frequency16 => "0 MHz",
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output_clock_frequency17 => "0 MHz",
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output_clock_frequency2 => "113.500000 MHz",
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output_clock_frequency3 => "0 MHz",
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output_clock_frequency4 => "0 MHz",
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output_clock_frequency5 => "0 MHz",
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output_clock_frequency6 => "0 MHz",
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output_clock_frequency7 => "0 MHz",
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output_clock_frequency8 => "0 MHz",
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output_clock_frequency9 => "0 MHz",
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phase_shift0 => "0 ps",
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phase_shift1 => "0 ps",
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phase_shift10 => "0 ps",
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phase_shift11 => "0 ps",
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phase_shift12 => "0 ps",
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phase_shift13 => "0 ps",
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phase_shift14 => "0 ps",
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phase_shift15 => "0 ps",
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phase_shift16 => "0 ps",
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phase_shift17 => "0 ps",
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phase_shift2 => "4405 ps",
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phase_shift3 => "0 ps",
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phase_shift4 => "0 ps",
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phase_shift5 => "0 ps",
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phase_shift6 => "0 ps",
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phase_shift7 => "0 ps",
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phase_shift8 => "0 ps",
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phase_shift9 => "0 ps",
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pll_auto_clk_sw_en => "false",
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pll_bwctrl => 0,
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pll_clk_loss_sw_en => "false",
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pll_clk_sw_dly => 0,
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pll_clkin_0_src => "clk_0",
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pll_clkin_1_src => "clk_0",
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pll_cp_current => 0,
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pll_dsm_out_sel => "1st_order",
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pll_extclk_0_cnt_src => "pll_extclk_cnt_src_vss",
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pll_extclk_1_cnt_src => "pll_extclk_cnt_src_vss",
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pll_fbclk_mux_1 => "glb",
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pll_fbclk_mux_2 => "fb_1",
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pll_fractional_cout => 24,
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pll_fractional_division => 1,
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pll_m_cnt_in_src => "ph_mux_clk",
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pll_manu_clk_sw_en => "false",
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pll_output_clk_frequency => "0 MHz",
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pll_slf_rst => "false",
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pll_subtype => "General",
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pll_type => "General",
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pll_vco_div => 1,
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pll_vcoph_div => 1,
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refclk1_frequency => "0 MHz",
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reference_clock_frequency => "5.0 MHz",
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sim_additional_refclk_cycles_to_lock => 0
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)
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PORT MAP (
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fbclk => wire_gnd,
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locked => wire_pll_altera_pll_altera_pll_i_1557_locked,
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outclk => wire_pll_altera_pll_altera_pll_i_1557_outclk,
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refclk => refclk,
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rst => rst
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);
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END RTL; --pll
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--synopsys translate_on
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--VALID FILE
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