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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY sram IS
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PORT
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(
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ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
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DIN : IN STD_LOGIC_vector(15 downto 0);
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WREN : IN STD_LOGIC;
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clk : in std_logic;
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reset_n : in std_logic;
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request : in std_logic;
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width_16bit : in std_logic;
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-- SRAM interface
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SRAM_ADDR: OUT STD_LOGIC_VECTOR(17 downto 0);
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SRAM_CE_N: OUT STD_LOGIC;
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SRAM_OE_N: OUT STD_LOGIC;
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SRAM_WE_N: OUT STD_LOGIC;
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SRAM_LB_N: OUT STD_LOGIC;
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SRAM_UB_N: OUT STD_LOGIC;
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SRAM_DQ: INOUT STD_LOGIC_VECTOR(15 downto 0);
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-- Provide data to system
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DOUT : OUT STD_LOGIC_VECTOR(15 downto 0);
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complete : out std_logic
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);
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END sram;
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-- TODO, implement 32-bit accesses in two cycles
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-- first cycle, capture inputs
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-- second cycle, sram access
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ARCHITECTURE slow OF sram IS
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signal oe_n_next : std_logic;
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signal oe_n_reg : std_logic;
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signal we_n_next : std_logic;
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signal we_n_reg : std_logic;
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signal data_next : std_logic_vector(15 downto 0);
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signal data_reg : std_logic_vector(15 downto 0);
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signal request_next : std_logic;
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signal request_reg : std_logic;
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signal low_byte : std_logic_vector(7 downto 0);
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BEGIN
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-- registers
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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oe_n_reg <= '1';
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we_n_reg <= '1';
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data_reg <= (others=>'0');
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request_reg <= '0';
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elsif (clk'event and clk='1') then
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oe_n_reg <= oe_n_next;
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we_n_reg <= we_n_next;
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data_reg <= data_next;
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request_reg <= request_next;
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end if;
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end process;
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-- next state
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process(din,wren,request,request_reg,width_16bit)
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begin
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data_next <= din;
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request_next <= '0';
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oe_n_next <= '0';
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we_n_next <= '1';
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if (width_16bit = '0') then
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data_next <= din(7 downto 0)&din(7 downto 0);
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end if;
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if (request = '1') then
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-- on second cycle do write - address/data stable by now guaranteed (normal timequest...)
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oe_n_next <= wren;
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we_n_next <= not(wren);
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request_next <= '1';
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end if;
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end process;
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LOW_BYTE <= SRAM_DQ(7 downto 0) when address(0)='0' else SRAM_DQ(15 downto 8);
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-- output
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SRAM_ADDR <= address(18 downto 1);
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SRAM_CE_N <= '0';
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SRAM_OE_N <= oe_n_reg;
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SRAM_WE_N <= we_n_reg;
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SRAM_LB_N <= not(width_16bit) and address(0);
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SRAM_UB_N <= not(width_16bit) and NOT(address(0));
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SRAM_DQ <= data_reg when we_n_reg = '0' else (others=>'Z');
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DOUT <= SRAM_DQ(15 downto 8)&LOW_BYTE;
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complete <= request_reg;
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--GPIO <= (others=>'0');
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END slow;
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--ARCHITECTURE fast OF sram IS
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-- signal we_n : std_logic;
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-- signal dq : std_logic_vector(7 downto 0);
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--
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--BEGIN
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-- we_n <= not(clk) nand WREN;
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-- dq <= SRAM_DQ(7 downto 0) when address(0)='0' else
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-- SRAM_DQ(15 downto 8);
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--
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-- -- output
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-- SRAM_ADDR <= ADDRESS(18 downto 1);
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-- --SRAM_ADDR <= ADDRESS(17 downto 0);
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-- SRAM_CE_N <= '0';
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-- SRAM_OE_N <= WREN;
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-- SRAM_WE_N <= we_n;
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--
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-- SRAM_LB_N <= ADDRESS(0);
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-- SRAM_UB_N <= NOT(ADDRESS(0));
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-- --SRAM_LB_N <= '0';
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-- --SRAM_UB_N <= '0';
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--
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-- DOUT <= dq;
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-- SRAM_DQ <= DIN&DIN when wren='1' else (others=>'Z');
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--
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-- -- immediate completion
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-- complete <= request;
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--END fast;
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