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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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library std_developerskit ; -- used for to_string
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-- use std_developerskit.std_iopak.all;
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entity antic_tb is
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end;
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architecture rtl of antic_tb is
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constant CLK_A_PERIOD : time := 1 us / (1.79*32);
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signal reset_n : std_logic;
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signal clk_a : std_logic;
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signal cpu_addr : std_logic_vector(15 downto 0);
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signal cpu_data_in : std_logic_vector(7 downto 0);
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signal cpu_wr_en : std_logic;
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signal memory_ready_antic : std_logic;
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signal memory_ready_cpu : std_logic;
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signal memory_data_in : std_logic_vector(7 downto 0);
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signal antic_enable_179 : std_logic;
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signal enable_179_memwait : std_logic;
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signal cpu_shared_enable : std_logic;
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signal an : std_logic_vector(2 downto 0);
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signal cc_out_orig : std_logic;
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signal cc_out_used : std_logic;
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signal cc_out_used_doubled : std_logic;
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signal fetch : std_logic;
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signal fetch_address : std_logic_vector(15 downto 0);
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signal refresh : std_logic;
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signal hcount : std_logic_vector(7 downto 0);
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begin
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p_clk_gen_a : process
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begin
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clk_a <= '1';
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wait for CLK_A_PERIOD/2;
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clk_a <= '0';
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wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
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end process;
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reset_n <= '0', '1' after 1000ns;
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-- signal cpu_addr : std_logic_vector(15 downto 0);
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-- signal cpu_data_in : std_logic_vector(7 downto 0);
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-- signal cpu_wr_en : std_logic;
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-- signal memory_ready_antic : std_logic;
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-- memory_ready_antic <= '0';
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-- signal memory_ready_cpu : std_logic;
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memory_ready_cpu <= cpu_shared_enable and not(fetch) and not(refresh);
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-- signal memory_data_in : std_logic_vector(7 downto 0);
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-- memory_data_in <= (others=>'0');
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-- signal an : std_logic_vector(2 downto 0);
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-- signal cc_out_orig : std_logic;
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-- signal cc_out_used : std_logic;
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-- signal cc_out_used_doubled : std_logic;
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-- signal fetch : std_logic;
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-- signal fetch_address : std_logic_vector(!5 downto 0);
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process_setup_antic : process
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begin
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cpu_wr_en <= '0';
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wait for 1100ns;
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wait until cpu_shared_enable = '1';
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cpu_wr_en <= '1';
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cpu_addr<= x"d402";
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cpu_data_in <= x"00";
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wait until cpu_shared_enable = '0';
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cpu_wr_en <= '0';
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wait until cpu_shared_enable = '1';
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cpu_wr_en <= '1';
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cpu_addr<= x"d403";
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cpu_data_in <= x"06";
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wait until cpu_shared_enable = '0';
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cpu_wr_en <= '0';
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wait until cpu_shared_enable = '1';
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cpu_wr_en <= '1';
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cpu_addr <= x"d400";
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cpu_data_in <= x"62";
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wait until cpu_shared_enable = '0';
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cpu_wr_en <= '0';
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wait until cpu_shared_enable = '1';
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wait for clk_a_period*7;
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cpu_wr_en <= '1';
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cpu_addr <= x"d40a";
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cpu_data_in <= x"11";
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wait for clk_a_period*1;
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cpu_wr_en <= '0';
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wait for 100000000us;
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end process;
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process_antic_dl_data : process
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variable fetch_pos : integer;
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type MEM is array(0 to 1000) of std_logic_vector(7 downto 0);
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variable fetch_data : MEM;
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begin
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-- fetch_data(0) := x"42";
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-- fetch_data(1) := x"11";
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-- fetch_data(2) := x"22";
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-- fetch_data(3) := x"33";
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-- fetch_data(4) := x"44";
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-- fetch_data(5) := x"55";
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-- fetch_data(6) := x"00";
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-- fetch_data(7) := x"07";
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-- fetch_data(8) := x"92"; -- char1
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-- fetch_data(9) := x"34"; -- char2
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-- fetch_data(10) := x"ff"; -- char1 data
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-- fetch_data(11) := x"d6"; -- char3
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-- fetch_data(12) := x"00"; -- char2 data
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-- fetch_data(13) := x"78"; -- char4
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-- fetch_data(14) := x"ff"; -- char3 data
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-- fetch_data(15):= x"12"; -- char5
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-- fetch_data(16):= x"00"; -- char4 data
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-- fetch_data(17):= x"12"; -- char6
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-- fetch_data(18):= x"a5"; -- char5 data
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-- fetch_data(19):= x"12"; -- char7
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-- fetch_data(20):= x"a5"; -- char6 data
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-- fetch_data(21):= x"12"; -- char8
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-- fetch_data(0) := x"42";
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-- fetch_data(1) := x"00";
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-- fetch_data(2) := x"07";
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-- fetch_data(3) := x"92"; -- char1
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-- fetch_data(4) := x"34"; -- char2
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-- fetch_data(5) := x"ff"; -- char1 data
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-- fetch_data(6) := x"d6"; -- char3
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-- fetch_data(7) := x"00"; -- char2 data
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-- fetch_data(8) := x"78"; -- char4
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-- fetch_data(9) := x"ff"; -- char3 data
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-- fetch_data(10):= x"12"; -- char5
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-- fetch_data(11):= x"00"; -- char4 data
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-- fetch_data(12):= x"12"; -- char6
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-- fetch_data(13):= x"a5"; -- char5 data
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-- fetch_data(14):= x"12"; -- char7
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-- fetch_data(15):= x"a5"; -- char6 data
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-- fetch_data(16):= x"12"; -- char8
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fetch_data(0) := x"42";
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fetch_data(1) := x"00";
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fetch_data(2) := x"07";
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fetch_data(3) := x"ff"; -- char1
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fetch_data(4) := x"55"; -- char2
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fetch_data(5) := x"ff"; -- char1 data
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fetch_data(6) := x"ff"; -- char3
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fetch_data(7) := x"ff"; -- char2 data
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fetch_data(8) := x"ff"; -- char4
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fetch_data(9) := x"ff"; -- char3 data
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fetch_data(10):= x"ff"; -- char5
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fetch_data(11):= x"ff"; -- char4 data
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fetch_data(12):= x"ff"; -- char6
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fetch_data(13):= x"ff"; -- char5 data
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fetch_data(14):= x"ff"; -- char7
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fetch_data(15):= x"ff"; -- char6 data
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fetch_data(16):= x"ff"; -- char8
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fetch_pos := 0;
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memory_ready_antic <= '0';
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memory_data_in <= (others=>'0');
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loop
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wait until fetch='1';
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--wait for fetch_delay(fetch_pos);
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--wait for clk_a_period*9;
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wait for clk_a_period*3;
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memory_data_in <= fetch_data(fetch_pos);
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memory_ready_antic <= '1';
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wait until fetch = '0';
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memory_ready_antic <= '0';
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memory_data_in <= (others=>'0');
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fetch_pos := fetch_pos +1;
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end loop;
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end process;
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enables : entity work.shared_enable
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GENERIC MAP(cycle_length => 16)
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PORT MAP(CLK => CLK_a,
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RESET_N => RESET_N,
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MEMORY_READY_CPU => MEMORY_READY_CPU,
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MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
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ANTIC_REFRESH => refresh,
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PAUSE_6502 => '0',
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THROTTLE_COUNT_6502 => "000001",
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ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
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oldcpu_enable => ENABLE_179_MEMWAIT,
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CPU_ENABLE_OUT => CPU_SHARED_ENABLE);
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antic1: entity work.antic
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generic map
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(
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cycle_length => 16
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)
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port map
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(
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CLK => clk_a,
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ADDR => cpu_addr(3 downto 0),
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CPU_DATA_IN => cpu_data_in, -- for writes
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WR_EN => cpu_wr_en,
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RESET_N => reset_n,
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MEMORY_READY_ANTIC => memory_ready_antic,
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MEMORY_READY_CPU => memory_ready_cpu,
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MEMORY_DATA_IN => memory_data_in, -- for fetches
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ANTIC_ENABLE_179 => antic_enable_179,
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PAL => '1',
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lightpen => '0',
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-- CPU interface
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DATA_OUT => open,
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NMI_N_OUT => open,
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ANTIC_READY => open,
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-- GTIA interface
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AN => an,
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COLOUR_CLOCK_ORIGINAL_OUT => cc_out_orig,
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COLOUR_CLOCK_OUT => cc_out_used,
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HIGHRES_COLOUR_CLOCK_OUT => cc_out_used_doubled,
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-- DMA fetch
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dma_fetch_out => fetch,
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dma_address_out => fetch_address,
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-- refresh
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refresh_out =>refresh,
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-- for debugging
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dma_clock_out => open,
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hcount_out => hcount,
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vcount_out => open
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);
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end rtl;
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