repo2/de1_5200/i2sslave.vhdl @ 461
| 176 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY i2sslave IS
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PORT
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(
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CLK : IN STD_LOGIC;
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BCLK : IN STD_LOGIC;
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DACLRC : IN STD_LOGIC;
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LEFT_IN : in std_logic_vector(15 downto 0);
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RIGHT_IN : in std_logic_vector(15 downto 0);
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MCLK_2 : OUT STD_LOGIC;
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DACDAT : OUT STD_LOGIC
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);
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END i2sslave;
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ARCHITECTURE vhdl OF i2sslave IS
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signal bclk_reg : std_logic;
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signal bclk_last_reg : std_logic;
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signal daclrc_reg : std_logic;
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signal daclrc_last_reg : std_logic;
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signal shiftreg_reg : std_logic_vector(15 downto 0);
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signal shiftreg_next : std_logic_vector(15 downto 0);
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signal CLK_FAKE : std_logic;
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BEGIN
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MCLK_2 <= CLK_FAKE; -- bad practice, but pll out of...
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-- Data read on bclk low->high transition
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-- daclrc is set on bclk high->low transition
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-- register inputs
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process(clk)
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begin
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if (clk'event and clk='1') then
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CLK_FAKE <= not(CLK_FAKE);
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end if;
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end process;
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process(CLK_FAKE)
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begin
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if (CLK_FAKE'event and CLK_FAKE='1') then
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bclk_reg <= bclk;
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bclk_last_reg <= bclk_reg;
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daclrc_reg <= daclrc;
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daclrc_last_reg <= daclrc_reg;
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shiftreg_reg <= shiftreg_next;
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end if;
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end process;
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-- sample on change to daclrc, shift out bit if required
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process(daclrc_reg,daclrc_last_reg,bclk_reg,shiftreg_reg,left_in,right_in,bclk_last_reg)
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variable reload : std_logic;
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begin
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reload := '0';
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shiftreg_next <= shiftreg_reg;
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if (daclrc_reg = '1' and daclrc_last_reg = '0') then
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shiftreg_next <= right_in;
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reload := '1';
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end if;
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if (daclrc_reg = '0' and daclrc_last_reg = '1') then
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shiftreg_next <= left_in;
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reload := '1';
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end if;
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if (bclk_reg = '0' and bclk_last_reg = '1' and reload='0') then
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shiftreg_next <= shiftreg_reg(14 downto 0)&'0';
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end if;
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end process;
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DACDAT <= shiftreg_reg(15);
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END vhdl;
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